Modules§
- ast
- bits
- Module that supports arbitrary width bit vectors The [Bits] type is used to capture values with arbitrarily large (but known) bit length
- block
- check_
connected - check_
error - check_
logic_ loops - check_
timing - check_
write_ inputs - clock
- code_
writer - constant
- constraint
- direction
- logic
- module_
defines - named_
path - path_
tools - prelude
- probe
- signal
- signed
- simulate
- synth
- timing
- top_
wrap - type_
descriptor - vcd_
probe - verilog_
gen - verilog_
visitor - yosys
Macros§
- clock
- The [clock!] macro is used to connect a set of devices to a common clock. The macro takes a variable number of arguments:
- sim_
assert - sim_
assert_ eq - simple_
sim - target_
path - vcd_
path - wait_
clock_ cycle - wait_
clock_ cycles - wait_
clock_ false - wait_
clock_ true