[−][src]Module ruspiro_register::system::aarch64::tcr_el2
TCR_EL2 - Translation Control Register EL2
Controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.
Usage Constraints
EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S) |
---|---|---|---|---|---|
- | - | - | R/W | R/W | R/W |
Modules
IRGN0 | AArch64 Inner cacheability attribute for memory associated with tlb walks using ttbr0_el2 |
ORGN0 | AArch64 Outer cacheability attribute for memory associated with tlb walks using ttbr0_el2 |
PS | AArch64 Physical address size |
SH0 | AArch64 Shareability attribute for memory associated with tlb walks using ttbr0_el2 |
T0SZ | AArch64 Size offset of the memory reagion addressed by ttbr0_el2 (size = 2^(64-t0sz)) |
TBI | AArch64 Top Byte Ignored |
TG0 | AArch64 Granule size for the ttbr0_el2 |
Functions
get | AArch64 Read the raw register contents using the appropriate assembly |
read | AArch64 Read the contents of a specific |
set | AArch64 Write the raw register contents using the appropriate contents |
write | AArch64 Update the contents of a register from the |