1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
/***********************************************************************************************************************
* Copyright (c) 2020 by the authors
*
* Author: André Borrmann <pspwizard@gmx.de>
* License: Apache License 2.0 / MIT
**********************************************************************************************************************/
//! # SCTLR_EL1 - System Control Register EL1
//!
//! Provides top level control of the system, including its memory system at EL1.
//!
//! ## Usage Constraints
//! EL0 | EL1 (NS) | EL1(S) | EL2 | EL3(NS) | EL3(S)
//! ----|----------|--------|-----|---------|-------
//! - | R/W | R/W | R/W | R/W | R/W
//!
use crate::register::*;
use crate::{define_aarch64_register, impl_system_register_rw};
define_aarch64_register! {
@sctlr_el1<u64> {
/// globally enable MMU
M OFFSET(0) [
DISABLE = 0,
ENABLE = 1
],
/// alignment fault check
A OFFSET(1) [
DISABLE = 0,
ENABLE = 1
],
/// global data cache
C OFFSET(2) [
DISABLE = 0,
ENABLE = 1
],
/// stack alignment checks
SA OFFSET(3) [
DISABLE = 0,
ENABLE = 1
],
/// El0 stack alignment checks
SA0 OFFSET(4) [
DISABLE = 0,
ENABLE = 1
],
/// CP15 barrier operations enabled ?
CP15EN OFFSET(5) [
DISABLE = 0,
ENABLE = 1
],
/// IT instructions disabled ?
ITD OFFSET(7) [
DISABLED = 1,
ENABLED = 0
],
/// SETEND instructions disabled ?
SED OFFSET(8) [
DISABLED = 1,
ENABLED = 0
],
/// Controls access to interrupt masks from EL0 if EL0 is using Aarch64
UMA OFFSET(9) [
DISABLED = 0,
ENABLED = 1
],
/// instruction cache
I OFFSET(12) [
DISABLE = 0,
ENABLE = 1
],
/// Enables access to the DC ZVA instruction at EL0
DZE OFFSET(14) [
DISABLED = 0,
ENABLED = 1
],
/// Enables EL0 access to the CTR_EL0 register in Aacrh64 mode
UCT OFFSET(15) [
DISABLED = 0,
ENABLED = 1
],
/// Non-trapping WFI instruction
NTWI OFFSET(17) [
/// WFI executions in EL0 are trapped to EL1
TRAP_EL1 = 0,
/// WFI executions in EL0 are executed as normal
NO_TRAP = 1
],
/// Non-trapping WFE instruction
NTWE OFFSET(18) [
/// WFE executions in EL0 are trapped to EL1
TRAP_EL1 = 0,
/// WFE executions in EL0 are executed as normal
NO_TRAP = 1
],
/// Force all memory regions with write permissions as XN
WXN OFFSET(19) [
DONT_FORCE = 0,
FORCE = 1
],
/// explicit data access endiannes at EL0
E0E OFFSET(24) [
/// data accesses at EL0 are little-endian
LTL_ENDIAN = 0,
/// data accesses at EL0 are big-endian
BIG_ENDIAN = 1
],
/// exception endiannes
EE OFFSET(25) [
LTL_ENDIAN = 0,
BIG_ENDIAN = 1
],
/// Enable EL0 access to cache maintenance instructions:
/// DC CVAU, DC CIVAC, DC CVAC and IC IVAU in Aarch64 mode
UCI OFFSET(26) [
DISABLED = 0,
ENABLED = 1
]
}
}