rtlil/syntax/
module.rs

1use super::*;
2use getset::*;
3
4#[derive(Debug)]
5pub enum ModuleStmt {
6    Empty,
7    Param(String),
8    ParamVal((String, Const)),
9    Wire(Wire),
10    Memory(Memory),
11    Cell(Cell),
12    Connect(Connect),
13    Process(Process),
14}
15
16#[derive(Debug, Default, Getters, MutGetters)]
17#[get = "pub"]
18#[get_mut = "pub"]
19pub struct Module {
20    ident: String,
21    attrs: HashMap<String, Const>,
22    params: HashMap<String, Const>,
23    wires: Vec<Wire>,
24    cells: Vec<Cell>,
25    processes: Vec<Process>,
26    memories: Vec<Memory>,
27    connects: Vec<Connect>,
28}
29
30impl Module {
31    pub fn new(ident: String, stmts: Vec<ModuleStmt>) -> Self {
32        let mut r = Self {
33            ident,
34            ..Self::default()
35        };
36        for stmt in stmts {
37            match stmt {
38                ModuleStmt::Param(n) => {
39                    r.params.insert(n, Const::Empty);
40                },
41                ModuleStmt::ParamVal((k, v)) => {
42                    r.params.insert(k, v);
43                },
44                ModuleStmt::Wire(n) => r.wires.push(n),
45                ModuleStmt::Cell(n) => r.cells.push(n),
46                ModuleStmt::Process(n) => r.processes.push(n),
47                ModuleStmt::Memory(n) => r.memories.push(n),
48                _ => (),
49            };
50        }
51        r
52    }
53}
54
55impl Visit for Module {
56    fn visit<F: Visitor>(&mut self, f: &mut F) -> Result<()> {
57        f.enter(Node::Module(self))?;
58        for n in self.wires.iter_mut() {
59            n.visit(f)?;
60        }
61        for n in self.cells.iter_mut() {
62            n.visit(f)?;
63        }
64        for n in self.processes.iter_mut() {
65            n.visit(f)?;
66        }
67        f.leave(Node::Module(self))?;
68        Ok(())
69    }
70}
rtlil/syntax/module.rs

rtlil/syntax/
module.rs
