Expand description
Yosys RTLIL text representation parsing library.
use rtlicious;
let src =
r#"module \test
wire $a;
end
"#;
let design = rtlicious::parse(src).unwrap();
assert_eq!(design.modules().len(), 1);Structs§
- Case
- Represents a case
- Cell
- Represents a logic cell
- Design
- A design is optional autoindex statement followed by zero or more modules.
- Memory
- Represents a memory cell
- Memwr
- Represents a memwr statement
- Module
- Represents a module A module is a collection of wires, memories, cells, processes, and connections
- Process
- Represents a process
- Switch
- Represents a switch
- Sync
- Represents a sync
- Wire
- Represents a wire
Enums§
- Case
Body - Represents a case body
- Constant
- Constant enum
- Id
- Identifier struct
- SigSpec
- Represents a signal specification
- Signal
Sync - Represents a
- SyncOn
- Represents a sync statement
Functions§
- parse
- Parse a RTLIL design from a type that implements
AsRef<str>.