[−][src]Type Definition rsl10_pac::rf::rf_reg2f::W

type W = W<u32, RF_REG2F>;

Writer for register RF_REG2F

Methods

impl W[src]

pub fn ck_div_1_6_ck_div_1_6(&mut self) -> CK_DIV_1_6_CK_DIV_1_6_W[src]

Bits 24:26 - Clock division factor for ck_div_1_6

pub fn pads_pe_ds_gpio_ds(&mut self) -> PADS_PE_DS_GPIO_DS_W[src]

Bit 22 - If set to 1 enables the increased drive strength of the digital pads

pub fn pads_pe_ds_gpio_pe(&mut self) -> PADS_PE_DS_GPIO_PE_W[src]

Bit 21 - If set to 1 enables the pull-up of the GPIO pads

pub fn pads_pe_ds_nreset_pe(&mut self) -> PADS_PE_DS_NRESET_PE_W[src]

Bit 20 - If set to 1 enables the pull-up of the nreset pad

pub fn pads_pe_ds_spi_miso_pe(&mut self) -> PADS_PE_DS_SPI_MISO_PE_W[src]

Bit 19 - If set to 1 enables the pull-up of the MISO SPI pad

pub fn pads_pe_ds_spi_mosi_pe(&mut self) -> PADS_PE_DS_SPI_MOSI_PE_W[src]

Bit 18 - If set to 1 enables the pull-up of the MOSI SPI pad

pub fn pads_pe_ds_spi_sclk_pe(&mut self) -> PADS_PE_DS_SPI_SCLK_PE_W[src]

Bit 17 - If set to 1 enables the pull-up of the SCLK SPI pad

pub fn pads_pe_ds_spi_cs_n_pe(&mut self) -> PADS_PE_DS_SPI_CS_N_PE_W[src]

Bit 16 - If set to 1 enables the pull-up of the CSN SPI pad

pub fn subband_fll_sb_fll_dither(&mut self) -> SUBBAND_FLL_SB_FLL_DITHER_W[src]

Bits 14:15 - Select the dithering: 00 no dithering, 01 PN9 positive, 10 PN10 negative, PN9+PN10

pub fn subband_fll_sb_fll_cic_tau(&mut self) -> SUBBAND_FLL_SB_FLL_CIC_TAU_W[src]

Bits 12:13 - Set the CIC decimator factor: 00 => 16, 01 => 32, 10 => 64, 11 => 128

pub fn subband_fll_sb_fll_ph_4_n8(&mut self) -> SUBBAND_FLL_SB_FLL_PH_4_N8_W[src]

Bit 11 - If set to 1, it uses only 4 phases in the frequency detector. Default 8 phases

pub fn subband_fll_sb_fll_wait(&mut self) -> SUBBAND_FLL_SB_FLL_WAIT_W[src]

Bits 8:10 - Set the number of CIC samples before stopping the FLL

pub fn sync_word_corr_en_sync_word_corr(
    &mut self
) -> SYNC_WORD_CORR_EN_SYNC_WORD_CORR_W[src]

Bit 7 - If set to 1 enable the sync word bias correction with RSSI detection

pub fn sync_word_corr_sync_word_bias(
    &mut self
) -> SYNC_WORD_CORR_SYNC_WORD_BIAS_W[src]

Bits 0:5 - set the sync word bias. Without the phADC rescaler, it's 8*mod_idx.