Type Definition rsl10_pac::rf::rf_reg18::R

type R = R<u32, RF_REG18>;

Reader of register RF_REG18

Methods

impl R

pub fn correct_cfreq_if_correct_cfreq_if(
    &self
) -> CORRECT_CFREQ_IF_CORRECT_CFREQ_IF_R

Bits 16:31 - Unsigned value that specifies the IF for the Rx mode.

pub fn rssi_bank_rssi_tri_ck_div(&self) -> RSSI_BANK_RSSI_TRI_CK_DIV_R

Bits 14:15 - Speed on the RSSI triangular dithering signal (cf reg RSSI_TUN)

pub fn rssi_bank_fast_rssi(&self) -> RSSI_BANK_FAST_RSSI_R

Bit 13 - If set to 1, the RSSI filtering is 8x faster

pub fn rssi_bank_en_fast_pre_sync(&self) -> RSSI_BANK_EN_FAST_PRE_SYNC_R

Bit 12 - If the packet mode is set, indicates to switch the fast modes during the preamble reception

pub fn rssi_bank_tau_rssi_filtering(&self) -> RSSI_BANK_TAU_RSSI_FILTERING_R

Bits 8:11 - Time constant of the RSSI filtering block: 0: 4symbols, 1: 8symbols, 2: 16 symbols, 3: 32symbols, 4: 64symbols, 5: 128symbols, 6: 256symbols, 7: 512symbols, 8: 1024symbols

pub fn decision_use_vit_soft(&self) -> DECISION_USE_VIT_SOFT_R

Bit 4 - If set to 1 uses the viterbi soft decoding

pub fn decision_viterbi_len(&self) -> DECISION_VITERBI_LEN_R

Bits 2:3 - Sets the Viterbi path length: 00: 1 bit, 01: 2 bits, 10: 4 bits, 11: 8 bits

pub fn decision_viterbi_pow_nlin(&self) -> DECISION_VITERBI_POW_NLIN_R

Bit 1 - if set to 1, the Viterbi algorithm uses power instead of amplitude to evaluate the error on the path

pub fn decision_en_viterbi_gfsk(&self) -> DECISION_EN_VITERBI_GFSK_R

Bit 0 - If set to 1 enables the Viterbi algorithm for the GFSK decoding; this will override the old ISI correction algorithm.