Type Definition rsl10_pac::rf::rf_reg07::W

type W = W<u32, RF_REG07>;

Writer for register RF_REG07

Methods

impl W

pub fn channels_1_channel_spacing_lo(
    &mut self
) -> CHANNELS_1_CHANNEL_SPACING_LO_W

Bits 16:31 - channel spacing: the formula that determines this value is the same as for the central frequency. v=ch_sp/144e6*2^25

pub fn mod_info_rx_en_div_2_n3_rx(&mut self) -> MOD_INFO_RX_EN_DIV_2_N3_RX_W

Bit 14 - If set to 1 the clock divider will provide a clock divided by 2 instead of 3.

pub fn mod_info_rx_symbol_2bit_rx(&mut self) -> MOD_INFO_RX_SYMBOL_2BIT_RX_W

Bit 13 - If set to 1, each symbol is composed by 2 bits (OQPSK or 4FSK)

pub fn mod_info_rx_dr_m_rx(&mut self) -> MOD_INFO_RX_DR_M_RX_W

Bits 8:12 - Unsigned value that determine the oversampling frequency and consequently the data-rate. This frequency is the system frequency (16 or 24 MHz) divided by this value+1.

pub fn mod_info_tx_en_div_2_n3_tx(&mut self) -> MOD_INFO_TX_EN_DIV_2_N3_TX_W

Bit 6 - If set to 1 the clock divider will provide a clock divided by 2 instead of 3.

pub fn mod_info_tx_symbol_2bit_tx(&mut self) -> MOD_INFO_TX_SYMBOL_2BIT_TX_W

Bit 5 - If set to 1, each symbol is composed by 2 bits (OQPSK or 4FSK)

pub fn mod_info_tx_dr_m_tx(&mut self) -> MOD_INFO_TX_DR_M_TX_W

Bits 0:4 - Unsigned value that determine the oversampling frequency and consequently the data-rate. This frequency is the system frequency (16 or 24 MHz) divided by this value+1.