[][src]Enum rsl10_pac::clk::clk_sys_cfg::SYSCLK_SRC_SEL_A

#[repr(u8)]
pub enum SYSCLK_SRC_SEL_A {
    SYSCLK_CLKSRC_RCCLK,
    SYSCLK_CLKSRC_STANDBYCLK,
    SYSCLK_CLKSRC_RFCLK,
    SYSCLK_CLKSRC_EXTCLK,
    SYSCLK_CLKSRC_JTCK,
}

Controls the source of the system clock : JTCK, RFCLK, RCCLK, EXTCLK or STANDBYCLK

Value on reset: 0

Variants

SYSCLK_CLKSRC_RCCLK

0: Select the RCCLK clock as SYSCLK clock source

SYSCLK_CLKSRC_STANDBYCLK

1: Select the STANDBYCLK clock as SYSCLK clock source

SYSCLK_CLKSRC_RFCLK

2: Select the RFCLK clock as SYSCLK clock source

SYSCLK_CLKSRC_EXTCLK

3: Select the EXTCLK clock as SYSCLK clock source

SYSCLK_CLKSRC_JTCK

4: Select the JTCK clock as SYSCLK clock source

Trait Implementations

impl Clone for SYSCLK_SRC_SEL_A[src]

impl Copy for SYSCLK_SRC_SEL_A[src]

impl Debug for SYSCLK_SRC_SEL_A[src]

impl From<SYSCLK_SRC_SEL_A> for u8[src]

impl PartialEq<SYSCLK_SRC_SEL_A> for SYSCLK_SRC_SEL_A[src]

impl StructuralPartialEq for SYSCLK_SRC_SEL_A[src]

Auto Trait Implementations

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impl<T> Any for T where
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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type Output = T

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type Error = Infallible

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    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

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