[][src]Type Definition rsl10_pac::clk::clk_div_cfg2::R

type R = R<u32, CLK_DIV_CFG2>;

Reader of register CLK_DIV_CFG2

Methods

impl R[src]

pub fn cpclk_disable(&self) -> CPCLK_DISABLE_R[src]

Bit 15 - Charge pump clock disable

pub fn cpclk_prescale(&self) -> CPCLK_PRESCALE_R[src]

Bits 8:13 - Prescale value for the charge pump clock from the SLOWCLK clock (1 to 64 in steps of 1)

pub fn dcclk_disable(&self) -> DCCLK_DISABLE_R[src]

Bit 7 - DC-DC converter clock disable

pub fn dcclk_prescale(&self) -> DCCLK_PRESCALE_R[src]

Bits 0:5 - Prescale value for the DC-DC converter clock (1 to 64 in steps of 1)