Type Definition rsl10_pac::clk::clk_div_cfg1::R

type R = R<u32, CLK_DIV_CFG1>;

Reader of register CLK_DIV_CFG1

Methods

impl R

pub fn audioslowclk_prescale(&self) -> AUDIOSLOWCLK_PRESCALE_R

Bits 30:31 - Prescale value for the slow audio clock down from the fast audio clock (1 to 4 in steps of 1)

pub fn audioclk_prescale(&self) -> AUDIOCLK_PRESCALE_R

Bits 24:29 - Prescale value for the fast audio clock (1 to 64 in steps of 1)

pub fn uartclk_prescale(&self) -> UARTCLK_PRESCALE_R

Bits 16:20 - Prescale value for the UART peripheral clock (1 to 32 in steps of 1)

pub fn pwm1clk_prescale(&self) -> PWM1CLK_PRESCALE_R

Bits 8:13 - Prescale value for the PWM1 peripheral clock (1 to 64 in steps of 1)

pub fn pwm0clk_prescale(&self) -> PWM0CLK_PRESCALE_R

Bits 0:5 - Prescale value for the PWM0 peripheral clock (1 to 64 in steps of 1)