[][src]Enum rsl10_pac::acs::acs_aout_ctrl::TEST_AOUT_A

#[repr(u8)]
pub enum TEST_AOUT_A {
    AOUT_VSSA,
    AOUT_VCC_SENSE,
    AOUT_VREF_0P75V_OUTPUT,
    AOUT_VREF_0P67V_OUTPUT,
    AOUT_IREF_50N_OUTPUT,
    AOUT_IREF_1N_OUTPUT,
    AOUT_VDDACS_OUTPUT,
    AOUT_VREF_0P75V_BUF_OUTPUT,
    AOUT_VREG_BG,
    AOUT_VDDRF_SW,
    AOUT_VDDRF_SENSE,
    AOUT_VDDT,
    AOUT_VDDC_SENSE,
    AOUT_VDDA_SW,
    AOUT_VDDA_SENSE,
    AOUT_VDDM_SENSE,
    AOUT_NC,
    AOUT_VDDPA_SENSE,
    AOUT_VDDPA_ISENSE,
    AOUT_TM0,
    AOUT_BG_READY,
    AOUT_VCC_READY,
    AOUT_DCDC_OVERLOAD,
    AOUT_DCDC_ACTIVATED,
    AOUT_VDDRF_READY,
    AOUT_VDDC_READY,
    AOUT_VDDM_READY,
    AOUT_VDDA_READY,
    AOUT_CLK_PRESENT,
    AOUT_XTAL_OK,
    AOUT_XTAL_CLK,
    AOUT_CLK_32K,
}

AOUT test signal selection

Value on reset: 0

Variants

AOUT_VSSA

0: AOUT grounded

AOUT_VCC_SENSE

1: AOUT high / VCC connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_VREF_0P75V_OUTPUT

2: Bandgap reference voltage 0p75V connected on AOUT

AOUT_VREF_0P67V_OUTPUT

3: Bandgap reference voltage 0p67V connected on AOUT

AOUT_IREF_50N_OUTPUT

4: Bandgap iref current source connected on AOUT

AOUT_IREF_1N_OUTPUT

5: PTAT iref current source connected on AOUT

AOUT_VDDACS_OUTPUT

6: vddacs voltage connected on AOUT

AOUT_VREF_0P75V_BUF_OUTPUT

7: Bandgap buffered reference voltage 0p75V connected on AOUT

AOUT_VREG_BG

8: Bandgap regulated supply voltage

AOUT_VDDRF_SW

9: vddrf_sw voltage connected on AOUT

AOUT_VDDRF_SENSE

10: VDDRF connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_VDDT

11: Baseband timer supply voltage

AOUT_VDDC_SENSE

12: VDDC connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_VDDA_SW

13: vdda_sw voltage connected on AOUT

AOUT_VDDA_SENSE

14: VDDA connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_VDDM_SENSE

15: VDDM connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_NC

16: AOUT floating (for pad leakage measurement)

AOUT_VDDPA_SENSE

17: VDDPA connected on AOUT (can be sensed for 4 wires measurement of the load regulation)

AOUT_VDDPA_ISENSE

18: VDDPA current sensing circuit connected to AOUT

AOUT_TM0

19: Flash TM0 connected to AOUT

AOUT_BG_READY

20: Bandgap ready on AOUT (digital signal using VSSA and VCC states)

AOUT_VCC_READY

21: vcc_ready on AOUT (digital signal using VSSA and VCC states)

AOUT_DCDC_OVERLOAD

22: dcdc_overload on AOUT (digital signal using VSSA and VCC states)

AOUT_DCDC_ACTIVATED

23: dcdc_activated on AOUT (digital signal using VSSA and VCC states)

AOUT_VDDRF_READY

24: vddrf_ready on AOUT (digital signal using VSSA and VCC states)

AOUT_VDDC_READY

25: vddc_ready on AOUT (digital signal using VSSA and VCC states)

AOUT_VDDM_READY

26: vddm_ready on AOUT (digital signal using VSSA and VCC states)

AOUT_VDDA_READY

27: vdda_ready on AOUT (digital signal using VSSA and VCC states)

AOUT_CLK_PRESENT

28: Clock present from clock detector on AOUT (digital signal using VSSA and VCC states)

AOUT_XTAL_OK

29: XTAL ok on AOUT (digital signal using VSSA and VCC states)

AOUT_XTAL_CLK

30: XTAL clock on AOUT (digital signal using VSSA and VCC states)

AOUT_CLK_32K

31: 32 kHz RC oscillator clock on AOUT (digital signal using VSSA and VCC states)

Trait Implementations

impl Clone for TEST_AOUT_A[src]

impl Copy for TEST_AOUT_A[src]

impl Debug for TEST_AOUT_A[src]

impl From<TEST_AOUT_A> for u8[src]

impl PartialEq<TEST_AOUT_A> for TEST_AOUT_A[src]

impl StructuralPartialEq for TEST_AOUT_A[src]

Auto Trait Implementations

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impl<T> Any for T where
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    T: ?Sized
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    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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type Output = T

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type Error = Infallible

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impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

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