[−][src]Enum rsl10_pac::acs::acs_aout_ctrl::TEST_AOUT_A
AOUT test signal selection
Value on reset: 0
Variants
0: AOUT grounded
1: AOUT high / VCC connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
2: Bandgap reference voltage 0p75V connected on AOUT
3: Bandgap reference voltage 0p67V connected on AOUT
4: Bandgap iref current source connected on AOUT
5: PTAT iref current source connected on AOUT
6: vddacs voltage connected on AOUT
7: Bandgap buffered reference voltage 0p75V connected on AOUT
8: Bandgap regulated supply voltage
9: vddrf_sw voltage connected on AOUT
10: VDDRF connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
11: Baseband timer supply voltage
12: VDDC connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
13: vdda_sw voltage connected on AOUT
14: VDDA connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
15: VDDM connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
16: AOUT floating (for pad leakage measurement)
17: VDDPA connected on AOUT (can be sensed for 4 wires measurement of the load regulation)
18: VDDPA current sensing circuit connected to AOUT
19: Flash TM0 connected to AOUT
20: Bandgap ready on AOUT (digital signal using VSSA and VCC states)
21: vcc_ready on AOUT (digital signal using VSSA and VCC states)
22: dcdc_overload on AOUT (digital signal using VSSA and VCC states)
23: dcdc_activated on AOUT (digital signal using VSSA and VCC states)
24: vddrf_ready on AOUT (digital signal using VSSA and VCC states)
25: vddc_ready on AOUT (digital signal using VSSA and VCC states)
26: vddm_ready on AOUT (digital signal using VSSA and VCC states)
27: vdda_ready on AOUT (digital signal using VSSA and VCC states)
28: Clock present from clock detector on AOUT (digital signal using VSSA and VCC states)
29: XTAL ok on AOUT (digital signal using VSSA and VCC states)
30: XTAL clock on AOUT (digital signal using VSSA and VCC states)
31: 32 kHz RC oscillator clock on AOUT (digital signal using VSSA and VCC states)
Trait Implementations
impl Clone for TEST_AOUT_A
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fn clone(&self) -> TEST_AOUT_A
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fn clone_from(&mut self, source: &Self)
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impl Copy for TEST_AOUT_A
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impl Debug for TEST_AOUT_A
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impl From<TEST_AOUT_A> for u8
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fn from(variant: TEST_AOUT_A) -> Self
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impl PartialEq<TEST_AOUT_A> for TEST_AOUT_A
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fn eq(&self, other: &TEST_AOUT_A) -> bool
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#[must_use]
fn ne(&self, other: &Rhs) -> bool
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impl StructuralPartialEq for TEST_AOUT_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,