Struct rsl10_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _SYSCTRL_DSS_CTRL>>

pub fn dss_css_int_reset(&mut self) -> DSS_CSS_INT_RESET_W

Bit 5 - Write a 1 to reset pending CSS interrupts in the DSS interrupt controller

pub fn dss_dma_int_reset(&mut self) -> DSS_DMA_INT_RESET_W

Bit 4 - Write a 1 to reset pending DMA interrupts in the DSS interrupt controller

pub fn dss_reset(&mut self) -> DSS_RESET_W

Bit 3 - Write a 1 to reset DSS

pub fn lpdsp32_pause(&mut self) -> LPDSP32_PAUSE_W

Bit 2 - Write a 1 to pause LPDSP32

pub fn lpdsp32_resume(&mut self) -> LPDSP32_RESUME_W

Bit 1 - Write a 1 to run LPDSP32

impl W<u32, Reg<u32, _SYSCTRL_DSS_CMD>>

pub fn dss_cmd_6(&mut self) -> DSS_CMD_6_W

Bit 6 - Write a 1 to issue DSS command 6

pub fn dss_cmd_5(&mut self) -> DSS_CMD_5_W

Bit 5 - Write a 1 to issue DSS command 5

pub fn dss_cmd_4(&mut self) -> DSS_CMD_4_W

Bit 4 - Write a 1 to issue DSS command 4

pub fn dss_cmd_3(&mut self) -> DSS_CMD_3_W

Bit 3 - Write a 1 to issue DSS command 3

pub fn dss_cmd_2(&mut self) -> DSS_CMD_2_W

Bit 2 - Write a 1 to issue DSS command 2

pub fn dss_cmd_1(&mut self) -> DSS_CMD_1_W

Bit 1 - Write a 1 to issue DSS command 1

pub fn dss_cmd_0(&mut self) -> DSS_CMD_0_W

Bit 0 - Write a 1 to issue DSS command 0

impl W<u32, Reg<u32, _SYSCTRL_FLASH_OVERLAY_CFG>>

pub fn dsp_pram0_overlay_cfg(&mut self) -> DSP_PRAM0_OVERLAY_CFG_W

Bit 7 - DSP_PRAM0 Flash overlay configuration

pub fn dsp_pram1_overlay_cfg(&mut self) -> DSP_PRAM1_OVERLAY_CFG_W

Bit 6 - DSP_PRAM1 Flash overlay configuration

pub fn dsp_pram2_overlay_cfg(&mut self) -> DSP_PRAM2_OVERLAY_CFG_W

Bit 5 - DSP_PRAM2 Flash overlay configuration

pub fn dsp_pram3_overlay_cfg(&mut self) -> DSP_PRAM3_OVERLAY_CFG_W

Bit 4 - DSP_PRAM3 Flash overlay configuration

pub fn pram3_overlay_cfg(&mut self) -> PRAM3_OVERLAY_CFG_W

Bit 3 - PRAM3 Flash overlay configuration

pub fn pram2_overlay_cfg(&mut self) -> PRAM2_OVERLAY_CFG_W

Bit 2 - PRAM2 Flash overlay configuration

pub fn pram1_overlay_cfg(&mut self) -> PRAM1_OVERLAY_CFG_W

Bit 1 - PRAM1 Flash overlay configuration

pub fn pram0_overlay_cfg(&mut self) -> PRAM0_OVERLAY_CFG_W

Bit 0 - PRAM0 Flash overlay configuration

impl W<u32, Reg<u32, _SYSCTRL_CSS_LOOP_CACHE_CFG>>

pub fn css_loop_cache_enable(&mut self) -> CSS_LOOP_CACHE_ENABLE_W

Bit 0 - CSS loop cache enable

impl W<u32, Reg<u32, _SYSCTRL_DSS_LOOP_CACHE_CFG>>

pub fn dss_loop_cache_enable(&mut self) -> DSS_LOOP_CACHE_ENABLE_W

Bit 0 - DSS loop cache enable

impl W<u32, Reg<u32, _SYSCTRL_MEM_ERROR>>

pub fn mem_error_clear(&mut self) -> MEM_ERROR_CLEAR_W

Bit 5 - Write a 1 to clear the memory error flags

impl W<u32, Reg<u32, _SYSCTRL_MEM_POWER_CFG>>

pub fn dsp_dram5_power(&mut self) -> DSP_DRAM5_POWER_W

Bit 21 - DSP PRAM0 power configuration

pub fn dsp_dram4_power(&mut self) -> DSP_DRAM4_POWER_W

Bit 20 - DSP PRAM0 power configuration

pub fn dsp_dram3_power(&mut self) -> DSP_DRAM3_POWER_W

Bit 19 - DSP PRAM0 power configuration

pub fn dsp_dram2_power(&mut self) -> DSP_DRAM2_POWER_W

Bit 18 - DSP PRAM0 power configuration

pub fn dsp_dram1_power(&mut self) -> DSP_DRAM1_POWER_W

Bit 17 - DSP PRAM0 power configuration

pub fn dsp_dram0_power(&mut self) -> DSP_DRAM0_POWER_W

Bit 16 - DSP PRAM0 power configuration

pub fn dsp_pram3_power(&mut self) -> DSP_PRAM3_POWER_W

Bit 15 - DSP PRAM0 power configuration

pub fn dsp_pram2_power(&mut self) -> DSP_PRAM2_POWER_W

Bit 14 - DSP PRAM0 power configuration

pub fn dsp_pram1_power(&mut self) -> DSP_PRAM1_POWER_W

Bit 13 - DSP PRAM0 power configuration

pub fn dsp_pram0_power(&mut self) -> DSP_PRAM0_POWER_W

Bit 12 - DSP PRAM0 power configuration

pub fn bb_dram1_power(&mut self) -> BB_DRAM1_POWER_W

Bit 11 - Baseband DRAM1 power configuration

pub fn bb_dram0_power(&mut self) -> BB_DRAM0_POWER_W

Bit 10 - Baseband DRAM0 power configuration

pub fn dram2_power(&mut self) -> DRAM2_POWER_W

Bit 8 - DRAM2 power configuration

pub fn dram1_power(&mut self) -> DRAM1_POWER_W

Bit 7 - DRAM1 power configuration

pub fn dram0_power(&mut self) -> DRAM0_POWER_W

Bit 6 - DRAM0 power configuration

pub fn pram3_power(&mut self) -> PRAM3_POWER_W

Bit 5 - PRAM3 power configuration

pub fn pram2_power(&mut self) -> PRAM2_POWER_W

Bit 4 - PRAM2 power configuration

pub fn pram1_power(&mut self) -> PRAM1_POWER_W

Bit 3 - PRAM1 power configuration

pub fn pram0_power(&mut self) -> PRAM0_POWER_W

Bit 2 - PRAM0 power configuration

pub fn flash_power(&mut self) -> FLASH_POWER_W

Bit 1 - Flash power configuration

pub fn prom_power(&mut self) -> PROM_POWER_W

Bit 0 - PROM power configuration

impl W<u32, Reg<u32, _SYSCTRL_MEM_ACCESS_CFG>>

pub fn wakeup_addr_packed(&mut self) -> WAKEUP_ADDR_PACKED_W

Bits 24:30 - Wakeup restore address in packed 7-bit format. When written, SYSCTRL_WAKEUP_ADDR is updated. This field reads back as zero when SYSCTRL_WAKEUP_ADDR does not point to an enabled RAM instance.

pub fn dsp_dram5_access(&mut self) -> DSP_DRAM5_ACCESS_W

Bit 21 - DSP PRAM0 access configuration

pub fn dsp_dram4_access(&mut self) -> DSP_DRAM4_ACCESS_W

Bit 20 - DSP PRAM0 access configuration

pub fn dsp_dram3_access(&mut self) -> DSP_DRAM3_ACCESS_W

Bit 19 - DSP PRAM0 access configuration

pub fn dsp_dram2_access(&mut self) -> DSP_DRAM2_ACCESS_W

Bit 18 - DSP PRAM0 access configuration

pub fn dsp_dram1_access(&mut self) -> DSP_DRAM1_ACCESS_W

Bit 17 - DSP PRAM0 access configuration

pub fn dsp_dram0_access(&mut self) -> DSP_DRAM0_ACCESS_W

Bit 16 - DSP PRAM0 access configuration

pub fn dsp_pram3_access(&mut self) -> DSP_PRAM3_ACCESS_W

Bit 15 - DSP PRAM0 access configuration

pub fn dsp_pram2_access(&mut self) -> DSP_PRAM2_ACCESS_W

Bit 14 - DSP PRAM0 access configuration

pub fn dsp_pram1_access(&mut self) -> DSP_PRAM1_ACCESS_W

Bit 13 - DSP PRAM0 access configuration

pub fn dsp_pram0_access(&mut self) -> DSP_PRAM0_ACCESS_W

Bit 12 - DSP PRAM0 access configuration

pub fn bb_dram1_access(&mut self) -> BB_DRAM1_ACCESS_W

Bit 11 - Baseband DRAM1 access configuration

pub fn bb_dram0_access(&mut self) -> BB_DRAM0_ACCESS_W

Bit 10 - Baseband DRAM0 access configuration

pub fn dram2_access(&mut self) -> DRAM2_ACCESS_W

Bit 8 - DRAM2 access configuration

pub fn dram1_access(&mut self) -> DRAM1_ACCESS_W

Bit 7 - DRAM1 access configuration

pub fn dram0_access(&mut self) -> DRAM0_ACCESS_W

Bit 6 - DRAM0 access configuration

pub fn pram3_access(&mut self) -> PRAM3_ACCESS_W

Bit 5 - PRAM3 access configuration

pub fn pram2_access(&mut self) -> PRAM2_ACCESS_W

Bit 4 - PRAM2 access configuration

pub fn pram1_access(&mut self) -> PRAM1_ACCESS_W

Bit 3 - PRAM1 access configuration

pub fn pram0_access(&mut self) -> PRAM0_ACCESS_W

Bit 2 - PRAM0 access configuration

pub fn flash_access(&mut self) -> FLASH_ACCESS_W

Bit 1 - Flash access configuration

pub fn prom_access(&mut self) -> PROM_ACCESS_W

Bit 0 - PROM access configuration

impl W<u32, Reg<u32, _SYSCTRL_WAKEUP_ADDR>>

pub fn wakeup_addr(&mut self) -> WAKEUP_ADDR_W

Bits 0:31 - Wakeup restore address in unpacked 32-bit format. When written, the WAKEUP_ADDR_PACKED field of SYSCTRL_MEM_ACCESS_CFG is updated. Bits 0-12 must be 0x0000 or 0x1FE8 (top or bottom of memory instance). Bits 17-20, 22-28 and 30-31 must be zero. When the WAKEUP_ADDR_PACKED field does not point to memory that is currently accessible, then SYSCTRL_WAKEUP_ADDR reads back as all zeros.

impl W<u32, Reg<u32, _SYSCTRL_MEM_RETENTION_CFG>>

pub fn dsp_dram5_retention(&mut self) -> DSP_DRAM5_RETENTION_W

Bit 21 - DSP PRAM0 retention configuration

pub fn dsp_dram4_retention(&mut self) -> DSP_DRAM4_RETENTION_W

Bit 20 - DSP PRAM0 retention configuration

pub fn dsp_dram3_retention(&mut self) -> DSP_DRAM3_RETENTION_W

Bit 19 - DSP PRAM0 retention configuration

pub fn dsp_dram2_retention(&mut self) -> DSP_DRAM2_RETENTION_W

Bit 18 - DSP PRAM0 retention configuration

pub fn dsp_dram1_retention(&mut self) -> DSP_DRAM1_RETENTION_W

Bit 17 - DSP PRAM0 retention configuration

pub fn dsp_dram0_retention(&mut self) -> DSP_DRAM0_RETENTION_W

Bit 16 - DSP PRAM0 retention configuration

pub fn dsp_pram3_retention(&mut self) -> DSP_PRAM3_RETENTION_W

Bit 15 - DSP PRAM0 retention configuration

pub fn dsp_pram2_retention(&mut self) -> DSP_PRAM2_RETENTION_W

Bit 14 - DSP PRAM0 retention configuration

pub fn dsp_pram1_retention(&mut self) -> DSP_PRAM1_RETENTION_W

Bit 13 - DSP PRAM0 retention configuration

pub fn dsp_pram0_retention(&mut self) -> DSP_PRAM0_RETENTION_W

Bit 12 - DSP PRAM0 retention configuration

pub fn bb_dram1_retention(&mut self) -> BB_DRAM1_RETENTION_W

Bit 11 - Baseband DRAM1 retention configuration

pub fn bb_dram0_retention(&mut self) -> BB_DRAM0_RETENTION_W

Bit 10 - Baseband DRAM0 retention configuration

pub fn dram2_retention(&mut self) -> DRAM2_RETENTION_W

Bit 8 - DRAM2 retention configuration

pub fn dram1_retention(&mut self) -> DRAM1_RETENTION_W

Bit 7 - DRAM1 retention configuration

pub fn dram0_retention(&mut self) -> DRAM0_RETENTION_W

Bit 6 - DRAM0 retention configuration

pub fn pram3_retention(&mut self) -> PRAM3_RETENTION_W

Bit 5 - PRAM3 retention configuration

pub fn pram2_retention(&mut self) -> PRAM2_RETENTION_W

Bit 4 - PRAM2 retention configuration

pub fn pram1_retention(&mut self) -> PRAM1_RETENTION_W

Bit 3 - PRAM1 retention configuration

pub fn pram0_retention(&mut self) -> PRAM0_RETENTION_W

Bit 2 - PRAM0 retention configuration

impl W<u32, Reg<u32, _SYSCTRL_MEM_ARBITER_CFG>>

pub fn dsp_dram45_arbiter(&mut self) -> DSP_DRAM45_ARBITER_W

Bits 28:29 - DSP DRAM4 and DRAM5 arbiter configuration

pub fn dsp_dram23_arbiter(&mut self) -> DSP_DRAM23_ARBITER_W

Bits 26:27 - DSP DRAM2 and DRAM3 arbiter configuration

pub fn dsp_dram01_arbiter(&mut self) -> DSP_DRAM01_ARBITER_W

Bits 24:25 - DSP DRAM0 and DRAM1 arbiter configuration

pub fn dsp_pram3_arbiter(&mut self) -> DSP_PRAM3_ARBITER_W

Bits 22:23 - DSP PRAM3 arbiter configuration

pub fn dsp_pram2_arbiter(&mut self) -> DSP_PRAM2_ARBITER_W

Bits 20:21 - DSP PRAM2 arbiter configuration

pub fn dsp_pram1_arbiter(&mut self) -> DSP_PRAM1_ARBITER_W

Bits 18:19 - DSP PRAM1 arbiter configuration

pub fn dsp_pram0_arbiter(&mut self) -> DSP_PRAM0_ARBITER_W

Bits 16:17 - DSP PRAM0 arbiter configuration

pub fn bb_dram1_arbiter(&mut self) -> BB_DRAM1_ARBITER_W

Bits 10:11 - Baseband DRAM1 arbiter configuration

pub fn bb_dram0_arbiter(&mut self) -> BB_DRAM0_ARBITER_W

Bits 8:9 - Baseband DRAM0 arbiter configuration

pub fn dram12_arbiter(&mut self) -> DRAM12_ARBITER_W

Bits 4:5 - DRAM1 and DRAM2 arbiter configuration

pub fn dram0_arbiter(&mut self) -> DRAM0_ARBITER_W

Bit 2 - DRAM0 arbiter configuration

pub fn pram_arbiter(&mut self) -> PRAM_ARBITER_W

Bit 1 - PRAM0 to PRAM3 arbiter configuration

pub fn round_robin_token(&mut self) -> ROUND_ROBIN_TOKEN_W

Bit 0 - Round-robin token generation configuration

impl W<u32, Reg<u32, _SYSCTRL_MEM_TIMING_CFG>>

pub fn dsp_pram_emaw(&mut self) -> DSP_PRAM_EMAW_W

Bits 8:9 - DSP_PRAM extra write margin configuration

pub fn dsp_pram_ema(&mut self) -> DSP_PRAM_EMA_W

Bits 4:6 - DSP_PRAM extra margin configuration

pub fn prom_ken(&mut self) -> PROM_KEN_W

Bit 3 - PROM bitlines keeper configuration

pub fn prom_ema(&mut self) -> PROM_EMA_W

Bits 0:2 - PROM extra margin configuration

impl W<u32, Reg<u32, _SYSCTRL_CNT_CTRL>>

pub fn cnt_clear(&mut self) -> CNT_CLEAR_W

Bit 2 - Clear activity counters

pub fn cnt_stop(&mut self) -> CNT_STOP_W

Bit 1 - Stop activity counters

pub fn cnt_start(&mut self) -> CNT_START_W

Bit 0 - Start activity counters

impl W<u32, Reg<u32, _SYSCTRL_SYSCLK_CNT>>

pub fn sysclk_cnt(&mut self) -> SYSCLK_CNT_W

Bits 0:31 - System clock counter value

impl W<u32, Reg<u32, _SYSCTRL_CM3_CNT>>

pub fn cm3_cnt(&mut self) -> CM3_CNT_W

Bits 0:31 - CM3 activity counter value

impl W<u32, Reg<u32, _SYSCTRL_LPDSP32_CNT>>

pub fn lpdsp32_cnt(&mut self) -> LPDSP32_CNT_W

Bits 0:31 - LPDSP32 activity counter value

impl W<u32, Reg<u32, _SYSCTRL_FLASH_READ_CNT>>

pub fn flash_read_cnt(&mut self) -> FLASH_READ_CNT_W

Bits 0:31 - Flash read access counter value

impl W<u32, Reg<u32, _SYSCTRL_SPEED_MEASURE>>

pub fn speed_measure_start(&mut self) -> SPEED_MEASURE_START_W

Bit 4 - Start critical path speed measurement

impl W<u32, Reg<u32, _SYSCTRL_LPDSP32_DEBUG_CFG>>

pub fn lpdsp32_exit_powerdown_when_halted(
    &mut self
) -> LPDSP32_EXIT_POWERDOWN_WHEN_HALTED_W

Bit 1 - LPDSP32 exit powerdown mode configuration when halted

pub fn lpdsp32_debug_enable(&mut self) -> LPDSP32_DEBUG_ENABLE_W

Bit 0 - LPDSP32 debug port enable

impl W<u32, Reg<u32, _SYSCTRL_RF_POWER_CFG>>

pub fn rf_power(&mut self) -> RF_POWER_W

Bit 0 - RF power configuration

impl W<u32, Reg<u32, _SYSCTRL_RF_ACCESS_CFG>>

pub fn rf_irq_access(&mut self) -> RF_IRQ_ACCESS_W

Bit 1 - RF IRQ access configuration

pub fn rf_access(&mut self) -> RF_ACCESS_W

Bit 0 - RF access configuration

impl W<u32, Reg<u32, _SYSCTRL_DBG_LOCK>>

pub fn dbg_lock_wr(&mut self) -> DBG_LOCK_WR_W

Bits 0:31 - Debug port access lock/unlock

impl W<u32, Reg<u32, _SYSCTRL_DBG_LOCK_KEY>>

pub fn dbg_lock_key(&mut self) -> DBG_LOCK_KEY_W

Bits 0:31 - Debug port key

impl W<u32, Reg<u32, _CLK_SYS_CFG>>

pub fn jtck_prescale(&mut self) -> JTCK_PRESCALE_W

Bits 16:19 - Prescale value for the input clock from pad JTCK (1 to 16 in steps of 1)

pub fn extclk_prescale(&mut self) -> EXTCLK_PRESCALE_W

Bits 8:11 - Prescale value for the input clock from pad EXTCLK (1 to 16 in steps of 1)

pub fn sysclk_src_sel(&mut self) -> SYSCLK_SRC_SEL_W

Bits 0:2 - Controls the source of the system clock : JTCK, RFCLK, RCCLK, EXTCLK or STANDBYCLK

impl W<u32, Reg<u32, _CLK_DIV_CFG0>>

pub fn usrclk_prescale(&mut self) -> USRCLK_PRESCALE_W

Bits 16:27 - Prescale value for the USR clock (1 to 4096 in steps of 1)

pub fn bbclk_prescale(&mut self) -> BBCLK_PRESCALE_W

Bits 8:10 - Prescale value for the Baseband peripheral clock (1 to 8 in steps of 1)

pub fn slowclk_prescale(&mut self) -> SLOWCLK_PRESCALE_W

Bits 0:5 - Prescale value for the SLOWCLK clock (1 to 64 in steps of 1)

impl W<u32, Reg<u32, _CLK_DIV_CFG1>>

pub fn audioslowclk_prescale(&mut self) -> AUDIOSLOWCLK_PRESCALE_W

Bits 30:31 - Prescale value for the slow audio clock down from the fast audio clock (1 to 4 in steps of 1)

pub fn audioclk_prescale(&mut self) -> AUDIOCLK_PRESCALE_W

Bits 24:29 - Prescale value for the fast audio clock (1 to 64 in steps of 1)

pub fn uartclk_prescale(&mut self) -> UARTCLK_PRESCALE_W

Bits 16:20 - Prescale value for the UART peripheral clock (1 to 32 in steps of 1)

pub fn pwm1clk_prescale(&mut self) -> PWM1CLK_PRESCALE_W

Bits 8:13 - Prescale value for the PWM1 peripheral clock (1 to 64 in steps of 1)

pub fn pwm0clk_prescale(&mut self) -> PWM0CLK_PRESCALE_W

Bits 0:5 - Prescale value for the PWM0 peripheral clock (1 to 64 in steps of 1)

impl W<u32, Reg<u32, _CLK_DIV_CFG2>>

pub fn cpclk_disable(&mut self) -> CPCLK_DISABLE_W

Bit 15 - Charge pump clock disable

pub fn cpclk_prescale(&mut self) -> CPCLK_PRESCALE_W

Bits 8:13 - Prescale value for the charge pump clock from the SLOWCLK clock (1 to 64 in steps of 1)

pub fn dcclk_disable(&mut self) -> DCCLK_DISABLE_W

Bit 7 - DC-DC converter clock disable

pub fn dcclk_prescale(&mut self) -> DCCLK_PRESCALE_W

Bits 0:5 - Prescale value for the DC-DC converter clock (1 to 64 in steps of 1)

impl W<u32, Reg<u32, _CLK_DET_CFG>>

pub fn clk_det_sel(&mut self) -> CLK_DET_SEL_W

Bit 5 - Clock detector source selection

pub fn clk_det_int_sel(&mut self) -> CLK_DET_INT_SEL_W

Bits 3:4 - Clock detector interrupt configuration

pub fn clk_det_div(&mut self) -> CLK_DET_DIV_W

Bits 1:2 - Clock detector configuration - Not used when running on standby clock

pub fn clk_det_enable(&mut self) -> CLK_DET_ENABLE_W

Bit 0 - Clock detector enable/disable

impl W<u32, Reg<u32, _DIG_RESET_STATUS>>

pub fn lockup_reset_flag_clear(&mut self) -> LOCKUP_RESET_FLAG_CLEAR_W

Bit 7 - Reset the sticky LOCKUP flag

pub fn watchdog_reset_flag_clear(&mut self) -> WATCHDOG_RESET_FLAG_CLEAR_W

Bit 6 - Reset the sticky Watchdog time-out reset flag

pub fn cm3_sw_reset_flag_clear(&mut self) -> CM3_SW_RESET_FLAG_CLEAR_W

Bit 5 - Reset the sticky CM3 software reset flag

pub fn acs_reset_flag_clear(&mut self) -> ACS_RESET_FLAG_CLEAR_W

Bit 4 - Reset the sticky ACS reset flag

impl W<u32, Reg<u32, _WATCHDOG_CFG>>

pub fn timeout_value(&mut self) -> TIMEOUT_VALUE_W

Bits 0:3 - Watchdog timeout period. Values 0xC to 0xF result in the same timeout period as the value 0xB.

impl W<u32, Reg<u32, _WATCHDOG_CTRL>>

pub fn watchdog_refresh(&mut self) -> WATCHDOG_REFRESH_W

Bits 0:31 - Write a key to reset the watchdog

impl W<u32, Reg<u32, _TIMER_CFG>>

pub fn multi_count(&mut self) -> MULTI_COUNT_W

Bits 29:31 - Multi-count value

pub fn mode(&mut self) -> MODE_W

Bit 28 - Timer mode

pub fn clk_src(&mut self) -> CLK_SRC_W

Bit 27 - Clock source

pub fn prescale(&mut self) -> PRESCALE_W

Bits 24:26 - Prescale value of the timer

pub fn timeout_value(&mut self) -> TIMEOUT_VALUE_W

Bits 0:23 - Number of Timer clock cycles to time-out

impl W<u32, Reg<u32, _TIMER_CTRL>>

pub fn timer_start(&mut self) -> TIMER_START_W

Bit 1 - Start or restart the timer

pub fn timer_stop(&mut self) -> TIMER_STOP_W

Bit 0 - Stop the timer

impl W<u32, Reg<u32, _FLASH_IF_CTRL>>

pub fn prefetch_dbus(&mut self) -> PREFETCH_DBUS_W

Bit 18 - Pre-fetch on D-Bus control

pub fn prefetch_ibus(&mut self) -> PREFETCH_IBUS_W

Bit 17 - Pre-fetch on I-Bus control

pub fn not_load_auto(&mut self) -> NOT_LOAD_AUTO_W

Bit 16 - Do not automatically load the configuration registers and the patch information from NVR4 sector after the command WAKEUP is completed.

pub fn vread1_mode(&mut self) -> VREAD1_MODE_W

Bit 12 - Control VREAD1: Read data after erase with more stringent condition than normal read. Changing this bit will execute the CMD_SET_VREAD1 or CMD_UNSET_VREAD1 command.

pub fn vread0_mode(&mut self) -> VREAD0_MODE_W

Bit 11 - Control VREAD0: Read data after program with more stringent condition than normal read. Changing this bit will execute the CMD_SET_VREAD0 or CMD_UNSET_VREAD0 command.

pub fn recall(&mut self) -> RECALL_W

Bit 10 - Set the recall pins mode during CMD_READ. Changing this bit will execute the CMD_SET_RECALL or CMD_UNSET_RECALL command.

pub fn retry(&mut self) -> RETRY_W

Bits 8:9 - Configures the erase retry iteration. This impacts the eFlash endurance time. Also used by Flash programming.

pub fn lp_mode(&mut self) -> LP_MODE_W

Bit 0 - Set the low power mode. Changing this bit will execute the CMD_SET_LOW_POWER or CMD_UNSET_LOW_POWER command.

impl W<u32, Reg<u32, _FLASH_MAIN_WRITE_UNLOCK>>

pub fn unlock_key(&mut self) -> UNLOCK_KEY_W

Bits 0:31 - 32-bit key to allow for write accesses into the Flash MAIN Block

impl W<u32, Reg<u32, _FLASH_MAIN_CTRL>>

pub fn main_high_w_en(&mut self) -> MAIN_HIGH_W_EN_W

Bit 2 - Authorize the write access to the high part of the Flash MAIN block through the FLASH_IF registers.

pub fn main_middle_w_en(&mut self) -> MAIN_MIDDLE_W_EN_W

Bit 1 - Authorize the write access to the middle part of the Flash MAIN block through the FLASH_IF registers.

pub fn main_low_w_en(&mut self) -> MAIN_LOW_W_EN_W

Bit 0 - Authorize the write access to the lower part of the Flash MAIN block through the FLASH_IF registers.

impl W<u32, Reg<u32, _FLASH_DELAY_CTRL>>

pub fn read_margin(&mut self) -> READ_MARGIN_W

Bit 7 - Flash Read access time margin

pub fn sysclk_freq(&mut self) -> SYSCLK_FREQ_W

Bits 0:3 - Configure Flash, memory and RF power-up delays

impl W<u32, Reg<u32, _FLASH_CMD_CTRL>>

pub fn cmd_end(&mut self) -> CMD_END_W

Bits 5:6 - Terminates an active Flash command if possible (e.g. sequential programming sequence)

pub fn command(&mut self) -> COMMAND_W

Bits 0:4 - Flash access command only writable when equal to CMD_IDLE

impl W<u32, Reg<u32, _FLASH_ADDR>>

pub fn flash_addr(&mut self) -> FLASH_ADDR_W

Bits 2:20 - Flash Byte Address

impl W<u32, Reg<u32, _FLASH_DATA>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - 32-bit Flash Data

impl W<u32, Reg<u32, _FLASH_NVR_WRITE_UNLOCK>>

pub fn unlock_key(&mut self) -> UNLOCK_KEY_W

Bits 0:31 - 32-bit key to allow for write accesses NVR sectors of the Flash

impl W<u32, Reg<u32, _FLASH_NVR_CTRL>>

pub fn nvr3_w_en(&mut self) -> NVR3_W_EN_W

Bit 3 - Authorize Write access to the Flash NVR3 sector through the FLASH_IF registers.

pub fn nvr2_w_en(&mut self) -> NVR2_W_EN_W

Bit 2 - Authorize Write access to the Flash NVR2 sector through the FLASH_IF registers.

pub fn nvr1_w_en(&mut self) -> NVR1_W_EN_W

Bit 1 - Authorize Write access to the Flash NVR1 sector through the FLASH_IF registers.

impl W<u32, Reg<u32, _FLASH_PATCH_ADDR>>

pub fn patch_addr(&mut self) -> PATCH_ADDR_W

Bits 11:20

impl W<u32, Reg<u32, _FLASH_COPY_CFG>>

pub fn comp_addr_step(&mut self) -> COMP_ADDR_STEP_W

Bit 18 - Comparator address increment/decrement by 1 or 2

pub fn comp_addr_dir(&mut self) -> COMP_ADDR_DIR_W

Bit 17 - Comparator address-up or address-down

pub fn comp_mode(&mut self) -> COMP_MODE_W

Bit 16 - Comparator Mode

pub fn copy_dest(&mut self) -> COPY_DEST_W

Bit 9 - Destination copier is the CRC or memories

pub fn copy_mode(&mut self) -> COPY_MODE_W

Bit 8 - Select copier mode (32-bit or 40-bit)

pub fn mode(&mut self) -> MODE_W

Bit 0 - Copier or Comparator Mode Configuration

impl W<u32, Reg<u32, _FLASH_COPY_CTRL>>

pub fn stop(&mut self) -> STOP_W

Bit 2 - Stop the transfer

pub fn start(&mut self) -> START_W

Bit 1 - Start the transfer

impl W<u32, Reg<u32, _FLASH_COPY_SRC_ADDR_PTR>>

pub fn copy_src_addr_ptr(&mut self) -> COPY_SRC_ADDR_PTR_W

Bits 0:20 - Source address pointer

impl W<u32, Reg<u32, _FLASH_COPY_DST_ADDR_PTR>>

pub fn copy_dst_addr_ptr(&mut self) -> COPY_DST_ADDR_PTR_W

Bits 2:31 - Destination address pointer

impl W<u32, Reg<u32, _FLASH_COPY_WORD_CNT>>

pub fn copy_word_cnt(&mut self) -> COPY_WORD_CNT_W

Bits 0:16 - Number of words to copy / compare

impl W<u32, Reg<u32, _FLASH_ECC_CTRL>>

pub fn ecc_cor_cnt_int_threshold(&mut self) -> ECC_COR_CNT_INT_THRESHOLD_W

Bits 8:15 - Select the number of corrected errors before sending a CM3 interrupt

pub fn copier_ecc_ctrl(&mut self) -> COPIER_ECC_CTRL_W

Bit 3

pub fn cmd_ecc_ctrl(&mut self) -> CMD_ECC_CTRL_W

Bit 2

pub fn idbus_ecc_ctrl(&mut self) -> IDBUS_ECC_CTRL_W

Bit 0 - Select the operating mode of the Flash ECC

impl W<u32, Reg<u32, _FLASH_ECC_STATUS>>

pub fn ecc_cor_error_cnt_clear(&mut self) -> ECC_COR_ERROR_CNT_CLEAR_W

Bit 6 - Reset the Flash corrected errors counter

pub fn ecc_uncor_error_cnt_clear(&mut self) -> ECC_UNCOR_ERROR_CNT_CLEAR_W

Bit 5 - Reset the Flash uncorrected errors counter

pub fn ecc_error_addr_clear(&mut self) -> ECC_ERROR_ADDR_CLEAR_W

Bit 4 - Reset the Flash address of the last detected error

impl W<u32, Reg<u32, _DMA_CTRL0>>

pub fn dest_addr_step_size(&mut self) -> DEST_ADDR_STEP_SIZE_W

Bits 30:31 - Select the destination address step size

pub fn src_addr_step_size(&mut self) -> SRC_ADDR_STEP_SIZE_W

Bits 28:29 - Select the source address step size

pub fn dest_addr_step_mode(&mut self) -> DEST_ADDR_STEP_MODE_W

Bit 27 - Configure the destination address to either increment or decrement

pub fn src_addr_step_mode(&mut self) -> SRC_ADDR_STEP_MODE_W

Bit 26 - Configure the source address to either increment or decrement

pub fn byte_order(&mut self) -> BYTE_ORDER_W

Bit 25 - Select the byte ordering for the DMA channel

pub fn disable_int_enable(&mut self) -> DISABLE_INT_ENABLE_W

Bit 24 - Raise an interrupt when the DMA channel is disabled

pub fn error_int_enable(&mut self) -> ERROR_INT_ENABLE_W

Bit 23 - Raise an interrupt when a state machine error occurs during a DMA transfer

pub fn complete_int_enable(&mut self) -> COMPLETE_INT_ENABLE_W

Bit 22 - Raise an interrupt when the DMA transfer completes

pub fn counter_int_enable(&mut self) -> COUNTER_INT_ENABLE_W

Bit 21 - Raise an interrupt when the DMA transfer reaches the counter value

pub fn start_int_enable(&mut self) -> START_INT_ENABLE_W

Bit 20 - Raise an interrupt when the DMA transfer starts

pub fn dest_word_size(&mut self) -> DEST_WORD_SIZE_W

Bits 18:19 - Select the destination word size

pub fn src_word_size(&mut self) -> SRC_WORD_SIZE_W

Bits 16:17 - Select the source word size

pub fn dest_select(&mut self) -> DEST_SELECT_W

Bits 12:14 - Select the request line for the destination

pub fn src_select(&mut self) -> SRC_SELECT_W

Bits 9:11 - Select the request line for the source

pub fn channel_priority(&mut self) -> CHANNEL_PRIORITY_W

Bits 6:7 - Select the priority level for this channel

pub fn transfer_type(&mut self) -> TRANSFER_TYPE_W

Bits 4:5 - Select the type of transfer implemented by DMA channel

pub fn dest_addr_inc(&mut self) -> DEST_ADDR_INC_W

Bit 3 - Configure whether the destination address should increment

pub fn src_addr_inc(&mut self) -> SRC_ADDR_INC_W

Bit 2 - Configure whether the source address should increment

pub fn addr_mode(&mut self) -> ADDR_MODE_W

Bit 1 - Select the addressing mode for this channel

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enable DMA Channel

impl W<u32, Reg<u32, _DMA_SRC_BASE_ADDR>>

pub fn dma_src_base_addr(&mut self) -> DMA_SRC_BASE_ADDR_W

Bits 0:31 - Base address for the source of data transferred using DMA channel

impl W<u32, Reg<u32, _DMA_DEST_BASE_ADDR>>

pub fn dma_dest_base_addr(&mut self) -> DMA_DEST_BASE_ADDR_W

Bits 0:31 - Base address for the destination of data transferred using DMA channel

impl W<u32, Reg<u32, _DMA_CTRL1>>

pub fn counter_int_value(&mut self) -> COUNTER_INT_VALUE_W

Bits 16:31 - Trigger a counter interrupt when the DMA transfer word count reaches this value

pub fn transfer_length(&mut self) -> TRANSFER_LENGTH_W

Bits 0:15 - The length, in words, of each data transfer using DMA channel

impl W<u32, Reg<u32, _DMA_STATUS>>

pub fn error_int_clear(&mut self) -> ERROR_INT_CLEAR_W

Bit 12 - Clear the state machine error interrupt flag

pub fn complete_int_clear(&mut self) -> COMPLETE_INT_CLEAR_W

Bit 11 - Clear the complete interrupt flag

pub fn counter_int_clear(&mut self) -> COUNTER_INT_CLEAR_W

Bit 10 - Clear the counter interrupt flag

pub fn start_int_clear(&mut self) -> START_INT_CLEAR_W

Bit 9 - Clear the start interrupt flag

pub fn disable_int_clear(&mut self) -> DISABLE_INT_CLEAR_W

Bit 8 - Clear the channel disable flag

impl W<u32, Reg<u32, _DIO_CFG>>

pub fn drive(&mut self) -> DRIVE_W

Bits 12:13 - Drive strength configuration

pub fn lpf(&mut self) -> LPF_W

Bit 10 - Low Pass Filter enable

pub fn pull_ctrl(&mut self) -> PULL_CTRL_W

Bits 8:9 - Pull selection

pub fn io_mode(&mut self) -> IO_MODE_W

Bits 0:5 - IO mode selection

impl W<u32, Reg<u32, _DIO_DATA>>

pub fn gpio(&mut self) -> GPIO_W

Bits 0:15 - GPIO[15:0] write data (updates output data of DIOs only for pads with IO_MODE 0b000XX)

impl W<u32, Reg<u32, _DIO_DIR>>

pub fn gpio(&mut self) -> GPIO_W

Bits 0:15 - Set DIO[15:0] GPIO direction (only in IO_MODE is 000XX)

impl W<u32, Reg<u32, _DIO_INT_CFG>>

pub fn debounce_enable(&mut self) -> DEBOUNCE_ENABLE_W

Bit 11 - Interrupt button debounce filter enable/disable

pub fn event(&mut self) -> EVENT_W

Bits 8:10 - Interrupt event configuration

pub fn src(&mut self) -> SRC_W

Bits 0:4 - Interrupt input selection

impl W<u32, Reg<u32, _DIO_INT_DEBOUNCE>>

pub fn debounce_clk(&mut self) -> DEBOUNCE_CLK_W

Bit 8 - Interrupt button debounce filter clock

pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W

Bits 0:7 - Interrupt button debounce filter count

impl W<u32, Reg<u32, _DIO_PCM_SRC>>

pub fn seri(&mut self) -> SERI_W

Bits 16:20 - PCM_SERI input selection

pub fn frame(&mut self) -> FRAME_W

Bits 8:12 - PCM_FRAME input selection

pub fn clk(&mut self) -> CLK_W

Bits 0:4 - PCM_CLK input selection

impl W<u32, Reg<u32, _DIO_SPI_SRC>>

pub fn seri(&mut self) -> SERI_W

Bits 16:20 - SPI_SERI input selection

pub fn cs(&mut self) -> CS_W

Bits 8:12 - SPI_CS input selection

pub fn clk(&mut self) -> CLK_W

Bits 0:4 - SPI_CLK input selection

impl W<u32, Reg<u32, _DIO_UART_SRC>>

pub fn rx(&mut self) -> RX_W

Bits 0:4 - UART_RX input selection

impl W<u32, Reg<u32, _DIO_I2C_SRC>>

pub fn sda(&mut self) -> SDA_W

Bits 8:12 - SDA input selection

pub fn scl(&mut self) -> SCL_W

Bits 0:4 - SCL input selection

impl W<u32, Reg<u32, _DIO_AUDIOSINK_SRC>>

pub fn clk(&mut self) -> CLK_W

Bits 0:4 - Audio sink clock input selection

impl W<u32, Reg<u32, _DIO_NMI_SRC>>

pub fn nmi_polarity(&mut self) -> NMI_POLARITY_W

Bit 5 - NMI polarity

pub fn nmi(&mut self) -> NMI_W

Bits 0:4 - NMI input selection

impl W<u32, Reg<u32, _DIO_BB_RX_SRC>>

pub fn rf_sync_p(&mut self) -> RF_SYNC_P_W

Bits 16:20 - Baseband controller interface RF_SYNC_P input selection

pub fn clk(&mut self) -> CLK_W

Bits 8:12 - Baseband controller RX clock input selection

pub fn data(&mut self) -> DATA_W

Bits 0:4 - Baseband controller RX data input selection

impl W<u32, Reg<u32, _DIO_BB_SPI_SRC>>

pub fn miso(&mut self) -> MISO_W

Bits 0:4 - Baseband controller SPI_MISO input selection

impl W<u32, Reg<u32, _DIO_RF_SPI_SRC>>

pub fn mosi(&mut self) -> MOSI_W

Bits 16:20 - RF front-end SPI_MOSI input selection

pub fn csn(&mut self) -> CSN_W

Bits 8:12 - RF front-end SPI_CSN input selection

pub fn clk(&mut self) -> CLK_W

Bits 0:4 - RF front-end SPI_CLK input selection

impl W<u32, Reg<u32, _DIO_RF_GPIO03_SRC>>

pub fn gpio3(&mut self) -> GPIO3_W

Bits 24:28 - RF front-end GPIO3 input selection

pub fn gpio2(&mut self) -> GPIO2_W

Bits 16:20 - RF front-end GPIO2 input selection

pub fn gpio1(&mut self) -> GPIO1_W

Bits 8:12 - RF front-end GPIO1 input selection

pub fn gpio0(&mut self) -> GPIO0_W

Bits 0:4 - RF front-end GPIO0 input selection

impl W<u32, Reg<u32, _DIO_RF_GPIO47_SRC>>

pub fn gpio7(&mut self) -> GPIO7_W

Bits 24:28 - RF front-end GPIO7 input selection

pub fn gpio6(&mut self) -> GPIO6_W

Bits 16:20 - RF front-end GPIO6 input selection

pub fn gpio5(&mut self) -> GPIO5_W

Bits 8:12 - RF front-end GPIO5 input selection

pub fn gpio4(&mut self) -> GPIO4_W

Bits 0:4 - RE front-end GPIO4 input selection

impl W<u32, Reg<u32, _DIO_RF_GPIO89_SRC>>

pub fn gpio9(&mut self) -> GPIO9_W

Bits 8:12 - RF front-end GPIO9 input selection

pub fn gpio8(&mut self) -> GPIO8_W

Bits 0:4 - RF front-end GPIO8 input selection

impl W<u32, Reg<u32, _DIO_DMIC_SRC>>

pub fn clk(&mut self) -> CLK_W

Bits 8:12 - DMIC clock input selection

pub fn data(&mut self) -> DATA_W

Bits 0:4 - DMIC data input selection

impl W<u32, Reg<u32, _DIO_LPDSP32_JTAG_SRC>>

pub fn tdi(&mut self) -> TDI_W

Bits 16:20 - LPDSP32_TDI input selection

pub fn tms(&mut self) -> TMS_W

Bits 8:12 - LPDSP32_TMS input selection

pub fn tck(&mut self) -> TCK_W

Bits 0:4 - LPDSP32_TCK input selection

impl W<u32, Reg<u32, _DIO_JTAG_SW_PAD_CFG>>

pub fn jtck_lpf(&mut self) -> JTCK_LPF_W

Bit 9 - JTCK Low-Pass-Filter enable / disable

pub fn jtms_lpf(&mut self) -> JTMS_LPF_W

Bit 8 - JTMS Low-Pass-Filter enable / disable

pub fn cm3_jtag_data_en(&mut self) -> CM3_JTAG_DATA_EN_W

Bit 7 - CM3 JTAG on DIO[14:15]

pub fn cm3_jtag_trst_en(&mut self) -> CM3_JTAG_TRST_EN_W

Bit 6 - CM3 JTAG TRST on DIO13

pub fn jtck_pull(&mut self) -> JTCK_PULL_W

Bits 4:5 - JTCK pull-up enable / disable

pub fn jtms_drive(&mut self) -> JTMS_DRIVE_W

Bits 2:3 - JTMS drive strength

pub fn jtms_pull(&mut self) -> JTMS_PULL_W

Bits 0:1 - JTMS pull-up enable / disable

impl W<u32, Reg<u32, _DIO_EXTCLK_CFG>>

pub fn lpf(&mut self) -> LPF_W

Bit 2 - Low Pass Filter enable

pub fn pull_ctrl(&mut self) -> PULL_CTRL_W

Bits 0:1 - Pull Selection

impl W<u32, Reg<u32, _DIO_PAD_CFG>>

pub fn drive(&mut self) -> DRIVE_W

Bit 0 - Drive strength configuration (scales the individual drive strengths)

impl W<u32, Reg<u32, _SPI0_CTRL0>>

pub fn spi0_overrun_int_enable(&mut self) -> SPI0_OVERRUN_INT_ENABLE_W

Bit 10 - Enable/disable SPI overrun interrupts

pub fn spi0_underrun_int_enable(&mut self) -> SPI0_UNDERRUN_INT_ENABLE_W

Bit 9 - Enable/disable SPI underrun interrupts

pub fn spi0_controller(&mut self) -> SPI0_CONTROLLER_W

Bit 8 - Select whether data transfer will be controlled by the CM3 or the DMA for SPI

pub fn spi0_slave(&mut self) -> SPI0_SLAVE_W

Bit 7 - Use the SPI interface as master or slave

pub fn spi0_clk_polarity(&mut self) -> SPI0_CLK_POLARITY_W

Bit 6 - Select the polarity of the SPI clock

pub fn spi0_mode_select(&mut self) -> SPI0_MODE_SELECT_W

Bit 5 - Select between manual and auto transaction handling modes for SPI master transactions

pub fn spi0_enable(&mut self) -> SPI0_ENABLE_W

Bit 4 - Enable/disable the SPI interface

pub fn spi0_prescale(&mut self) -> SPI0_PRESCALE_W

Bits 0:3 - Prescale the SPI interface clock for master transfers

impl W<u32, Reg<u32, _SPI0_CTRL1>>

pub fn spi0_start_busy(&mut self) -> SPI0_START_BUSY_W

Bit 8 - Start an SPI data transfer and indicate if a transfer is in progress

pub fn spi0_rw_cmd(&mut self) -> SPI0_RW_CMD_W

Bits 6:7 - Issue a read command or write command to the SPI interface

pub fn spi0_cs(&mut self) -> SPI0_CS_W

Bit 5 - Set the chip-select line for SPI (master mode), read the chip-select line for SPI (slave mode)

pub fn spi0_word_size(&mut self) -> SPI0_WORD_SIZE_W

Bits 0:4 - Select the word size used by the SPI interface (word size = SPI0_WORD_SIZE + 1)

impl W<u32, Reg<u32, _SPI0_TX_DATA>>

pub fn spi0_tx_data(&mut self) -> SPI0_TX_DATA_W

Bits 0:31 - Single word buffer for data to be transmitted over the SPI interface

impl W<u32, Reg<u32, _SPI0_STATUS>>

pub fn spi0_transmit_status(&mut self) -> SPI0_TRANSMIT_STATUS_W

Bit 3 - Indicate that the transmission of the data is completed

pub fn spi0_receive_status(&mut self) -> SPI0_RECEIVE_STATUS_W

Bit 2 - Indicate that new data has been received

pub fn spi0_overrun_status(&mut self) -> SPI0_OVERRUN_STATUS_W

Bit 1 - Indicate that an overrun has occurred when receiving data on the SPI interface

pub fn spi0_underrun_status(&mut self) -> SPI0_UNDERRUN_STATUS_W

Bit 0 - Indicate that an underrun has occurred when transmitting data on the SPI interface

impl W<u32, Reg<u32, _SPI1_CTRL0>>

pub fn spi1_overrun_int_enable(&mut self) -> SPI1_OVERRUN_INT_ENABLE_W

Bit 10 - Enable/disable SPI overrun interrupts

pub fn spi1_underrun_int_enable(&mut self) -> SPI1_UNDERRUN_INT_ENABLE_W

Bit 9 - Enable/disable SPI underrun interrupts

pub fn spi1_controller(&mut self) -> SPI1_CONTROLLER_W

Bit 8 - Select whether data transfer will be controlled by the CM3 or the DMA for SPI

pub fn spi1_slave(&mut self) -> SPI1_SLAVE_W

Bit 7 - Use the SPI interface as master or slave

pub fn spi1_clk_polarity(&mut self) -> SPI1_CLK_POLARITY_W

Bit 6 - Select the polarity of the SPI clock

pub fn spi1_mode_select(&mut self) -> SPI1_MODE_SELECT_W

Bit 5 - Select between manual and auto transaction handling modes for SPI master transactions

pub fn spi1_enable(&mut self) -> SPI1_ENABLE_W

Bit 4 - Enable/disable the SPI interface

pub fn spi1_prescale(&mut self) -> SPI1_PRESCALE_W

Bits 0:3 - Prescale the SPI interface clock for master transfers

impl W<u32, Reg<u32, _SPI1_CTRL1>>

pub fn spi1_start_busy(&mut self) -> SPI1_START_BUSY_W

Bit 8 - Start an SPI data transfer and indicate if a transfer is in progress

pub fn spi1_rw_cmd(&mut self) -> SPI1_RW_CMD_W

Bits 6:7 - Issue a read command or write command to the SPI interface

pub fn spi1_cs(&mut self) -> SPI1_CS_W

Bit 5 - Set the chip-select line for SPI (master mode), read the chip-select line for SPI (slave mode)

pub fn spi1_word_size(&mut self) -> SPI1_WORD_SIZE_W

Bits 0:4 - Select the word size used by the SPI interface (word size = SPI1_WORD_SIZE + 1)

impl W<u32, Reg<u32, _SPI1_TX_DATA>>

pub fn spi1_tx_data(&mut self) -> SPI1_TX_DATA_W

Bits 0:31 - Single word buffer for data to be transmitted over the SPI interface

impl W<u32, Reg<u32, _SPI1_STATUS>>

pub fn spi1_transmit_status(&mut self) -> SPI1_TRANSMIT_STATUS_W

Bit 3 - Indicate that the transmission of the data is completed

pub fn spi1_receive_status(&mut self) -> SPI1_RECEIVE_STATUS_W

Bit 2 - Indicate that new data has been received

pub fn spi1_overrun_status(&mut self) -> SPI1_OVERRUN_STATUS_W

Bit 1 - Indicate that an overrun has occurred when receiving data on the SPI interface

pub fn spi1_underrun_status(&mut self) -> SPI1_UNDERRUN_STATUS_W

Bit 0 - Indicate that an underrun has occurred when transmitting data on the SPI interface

impl W<u32, Reg<u32, _PCM_CTRL>>

pub fn pcm_clk_pol(&mut self) -> PCM_CLK_POL_W

Bit 14 - PCM clock polarity

pub fn bit_order(&mut self) -> BIT_ORDER_W

Bit 12 - Select whether the data will be transmitted starting with the MSB or LSB

pub fn tx_align(&mut self) -> TX_ALIGN_W

Bit 11 - Select what bits to use for transmit data

pub fn word_size(&mut self) -> WORD_SIZE_W

Bits 9:10 - Select the number of bits per PCM word

pub fn frame_align(&mut self) -> FRAME_ALIGN_W

Bit 8 - Align the PCM frame signal to the first/last bit

pub fn frame_width(&mut self) -> FRAME_WIDTH_W

Bit 7 - Use a long/short PCM frame signal

pub fn frame_length(&mut self) -> FRAME_LENGTH_W

Bits 4:6 - Select the number of words per PCM frame

pub fn frame_subframes(&mut self) -> FRAME_SUBFRAMES_W

Bit 3 - Enable the frame duration for each word

pub fn controller(&mut self) -> CONTROLLER_W

Bit 2 - Select whether data transfer will be controlled by the CM3 or the DMA for PCM

pub fn enable(&mut self) -> ENABLE_W

Bit 1 - Enable/disable the PCM interface

pub fn slave(&mut self) -> SLAVE_W

Bit 0 - Use the PCM interface as a master/slave

impl W<u32, Reg<u32, _PCM_TX_DATA>>

pub fn pcm_tx_data(&mut self) -> PCM_TX_DATA_W

Bits 0:31 - Data to transmit over the PCM interface

impl W<u32, Reg<u32, _PCM_STATUS>>

pub fn transmit_status(&mut self) -> TRANSMIT_STATUS_W

Bit 3 - Indicate that PCM data has been sent

pub fn receive_status(&mut self) -> RECEIVE_STATUS_W

Bit 2 - Indicate that PCM data has been received

pub fn overrun_status(&mut self) -> OVERRUN_STATUS_W

Bit 1 - Indicate that an overrun has occurred when receiving data on the PCM interface

pub fn underrun_status(&mut self) -> UNDERRUN_STATUS_W

Bit 0 - Indicate that an underrun has occurred when transmitting data on the PCM interface

impl W<u32, Reg<u32, _I2C_CTRL0>>

pub fn speed(&mut self) -> SPEED_W

Bits 16:23 - Prescaler used to divide SYSCLK to the correct SCL frequency when operating in I2C interface master mode. SCL is prescaled by (SPEED + 1) * 3. In slave mode controls the number of SYSCLK wait cycles in case of clock streching between the moment the data is put on the SDA line and the SCL line is released.

pub fn slave_address(&mut self) -> SLAVE_ADDRESS_W

Bits 8:14 - Set the I2C slave address for this device

pub fn controller(&mut self) -> CONTROLLER_W

Bit 4 - Select whether data transfer will be controlled by the CM3 or the DMA for I2C

pub fn stop_int_enable(&mut self) -> STOP_INT_ENABLE_W

Bit 3 - Configure whether stop interrupts will be generated by the I2C interface

pub fn auto_ack_enable(&mut self) -> AUTO_ACK_ENABLE_W

Bit 2 - Select whether acknowledgement is automatically generated or not

pub fn i2c_sample_clk_enable(&mut self) -> I2C_SAMPLE_CLK_ENABLE_W

Bit 1 - Enable/disable the I2C sample clock (mandatory to enable the I2C)

pub fn slave_enable(&mut self) -> SLAVE_ENABLE_W

Bit 0 - Select whether the I2C interface will be enabled for slave mode or not

impl W<u32, Reg<u32, _I2C_CTRL1>>

pub fn reset(&mut self) -> RESET_W

Bit 5 - Reset the I2C interface

pub fn last_data(&mut self) -> LAST_DATA_W

Bit 4 - Indicate that the current data is the last byte of a data transfer

pub fn stop(&mut self) -> STOP_W

Bit 3 - Issue a stop condition on the I2C interface bus

pub fn nack(&mut self) -> NACK_W

Bit 1 - Issue a not acknowledge on the I2C interface bus

pub fn ack(&mut self) -> ACK_W

Bit 0 - Issue an acknowledge on the I2C interface bus

impl W<u32, Reg<u32, _I2C_DATA>>

pub fn i2c_data(&mut self) -> I2C_DATA_W

Bits 0:7 - Single byte buffer for data transmitted and received over the I2C interface

impl W<u32, Reg<u32, _I2C_DATA_M>>

pub fn i2c_data_m(&mut self) -> I2C_DATA_M_W

Bits 0:7 - Mirror of the single byte buffer for data transmitted and received over the I2C interface

impl W<u32, Reg<u32, _I2C_ADDR_START>>

pub fn address(&mut self) -> ADDRESS_W

Bits 1:7 - I2C address to use for the transaction

pub fn read_write(&mut self) -> READ_WRITE_W

Bit 0 - Select whether a read or a write transaction is started

impl W<u32, Reg<u32, _UART_CFG>>

pub fn prescale(&mut self) -> PRESCALE_W

Bits 8:23 - Prescaling multiplier in baud rate calculation

pub fn prescale_enable(&mut self) -> PRESCALE_ENABLE_W

Bit 4 - Enable/disable a fixed prescaler by 12

pub fn dma_enable(&mut self) -> DMA_ENABLE_W

Bit 1 - DMA mode enable

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enable/disable the UART interface

impl W<u32, Reg<u32, _UART_TX_DATA>>

pub fn uart_tx_data(&mut self) -> UART_TX_DATA_W

Bits 0:7 - UART Transmit data

impl W<u32, Reg<u32, _UART_STATUS>>

pub fn uart_rx_overrun_status(&mut self) -> UART_RX_OVERRUN_STATUS_W

Bit 0 - Indicate that an overrun has occurred when receiving data on the UART interface

impl W<u32, Reg<u32, _PWM_CFG>>

pub fn pwm_high(&mut self) -> PWM_HIGH_W

Bits 8:15 - PWM high duty cycle

pub fn pwm_period(&mut self) -> PWM_PERIOD_W

Bits 0:7 - PWM period

impl W<u32, Reg<u32, _PWM_CTRL>>

pub fn pwm_offset_enable(&mut self) -> PWM_OFFSET_ENABLE_W

Bit 16 - Enable/disable the PWM offset function

pub fn pwm_offset(&mut self) -> PWM_OFFSET_W

Bits 8:15 - PWM0 to PWM1 offset

pub fn pwm1_enable(&mut self) -> PWM1_ENABLE_W

Bit 4 - Enable/disable the PWM1 block

pub fn pwm0_enable(&mut self) -> PWM0_ENABLE_W

Bit 0 - Enable/disable the PWM0 block

impl W<u32, Reg<u32, _AUDIO_CFG>>

pub fn od_clk_src(&mut self) -> OD_CLK_SRC_W

Bit 25 - Output driver clock selection

pub fn dmic_clk_src(&mut self) -> DMIC_CLK_SRC_W

Bit 24 - DMIC clock selection (the same clock must be output to the DMIC_CLK DIO pad)

pub fn dec_rate(&mut self) -> DEC_RATE_W

Bits 16:20 - DMIC input data decimation rate (also determines the OD interpolation rate in combination with DMIC_CLK_SRC and OD_CLK_SRC configuration bits)

pub fn od_underrun_protect(&mut self) -> OD_UNDERRUN_PROTECT_W

Bit 12 - Enable OD_DATA underrun protection (automatically resets OD_DATA if it hasn't been updated during 16 sample periods)

pub fn od_dma_req_en(&mut self) -> OD_DMA_REQ_EN_W

Bit 11 - Enable the DMA request when a new output driver sample is required

pub fn od_int_gen_en(&mut self) -> OD_INT_GEN_EN_W

Bit 10 - Enable the interrupt generation when a new output driver sample is required

pub fn od_data_align(&mut self) -> OD_DATA_ALIGN_W

Bit 9 - Data alignment in AUDIO_OD_DATA

pub fn od_enable(&mut self) -> OD_ENABLE_W

Bit 8 - Enable output driver output

pub fn dmic1_dma_req_en(&mut self) -> DMIC1_DMA_REQ_EN_W

Bit 7 - Enable the DMA request when a new DMIC1 sample is ready

pub fn dmic1_int_gen_en(&mut self) -> DMIC1_INT_GEN_EN_W

Bit 6 - Enable the interrupt generation when a new DMIC1 sample is ready

pub fn dmic1_data_align(&mut self) -> DMIC1_DATA_ALIGN_W

Bit 5 - Data alignment in AUDIO_DMIC_DATA_1

pub fn dmic1_enable(&mut self) -> DMIC1_ENABLE_W

Bit 4 - Enable DMIC1 input

pub fn dmic0_dma_req_en(&mut self) -> DMIC0_DMA_REQ_EN_W

Bit 3 - Enable the DMA request when a new DMIC0 sample is ready

pub fn dmic0_int_gen_en(&mut self) -> DMIC0_INT_GEN_EN_W

Bit 2 - Enable the interrupt generation when a new DMIC0 sample is ready

pub fn dmic0_data_align(&mut self) -> DMIC0_DATA_ALIGN_W

Bit 1 - Data alignment in AUDIO_DMIC_DATA_0

pub fn dmic0_enable(&mut self) -> DMIC0_ENABLE_W

Bit 0 - Enable DMIC0 input

impl W<u32, Reg<u32, _AUDIO_STATUS>>

pub fn od_underrun_flag_clear(&mut self) -> OD_UNDERRUN_FLAG_CLEAR_W

Bit 10 - Reset the output driver underrun detection sticky bit

pub fn dmic1_overrun_flag_clear(&mut self) -> DMIC1_OVERRUN_FLAG_CLEAR_W

Bit 6 - Reset the DMIC1 overrun detection sticky bit

pub fn dmic0_overrun_flag_clear(&mut self) -> DMIC0_OVERRUN_FLAG_CLEAR_W

Bit 2 - Reset the DMIC0 overrun detection sticky bit

impl W<u32, Reg<u32, _AUDIO_DMIC_CFG>>

pub fn dmic1_frac_delay(&mut self) -> DMIC1_FRAC_DELAY_W

Bits 24:28 - DMIC1 fractional delay (each step represents a DMIC clock cycle)

pub fn dmic1_delay(&mut self) -> DMIC1_DELAY_W

Bits 16:19 - DMIC1 delay (0 to 1.875 samples in steps of 0.125 samples)

pub fn dmic1_dcrm(&mut self) -> DMIC1_DCRM_W

Bits 12:14 - DMIC1 DC removal filter enable and cut-off frequency

pub fn dmic0_dcrm(&mut self) -> DMIC0_DCRM_W

Bits 8:10 - DMIC0 DC removal filter enable and cut-off frequency

pub fn dmic1_clk_edge(&mut self) -> DMIC1_CLK_EDGE_W

Bit 1 - DMIC1 input clock edge

pub fn dmic0_clk_edge(&mut self) -> DMIC0_CLK_EDGE_W

Bit 0 - DMIC0 input clock edge

impl W<u32, Reg<u32, _AUDIO_DMIC0_GAIN>>

pub fn gain(&mut self) -> GAIN_W

Bits 0:11 - DMIC calibration gain (unsigned value from 0 to +2)

impl W<u32, Reg<u32, _AUDIO_DMIC1_GAIN>>

pub fn gain(&mut self) -> GAIN_W

Bits 0:11 - DMIC calibration gain (unsigned value from 0 to +2)

impl W<u32, Reg<u32, _AUDIO_OD_CFG>>

pub fn dcrm(&mut self) -> DCRM_W

Bits 16:19 - Output driver DC removal filter enable and cut-off frequency

pub fn dither(&mut self) -> DITHER_W

Bit 10 - Sigma-delta modulator dithering enable

pub fn clk_edge(&mut self) -> CLK_EDGE_W

Bit 0 - Output driver output clock edge

impl W<u32, Reg<u32, _AUDIO_OD_GAIN>>

pub fn gain(&mut self) -> GAIN_W

Bits 0:11 - Output driver calibration gain (unsigned value from 0 to +2)

impl W<u32, Reg<u32, _AUDIO_OD_DATA>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - OD output data (LSB or MSB aligned according to OD_CFG); data is truncated to 16 bits when written in LSB aligned mode or rounded symmetrically with saturation when written in MSB aligned mode

impl W<u32, Reg<u32, _AUDIO_SDM_CFG>>

pub fn sdm_cfg(&mut self) -> SDM_CFG_W

Bits 0:31 - Sigma-Delta modulator internal configuration for test purposes

impl W<u32, Reg<u32, _CRC_CTRL>>

pub fn final_crc_xor(&mut self) -> FINAL_CRC_XOR_W

Bit 4 - Selects the final CRC XOR mode

pub fn final_crc_reverse(&mut self) -> FINAL_CRC_REVERSE_W

Bit 3 - Selects the final CRC reversal mode

pub fn bit_order(&mut self) -> BIT_ORDER_W

Bit 2 - Selects the bit order for bytes added to the CRC

pub fn crc_type(&mut self) -> CRC_TYPE_W

Bit 1 - Selects the CRC type

pub fn byte_order(&mut self) -> BYTE_ORDER_W

Bit 0 - Selects the endianness for bytes added to the CRC

impl W<u32, Reg<u32, _CRC_VALUE>>

pub fn current_crc(&mut self) -> CURRENT_CRC_W

Bits 0:31 - CRC generator value: Write 0xFFFFFFF (32) or 0xFFFF (CCITT) to initialize the CRC, read provides the current CRC value.

impl W<u32, Reg<u32, _CRC_ADD_1>>

pub fn crc_add_1_bit(&mut self) -> CRC_ADD_1_BIT_W

Bit 0 - Add 1 bit to the CRC calculation

impl W<u32, Reg<u32, _CRC_ADD_8>>

pub fn crc_add_8(&mut self) -> CRC_ADD_8_W

Bits 0:7 - Add 1 byte (8 bits) to the CRC calculation

impl W<u32, Reg<u32, _CRC_ADD_16>>

pub fn crc_add_16(&mut self) -> CRC_ADD_16_W

Bits 0:15 - Add 1 half-word (16 bits) to the CRC calculation

impl W<u32, Reg<u32, _CRC_ADD_24>>

pub fn crc_add_24_bits(&mut self) -> CRC_ADD_24_BITS_W

Bits 0:23 - Add 3 bytes (24 bits) to the CRC calculation

impl W<u32, Reg<u32, _CRC_ADD_32>>

pub fn crc_add_32(&mut self) -> CRC_ADD_32_W

Bits 0:31 - Add 1 word (32 bits) to the CRC calculation

impl W<u32, Reg<u32, _AUDIOSINK_CTRL>>

pub fn phase_cnt_start_no_wait(&mut self) -> PHASE_CNT_START_NO_WAIT_W

Bit 8 - Start the audio sink clock phase counter mechanism without waiting on a sync pulse

pub fn period_cnt_stop(&mut self) -> PERIOD_CNT_STOP_W

Bit 6 - Stop the audio sink clock period counter mechanism

pub fn period_cnt_start(&mut self) -> PERIOD_CNT_START_W

Bit 5 - Start the audio sink clock period counter mechanism

pub fn phase_cnt_stop(&mut self) -> PHASE_CNT_STOP_W

Bit 2 - Stop the audio sink clock phase counter mechanism

pub fn phase_cnt_start(&mut self) -> PHASE_CNT_START_W

Bit 1 - Start the audio sink clock PHASE counter mechanism and wait for sync pulse

pub fn cnt_reset(&mut self) -> CNT_RESET_W

Bit 0 - Reset audio sink clock counter

impl W<u32, Reg<u32, _AUDIOSINK_CFG>>

pub fn periods_cfg(&mut self) -> PERIODS_CFG_W

Bits 0:3 - Defines how over how many audio sink clock periods the period counter measures

impl W<u32, Reg<u32, _AUDIOSINK_PHASE_CNT>>

pub fn phase_cnt(&mut self) -> PHASE_CNT_W

Bits 0:15 - Sink clock phase counter value

impl W<u32, Reg<u32, _AUDIOSINK_PERIOD_CNT>>

pub fn period_cnt(&mut self) -> PERIOD_CNT_W

Bits 0:15 - Sink clock period counter value

impl W<u32, Reg<u32, _ASRC_CTRL>>

pub fn asrc_update_err_clr(&mut self) -> ASRC_UPDATE_ERR_CLR_W

Bit 9 - Clear the ASRC update/configuration error interrupt status

pub fn asrc_in_err_clr(&mut self) -> ASRC_IN_ERR_CLR_W

Bit 8 - Clear the ASRC input interface error interrupt

pub fn asrc_reset(&mut self) -> ASRC_RESET_W

Bit 3 - Write a 1 to reset ASRC

pub fn asrc_disable(&mut self) -> ASRC_DISABLE_W

Bit 1 - Disable the re-sampler block

pub fn asrc_enable(&mut self) -> ASRC_ENABLE_W

Bit 0 - Enable the re-sampler block

impl W<u32, Reg<u32, _ASRC_INT_ENABLE>>

pub fn asrc_update_err(&mut self) -> ASRC_UPDATE_ERR_W

Bit 3 - The ASRC state/configuration update error interrupt mask

pub fn asrc_in_err(&mut self) -> ASRC_IN_ERR_W

Bit 2 - The ASRC input interface error interrupt mask

pub fn asrc_out_req(&mut self) -> ASRC_OUT_REQ_W

Bit 1 - The ASRC_OUT register interrupt status

pub fn asrc_in_req(&mut self) -> ASRC_IN_REQ_W

Bit 0 - The ASRC_IN register interrupt status

impl W<u32, Reg<u32, _ASRC_OUT>>

pub fn asrc_out(&mut self) -> ASRC_OUT_W

Bits 0:15 - Audio sample output

impl W<u32, Reg<u32, _ASRC_IN>>

pub fn asrc_in(&mut self) -> ASRC_IN_W

Bits 0:15 - Audio sample input

impl W<u32, Reg<u32, _ASRC_CFG>>

pub fn wdf_type(&mut self) -> WDF_TYPE_W

Bit 2 - WDF Type Selection

pub fn asrc_mode(&mut self) -> ASRC_MODE_W

Bits 0:1 - ASRC mode

impl W<u32, Reg<u32, _ASRC_OUTPUT_CNT>>

pub fn asrc_output_cnt(&mut self) -> ASRC_OUTPUT_CNT_W

Bits 0:11 - ASRC output sample counter

impl W<u32, Reg<u32, _ASRC_PHASE_INC>>

pub fn asrc_step(&mut self) -> ASRC_STEP_W

Bits 0:31 - ASRC_PHASE_INC

impl W<u32, Reg<u32, _ASRC_PHASE_CNT>>

pub fn asrc_phase_cnt(&mut self) -> ASRC_PHASE_CNT_W

Bits 0:31 - ASRC phase counter

impl W<u32, Reg<u32, _ASRC_STATE_MEM>>

pub fn asrc_state_mem(&mut self) -> ASRC_STATE_MEM_W

Bits 0:31 - ASRC State Memory 0 to 29

impl W<u32, Reg<u32, _ADC_INPUT_SEL>>

pub fn pos_input_sel(&mut self) -> POS_INPUT_SEL_W

Bits 4:6 - Positive input selection

pub fn neg_input_sel(&mut self) -> NEG_INPUT_SEL_W

Bits 0:2 - Negative input selection

impl W<u32, Reg<u32, _ADC_CFG>>

pub fn duty_divider(&mut self) -> DUTY_DIVIDER_W

Bit 5 - Duty cycling VDD divider

pub fn continuous_mode(&mut self) -> CONTINUOUS_MODE_W

Bit 4 - ADC continuously sampling the channel selected as interrupt source (ADC_INT_CH_NUM)

pub fn freq(&mut self) -> FREQ_W

Bits 0:3 - Defines the sampling frequency of the ADC channels

impl W<u32, Reg<u32, _ADC_OFFSET>>

pub fn data(&mut self) -> DATA_W

Bits 0:14 - 15-bit ADC signed offset

impl W<u32, Reg<u32, _ADC_BATMON_CFG>>

pub fn alarm_count_value(&mut self) -> ALARM_COUNT_VALUE_W

Bits 16:23 - An Alarm Status bit gets set when SUPPLY_COUNT_VALUE= ALARM_COUNT_VALUE

pub fn supply_threshold(&mut self) -> SUPPLY_THRESHOLD_W

Bits 8:15 - Low voltage detection threshold (7.8 mV steps)

pub fn supply_src(&mut self) -> SUPPLY_SRC_W

Bit 0 - Selects the power supply voltage source to be monitored

impl W<u32, Reg<u32, _ADC_BATMON_INT_ENABLE>>

pub fn batmon_alarm_int_enable(&mut self) -> BATMON_ALARM_INT_ENABLE_W

Bit 4 - The BATMON Alarm interrupt mask

pub fn adc_int_ch_num(&mut self) -> ADC_INT_CH_NUM_W

Bits 1:3 - Channel number triggering the ADC interrupt

pub fn adc_int_enable(&mut self) -> ADC_INT_ENABLE_W

Bit 0 - The ADC new sample ready interrupt mask

impl W<u32, Reg<u32, _ADC_BATMON_STATUS>>

pub fn batmon_alarm_clear(&mut self) -> BATMON_ALARM_CLEAR_W

Bit 12 - Battery monitoring alarm status bit

pub fn adc_overrun_clear(&mut self) -> ADC_OVERRUN_CLEAR_W

Bit 9 - ADC Overrun condition

pub fn adc_ready_clear(&mut self) -> ADC_READY_CLEAR_W

Bit 8 - ADC new sample Ready status bit

impl W<u32, Reg<u32, _ACS_BG_CTRL>>

pub fn slope_trim(&mut self) -> SLOPE_TRIM_W

Bits 8:12 - Temperature coefficient trimming

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:5 - Reference voltage trimming (2.5 mV steps)

impl W<u32, Reg<u32, _ACS_VCC_CTRL>>

pub fn ich_trim(&mut self) -> ICH_TRIM_W

Bits 16:19 - Inductor charge current trimming

pub fn ccm_enable(&mut self) -> CCM_ENABLE_W

Bit 11 - Enable CCM mode

pub fn pulse_ctrl(&mut self) -> PULSE_CTRL_W

Bit 10 - Pulse mode control

pub fn charge_ctrl(&mut self) -> CHARGE_CTRL_W

Bit 9 - Charge mode control

pub fn buck_enable(&mut self) -> BUCK_ENABLE_W

Bit 8 - Enable buck converter mode

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:4 - Output voltage trimming configuration in 10 mV steps

impl W<u32, Reg<u32, _ACS_VDDA_CP_CTRL>>

pub fn ptrim(&mut self) -> PTRIM_W

Bits 0:1 - Output power trimming

impl W<u32, Reg<u32, _ACS_VDDC_CTRL>>

pub fn standby_vtrim(&mut self) -> STANDBY_VTRIM_W

Bits 16:21 - VDDC standby voltage trimming (10 mV steps)

pub fn enable_low_bias(&mut self) -> ENABLE_LOW_BIAS_W

Bit 13 - Low power mode control

pub fn sleep_clamp(&mut self) -> SLEEP_CLAMP_W

Bit 12 - Sleep mode clamp control

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:5 - Output voltage trimming configuration in 10 mV steps

impl W<u32, Reg<u32, _ACS_VDDM_CTRL>>

pub fn standby_vtrim(&mut self) -> STANDBY_VTRIM_W

Bits 16:21 - VDDM standby voltage trimming (10 mV steps)

pub fn enable_low_bias(&mut self) -> ENABLE_LOW_BIAS_W

Bit 13 - Low power mode control

pub fn sleep_clamp(&mut self) -> SLEEP_CLAMP_W

Bit 12 - Sleep mode clamp control

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:5 - Output voltage trimming configuration in 10 mV steps

impl W<u32, Reg<u32, _ACS_VDDRF_CTRL>>

pub fn clamp(&mut self) -> CLAMP_W

Bit 12 - Disable mode clamp control

pub fn enable(&mut self) -> ENABLE_W

Bit 8 - Enable control

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:5 - Output voltage trimming configuration in 10 mV steps

impl W<u32, Reg<u32, _ACS_VDDPA_CTRL>>

pub fn vddpa_sw_ctrl(&mut self) -> VDDPA_SW_CTRL_W

Bit 12 - Power amplifier supply control

pub fn enable_isense(&mut self) -> ENABLE_ISENSE_W

Bit 9 - Enable current sensing circuit

pub fn enable(&mut self) -> ENABLE_W

Bit 8 - Enable control

pub fn vtrim(&mut self) -> VTRIM_W

Bits 0:5 - Output voltage trimming configuration in 10 mV steps

impl W<u32, Reg<u32, _ACS_VDDRET_CTRL>>

pub fn vddmret_vtrim(&mut self) -> VDDMRET_VTRIM_W

Bits 17:18 - VDDMRET retention regulator voltage trimming

pub fn vddmret_enable(&mut self) -> VDDMRET_ENABLE_W

Bit 16 - Enable/Disable the VDDMRET retention regulator

pub fn vddtret_vtrim(&mut self) -> VDDTRET_VTRIM_W

Bits 9:10 - VDDTRET retention regulator voltage trimming

pub fn vddtret_enable(&mut self) -> VDDTRET_ENABLE_W

Bit 8 - Enable/Disable the VDDTRET retention regulator

pub fn vddcret_vtrim(&mut self) -> VDDCRET_VTRIM_W

Bits 1:2 - VDDCRET retention regulator voltage trimming

pub fn vddcret_enable(&mut self) -> VDDCRET_ENABLE_W

Bit 0 - Enable/Disable the VDDCRET retention regulator

impl W<u32, Reg<u32, _ACS_RCOSC_CTRL>>

pub fn clock_mult(&mut self) -> CLOCK_MULT_W

Bit 18 - Enable 12 MHz mode of startup oscillator

pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W

Bit 16 - Enable/Disable the 32 kHz RC Oscillator

pub fn ftrim_flag(&mut self) -> FTRIM_FLAG_W

Bit 15 - Trimming flag

pub fn ftrim_start(&mut self) -> FTRIM_START_W

Bits 8:13 - Start RC oscillator frequency trimming

pub fn ftrim_32k_adj(&mut self) -> FTRIM_32K_ADJ_W

Bit 6 - Adjust 32 kHz oscillator frequency range

pub fn ftrim_32k(&mut self) -> FTRIM_32K_W

Bits 0:5 - 32 kHz RC oscillator frequency trimming

impl W<u32, Reg<u32, _ACS_XTAL32K_CTRL>>

pub fn xin_cap_bypass_en(&mut self) -> XIN_CAP_BYPASS_EN_W

Bit 18 - Switch to bypass the added XIN serial cap to reduce the leakage

pub fn en_ampl_ctrl(&mut self) -> EN_AMPL_CTRL_W

Bit 17 - XTAL enable amplitude control (regulation)

pub fn force_ready(&mut self) -> FORCE_READY_W

Bit 16 - XTAL bypass the ready detector

pub fn cload_trim(&mut self) -> CLOAD_TRIM_W

Bits 8:13 - XTAL load capacitance configuration

pub fn itrim(&mut self) -> ITRIM_W

Bits 4:7 - XTAL current trimming

pub fn iboost(&mut self) -> IBOOST_W

Bit 1 - XTAL current boosting (4x)

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enable the XTAL 32 kHz oscillator

impl W<u32, Reg<u32, _ACS_BB_TIMER_CTRL>>

pub fn bb_clk_prescale(&mut self) -> BB_CLK_PRESCALE_W

Bits 8:9 - Prescale value for the baseband timer clock

pub fn bb_timer_nreset(&mut self) -> BB_TIMER_NRESET_W

Bit 0 - nReset signal for the baseband timer

impl W<u32, Reg<u32, _ACS_CLK_DET_CTRL>>

pub fn reset_ignore(&mut self) -> RESET_IGNORE_W

Bit 1 - Clock detector reset condition ignore

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Clock detector enable

impl W<u32, Reg<u32, _ACS_RTC_CFG>>

pub fn start_value(&mut self) -> START_VALUE_W

Bits 0:31 - Start value for the RTC timer counter (counts from start_value down to 0)

impl W<u32, Reg<u32, _ACS_RTC_CTRL>>

pub fn force_clock(&mut self) -> FORCE_CLOCK_W

Bit 25 - Force a clock on RTC timer (Test Purpose)

pub fn reset(&mut self) -> RESET_W

Bit 24 - Reset the RTC timer

pub fn alarm_cfg(&mut self) -> ALARM_CFG_W

Bits 4:7 - Configure RTC timer alarm

pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W

Bits 1:3 - Select the RTC, standby and bb timer clock source

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enable counter and RTC interrupt every 1s

impl W<u32, Reg<u32, _ACS_PWR_MODES_CTRL>>

pub fn power_mode(&mut self) -> POWER_MODE_W

Bits 0:31 - 32-bit key to enter RUN, STANDBY or SLEEP mode

impl W<u32, Reg<u32, _ACS_WAKEUP_CTRL>>

pub fn pads_retention_en(&mut self) -> PADS_RETENTION_EN_W

Bit 24 - Enable / Disable the retention mode of the pads

pub fn boot_flash_app_reboot(&mut self) -> BOOT_FLASH_APP_REBOOT_W

Bit 20 - Boot mode flag

pub fn boot_select(&mut self) -> BOOT_SELECT_W

Bits 16:17 - Boot selection to indicate boot source

pub fn dcdc_overload_clear(&mut self) -> DCDC_OVERLOAD_CLEAR_W

Bit 7

pub fn wakeup_pad_wakeup_clear(&mut self) -> WAKEUP_PAD_WAKEUP_CLEAR_W

Bit 6

pub fn rtc_alarm_wakeup_clear(&mut self) -> RTC_ALARM_WAKEUP_CLEAR_W

Bit 5

pub fn bb_timer_wakeup_clear(&mut self) -> BB_TIMER_WAKEUP_CLEAR_W

Bit 4

pub fn dio3_wakeup_clear(&mut self) -> DIO3_WAKEUP_CLEAR_W

Bit 3

pub fn dio2_wakeup_clear(&mut self) -> DIO2_WAKEUP_CLEAR_W

Bit 2

pub fn dio1_wakeup_clear(&mut self) -> DIO1_WAKEUP_CLEAR_W

Bit 1

pub fn dio0_wakeup_clear(&mut self) -> DIO0_WAKEUP_CLEAR_W

Bit 0

impl W<u32, Reg<u32, _ACS_WAKEUP_CFG>>

pub fn delay(&mut self) -> DELAY_W

Bits 16:18 - Delay from VDDC ready to digital clock enable (power of 2)

pub fn dcdc_overload_en(&mut self) -> DCDC_OVERLOAD_EN_W

Bit 9 - Enable / Disable the Wake-up functionality on the DCDC overload flag

pub fn wakeup_pad_pol(&mut self) -> WAKEUP_PAD_POL_W

Bit 8 - Wake-up polarity on the WAKEUP pad

pub fn dio3_pol(&mut self) -> DIO3_POL_W

Bit 7 - Wake-up polarity on the DIO3 pad

pub fn dio2_pol(&mut self) -> DIO2_POL_W

Bit 6 - Wake-up polarity on the DIO2 pad

pub fn dio1_pol(&mut self) -> DIO1_POL_W

Bit 5 - Wake-up polarity on the DIO1 pad

pub fn dio0_pol(&mut self) -> DIO0_POL_W

Bit 4 - Wake-up polarity on the DIO0 pad

pub fn dio3_en(&mut self) -> DIO3_EN_W

Bit 3 - Enable / Disable the Wake-up functionality on the DIO3 pad

pub fn dio2_en(&mut self) -> DIO2_EN_W

Bit 2 - Enable / Disable the Wake-up functionality on the DIO2 pad

pub fn dio1_en(&mut self) -> DIO1_EN_W

Bit 1 - Enable / Disable the Wake-up functionality on the DIO1 pad

pub fn dio0_en(&mut self) -> DIO0_EN_W

Bit 0 - Enable / Disable the Wake-up functionality on the DIO0 pad

impl W<u32, Reg<u32, _ACS_WAKEUP_GP_DATA>>

pub fn gp_data(&mut self) -> GP_DATA_W

Bits 0:31 - 32-bit General-Purpose RW Data

impl W<u32, Reg<u32, _ACS_RESET_STATUS>>

pub fn timeout_reset_flag_clear(&mut self) -> TIMEOUT_RESET_FLAG_CLEAR_W

Bit 6 - Reset the sticky TIMEOUT_RESET flag.

pub fn clk_det_reset_flag_clear(&mut self) -> CLK_DET_RESET_FLAG_CLEAR_W

Bit 5 - Reset the sticky CLK_DET_RESET flag.

pub fn vdda_reset_flag_clear(&mut self) -> VDDA_RESET_FLAG_CLEAR_W

Bit 4 - Reset the sticky VDDA_RESET flag.

pub fn vddm_reset_flag_clear(&mut self) -> VDDM_RESET_FLAG_CLEAR_W

Bit 3 - Reset the sticky VDDM_RESET flag.

pub fn vddc_reset_flag_clear(&mut self) -> VDDC_RESET_FLAG_CLEAR_W

Bit 2 - Reset the sticky VDDC_RESET flag.

pub fn pad_reset_flag_clear(&mut self) -> PAD_RESET_FLAG_CLEAR_W

Bit 1 - Reset the sticky PAD_RESET flag.

pub fn por_reset_flag_clear(&mut self) -> POR_RESET_FLAG_CLEAR_W

Bit 0 - Reset the sticky POR_RESET flag.

impl W<u32, Reg<u32, _ACS_AOUT_CTRL>>

pub fn rtc_clock_dio0_stop_edge(&mut self) -> RTC_CLOCK_DIO0_STOP_EDGE_W

Bit 13 - Stop edge for RTC clock output on AOUT

pub fn rtc_clock_dio0_stop_src(&mut self) -> RTC_CLOCK_DIO0_STOP_SRC_W

Bits 11:12 - Stop source for RTC clock output on AOUT

pub fn rtc_clock_dio0_start(&mut self) -> RTC_CLOCK_DIO0_START_W

Bits 8:10 - Start event for RTC clock output on AOUT (RTC prescaler and counter need to be enabled)

pub fn test_aout(&mut self) -> TEST_AOUT_W

Bits 0:4 - AOUT test signal selection

impl W<u32, Reg<u32, _BBIF_CTRL>>

pub fn wakeup_req(&mut self) -> WAKEUP_REQ_W

Bit 16 - External wake up request used to sort-out sleep modes

pub fn clk_sel(&mut self) -> CLK_SEL_W

Bits 4:9 - Configure the internal baseband controller clock divider in order to provide a 1MHz reference clock

pub fn clk_enable(&mut self) -> CLK_ENABLE_W

Bit 0 - Enable the baseband controller clocks generation

impl W<u32, Reg<u32, _BBIF_COEX_CTRL>>

pub fn tx(&mut self) -> TX_W

Bit 4 - Indicates if the RF front-end performs a non-BLE Tx activity

pub fn rx(&mut self) -> RX_W

Bit 0 - Indicates if the RF front-end performs a non-BLE Rx activity

impl W<u32, Reg<u32, _BBIF_COEX_INT_CFG>>

pub fn ble_in_process_event(&mut self) -> BLE_IN_PROCESS_EVENT_W

Bits 8:9 - BLE_IN_PROCESS event interrupt configuration

pub fn ble_tx_event(&mut self) -> BLE_TX_EVENT_W

Bits 4:5 - BLE_TX event interrupt configuration

pub fn ble_rx_event(&mut self) -> BLE_RX_EVENT_W

Bits 0:1 - BLE_RX event interrupt configuration

impl W<u32, Reg<u32, _BBIF_SYNC_CFG>>

pub fn rf_rx(&mut self) -> RF_RX_W

Bit 17 - Specify if the RF front-end is currently receiving the audio link

pub fn rf_active(&mut self) -> RF_ACTIVE_W

Bit 16 - Specify if the RF front-end is currently processing the audio link

pub fn link_format(&mut self) -> LINK_FORMAT_W

Bits 11:15 - Configure the BLE link format for synchronization

pub fn link_label(&mut self) -> LINK_LABEL_W

Bits 4:8 - Configure the BLE link label for synchronization

pub fn source(&mut self) -> SOURCE_W

Bits 1:3 - Select the BLE/RF link synchronization source

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Enable the frame synchronization pulse filter

impl W<u32, Reg<u32, _BB_RWBBCNTL>>

pub fn master_soft_rst(&mut self) -> MASTER_SOFT_RST_W

Bit 31 - Reset the complete system except registers and timing generator

pub fn master_tgsoft_rst(&mut self) -> MASTER_TGSOFT_RST_W

Bit 30 - Reset the timing generator

pub fn reg_soft_rst(&mut self) -> REG_SOFT_RST_W

Bit 29 - Reset the complete register block

pub fn swint_req(&mut self) -> SWINT_REQ_W

Bit 28 - Forces the generation of ble_sw_irq

pub fn rftest_abort(&mut self) -> RFTEST_ABORT_W

Bit 26 - Abort the current RF testing defined as per CS-FORMAT

pub fn advert_abort(&mut self) -> ADVERT_ABORT_W

Bit 25 - Abort the current scan window

pub fn scan_abort(&mut self) -> SCAN_ABORT_W

Bit 24 - Abort the current advertising event

pub fn md_dsb(&mut self) -> MD_DSB_W

Bit 22 - Allow a single Tx/Rx exchange whatever the MD bits are

pub fn sn_dsb(&mut self) -> SN_DSB_W

Bit 21 - Disable sequence number management

pub fn nesn_dsb(&mut self) -> NESN_DSB_W

Bit 20 - Disable acknowledge scheme

pub fn crypt_dsb(&mut self) -> CRYPT_DSB_W

Bit 19 - Disable encryption / decryption

pub fn whit_dsb(&mut self) -> WHIT_DSB_W

Bit 18 - Disable whitening

pub fn crc_dsb(&mut self) -> CRC_DSB_W

Bit 17 - Disable CRC stripping

pub fn hop_remap_dsb(&mut self) -> HOP_REMAP_DSB_W

Bit 16 - Disable frequency hopping remapping algorithm

pub fn advertfilt_en(&mut self) -> ADVERTFILT_EN_W

Bit 9 - Advertising channels error filtering enable control

pub fn rwble_en(&mut self) -> RWBLE_EN_W

Bit 8 - Enable RW-BLE core exchange table pre-fetch mechanism

pub fn rxwinszdef(&mut self) -> RXWINSZDEF_W

Bits 4:7 - Default Rx Window size in us (used when device is master connected or performs its second receipt)

pub fn syncerr(&mut self) -> SYNCERR_W

Bits 0:2 - Indicates the maximum number of errors allowed to recognize the synchronization word

impl W<u32, Reg<u32, _BB_INTCNTL>>

pub fn cscntdevmsk(&mut self) -> CSCNTDEVMSK_W

Bit 15 - CSCNT interrupt mask during event allowing to enable CSCNT interrupt generation during events

pub fn audioint2msk(&mut self) -> AUDIOINT2MSK_W

Bit 12 - Audio channel 2 interrupt mask

pub fn audioint1msk(&mut self) -> AUDIOINT1MSK_W

Bit 11 - Audio channel 1 interrupt mask

pub fn audioint0msk(&mut self) -> AUDIOINT0MSK_W

Bit 10 - Audio channel 0 interrupt mask

pub fn swintmsk(&mut self) -> SWINTMSK_W

Bit 9 - SW triggered interrupt mask

pub fn eventapfaintmsk(&mut self) -> EVENTAPFAINTMSK_W

Bit 8 - End of event / anticipated pre-fetch abort interrupt mask

pub fn finetgtimintmsk(&mut self) -> FINETGTIMINTMSK_W

Bit 7 - Fine target timer mask

pub fn grosstgtimintmsk(&mut self) -> GROSSTGTIMINTMSK_W

Bit 6 - Gross target timer mask

pub fn errorintmsk(&mut self) -> ERRORINTMSK_W

Bit 5 - Error interrupt mask

pub fn cryptintmsk(&mut self) -> CRYPTINTMSK_W

Bit 4 - Encryption engine interrupt mask

pub fn eventintmsk(&mut self) -> EVENTINTMSK_W

Bit 3 - End of event interrupt mask

pub fn slpintmsk(&mut self) -> SLPINTMSK_W

Bit 2 - Sleep mode interrupt mask

pub fn rxintmsk(&mut self) -> RXINTMSK_W

Bit 1 - Rx interrupt mask

pub fn cscntintmsk(&mut self) -> CSCNTINTMSK_W

Bit 0 - 625us base time interrupt mask

impl W<u32, Reg<u32, _BB_INTACK>>

pub fn swintack(&mut self) -> SWINTACK_W

Bit 9 - SW triggered interrupt acknowledgement bit

pub fn eventapfaintack(&mut self) -> EVENTAPFAINTACK_W

Bit 8 - End of event / anticipated pre-fetch abort interrupt acknowledgement bit

pub fn finetgtimintack(&mut self) -> FINETGTIMINTACK_W

Bit 7 - Fine target timer interrupt acknowledgement bit

pub fn grosstgtimintack(&mut self) -> GROSSTGTIMINTACK_W

Bit 6 - Gross target timer interrupt acknowledgement bit

pub fn errorintack(&mut self) -> ERRORINTACK_W

Bit 5 - Error interrupt acknowledgement bit

pub fn cryptintack(&mut self) -> CRYPTINTACK_W

Bit 4 - Encryption engine interrupt acknowledgement bit

pub fn eventintack(&mut self) -> EVENTINTACK_W

Bit 3 - End of event interrupt acknowledgment bit

pub fn slpintack(&mut self) -> SLPINTACK_W

Bit 2 - End of deep sleep interrupt acknowledgment bit

pub fn rxintack(&mut self) -> RXINTACK_W

Bit 1 - Packet reception interrupt acknowledgment bit

pub fn cscntintack(&mut self) -> CSCNTINTACK_W

Bit 0 - 625us base time reference interrupt acknowledgment bit

impl W<u32, Reg<u32, _BB_BASETIMECNT>>

pub fn samp(&mut self) -> SAMP_W

Bit 31 - Sample the base time counter

impl W<u32, Reg<u32, _BB_BDADDRL>>

pub fn bdaddrl(&mut self) -> BDADDRL_W

Bits 0:31 - BLE device address (LSB part)

impl W<u32, Reg<u32, _BB_BDADDRU>>

pub fn priv_npub(&mut self) -> PRIV_NPUB_W

Bit 16 - BLE device address privacy indicator

pub fn bdaddru(&mut self) -> BDADDRU_W

Bits 0:15 - BLE device address (MSB part)

impl W<u32, Reg<u32, _BB_ET_CURRENTRXDESCPTR>>

pub fn etptr(&mut self) -> ETPTR_W

Bits 16:31 - Exchange table pointer that determines the starting point of the exchange table

pub fn currentrxdescptr(&mut self) -> CURRENTRXDESCPTR_W

Bits 0:14 - Rx descriptor pointer that determines the starting point of the receive buffer chained list

impl W<u32, Reg<u32, _BB_DEEPSLCNTL>>

pub fn extwkupdsb(&mut self) -> EXTWKUPDSB_W

Bit 31 - External wake-up disable

pub fn soft_wakeup_req(&mut self) -> SOFT_WAKEUP_REQ_W

Bit 4 - Wake up request from RW-BLE software applying when system is in deep sleep mode

pub fn deep_sleep_corr_en(&mut self) -> DEEP_SLEEP_CORR_EN_W

Bit 3 - 625us base time reference integer and fractional part correction applying when system has been woken-up from deep sleep mode

pub fn deep_sleep_on(&mut self) -> DEEP_SLEEP_ON_W

Bit 2 - RW-BLE core power mode control

pub fn radio_sleep_en(&mut self) -> RADIO_SLEEP_EN_W

Bit 1 - Controls the radio module

pub fn osc_sleep_en(&mut self) -> OSC_SLEEP_EN_W

Bit 0 - Controls the RF high frequency crystal oscillator

impl W<u32, Reg<u32, _BB_DEEPSLWKUP>>

pub fn deepsltime(&mut self) -> DEEPSLTIME_W

Bits 0:31 - Determines the time in low_power_clk clock cycles to spend in deep sleep mode before waking-up the device

impl W<u32, Reg<u32, _BB_ENBPRESET>>

pub fn twosc(&mut self) -> TWOSC_W

Bits 10:20 - Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator when the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP-DEEPSLTIME])

impl W<u32, Reg<u32, _BB_FINECNTCORR>>

pub fn finecntcorr(&mut self) -> FINECNTCORR_W

Bits 0:9 - Phase correction value for the 625us reference counter (i.e. fine counter) in us

impl W<u32, Reg<u32, _BB_BASETIMECNTCORR>>

pub fn basetimecntcorr(&mut self) -> BASETIMECNTCORR_W

Bits 0:26 - Base time counter correction value

impl W<u32, Reg<u32, _BB_DIAGCNTL>>

pub fn diag3_en(&mut self) -> DIAG3_EN_W

Bit 31 - Enable diagnostic port 3 output

pub fn diag3(&mut self) -> DIAG3_W

Bits 24:29

pub fn diag2_en(&mut self) -> DIAG2_EN_W

Bit 23 - Enable diagnostic port 2 output

pub fn diag2(&mut self) -> DIAG2_W

Bits 16:21

pub fn diag1_en(&mut self) -> DIAG1_EN_W

Bit 15 - Enable diagnostic port 1 output

pub fn diag1(&mut self) -> DIAG1_W

Bits 8:13

pub fn diag0_en(&mut self) -> DIAG0_EN_W

Bit 7 - Enable diagnostic port 0 output

pub fn diag0(&mut self) -> DIAG0_W

Bits 0:5

impl W<u32, Reg<u32, _BB_DEBUGADDMAX>>

pub fn reg_addmax(&mut self) -> REG_ADDMAX_W

Bits 16:31 - Upper limit for the register zone indicated by the reg_inzone flag

pub fn em_addmax(&mut self) -> EM_ADDMAX_W

Bits 0:15 - Upper limit for the exchange memory zone indicated by the em_inzone flag

impl W<u32, Reg<u32, _BB_DEBUGADDMIN>>

pub fn reg_addmin(&mut self) -> REG_ADDMIN_W

Bits 16:31 - Lower limit for the register zone indicated by the reg_inzone flag

pub fn em_addmin(&mut self) -> EM_ADDMIN_W

Bits 0:15 - Lower limit for the exchange memory zone indicated by the em_inzone flag

impl W<u32, Reg<u32, _BB_SWPROFILING>>

pub fn swprof(&mut self) -> SWPROF_W

Bits 0:31 - Software profiling register: used by RW-BLE software for profiling purpose

impl W<u32, Reg<u32, _BB_RADIOCNTL0>>

pub fn spiptr(&mut self) -> SPIPTR_W

Bits 16:31 - Pointer to the buffer containing data to be transferred to or received from the SPI port

pub fn spifreq(&mut self) -> SPIFREQ_W

Bits 4:5 - SPI clock frequency

pub fn spigo(&mut self) -> SPIGO_W

Bit 0 - Start SPI transfer when writing a 1

impl W<u32, Reg<u32, _BB_RADIOCNTL1>>

pub fn forceagc_en(&mut self) -> FORCEAGC_EN_W

Bit 31 - Control ATLAS/Ripple AGC force mode based on radioCNTL2-FORCEAGC_LENGTH value

pub fn forcebleiq(&mut self) -> FORCEBLEIQ_W

Bit 30 - Control Ripple modulation mode in between FM and I&Q

pub fn forceagc_length(&mut self) -> FORCEAGC_LENGTH_W

Bits 16:27 - Control ATLAS/Ripple AGC force mode based on radioCNTL2-FORCEAGC_LENGTH value

pub fn sync_pulse_mode(&mut self) -> SYNC_PULSE_MODE_W

Bit 15 - Define whether the SYNC_P pulse is generated as pulse or level

pub fn dpcorr_en(&mut self) -> DPCORR_EN_W

Bit 13 - Enable the use of delayed DC compensated data path in radio correlator block

pub fn jef_select(&mut self) -> JEF_SELECT_W

Bit 12 - Selects Jitter Elimination FIFO

pub fn xrfsel(&mut self) -> XRFSEL_W

Bits 4:8 - Extended radio selection field

pub fn subversion(&mut self) -> SUBVERSION_W

Bits 0:3 - CSEM RF Sub-version selection

impl W<u32, Reg<u32, _BB_RADIOCNTL2>>

pub fn freqtable_ptr(&mut self) -> FREQTABLE_PTR_W

Bits 0:15 - Frequency table pointer

impl W<u32, Reg<u32, _BB_RADIOPWRUPDN0>>

pub fn rxpwrup0(&mut self) -> RXPWRUP0_W

Bits 16:23 - This register holds the length in us of the RX power up phase for the current radio device

pub fn txpwrdn0(&mut self) -> TXPWRDN0_W

Bits 8:12 - This register extends the length in us of the TX power down phase for the current radio device

pub fn txpwrup0(&mut self) -> TXPWRUP0_W

Bits 0:7 - This register holds the length in us of the TX power up phase for the current radio device

impl W<u32, Reg<u32, _BB_RADIOPWRUPDN1>>

pub fn rxpwrup1(&mut self) -> RXPWRUP1_W

Bits 16:23 - This register holds the length in us of the RX power up phase for the current radio device

pub fn txpwrdn1(&mut self) -> TXPWRDN1_W

Bits 8:12 - This register extends the length in us of the TX power down phase for the current radio device

pub fn txpwrup1(&mut self) -> TXPWRUP1_W

Bits 0:7 - This register holds the length in us of the TX power up phase for the current radio device

impl W<u32, Reg<u32, _BB_RADIOTXRXTIM0>>

pub fn txpathdly0(&mut self) -> TXPATHDLY0_W

Bits 24:31

pub fn rxpathdly0(&mut self) -> RXPATHDLY0_W

Bits 16:20

pub fn rfrxtmda0(&mut self) -> RFRXTMDA0_W

Bits 8:14

pub fn sync_position0(&mut self) -> SYNC_POSITION0_W

Bits 0:6

impl W<u32, Reg<u32, _BB_RADIOTXRXTIM1>>

pub fn txpathdly1(&mut self) -> TXPATHDLY1_W

Bits 24:31

pub fn rxpathdly1(&mut self) -> RXPATHDLY1_W

Bits 16:20

pub fn rfrxtmda1(&mut self) -> RFRXTMDA1_W

Bits 8:14

pub fn sync_position1(&mut self) -> SYNC_POSITION1_W

Bits 0:6

impl W<u32, Reg<u32, _BB_SPIPTRCNTL0>>

pub fn txoffptr(&mut self) -> TXOFFPTR_W

Bits 16:31 - Pointer to the TxOFF sequence address section

pub fn txonptr(&mut self) -> TXONPTR_W

Bits 0:15 - Pointer to the TxON sequence address section

impl W<u32, Reg<u32, _BB_SPIPTRCNTL1>>

pub fn rxoffptr(&mut self) -> RXOFFPTR_W

Bits 16:31 - Pointer to the RxOFF sequence address section

pub fn rxonptr(&mut self) -> RXONPTR_W

Bits 0:15 - Pointer to the RxON sequence address section

impl W<u32, Reg<u32, _BB_SPIPTRCNTL2>>

pub fn rssiptr(&mut self) -> RSSIPTR_W

Bits 0:15 - Pointer to the RSSI read sequence address section

impl W<u32, Reg<u32, _BB_ADVCHMAP>>

pub fn advchmap(&mut self) -> ADVCHMAP_W

Bits 0:2 - Advertising channel map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39

impl W<u32, Reg<u32, _BB_ADVTIM>>

pub fn advint(&mut self) -> ADVINT_W

Bits 0:13 - Advertising packet interval defines the time interval in between two ADV_xxx packet sent (value in us)

impl W<u32, Reg<u32, _BB_WLPUBADDPTR>>

pub fn wlpubaddptr(&mut self) -> WLPUBADDPTR_W

Bits 0:15 - Start address pointer of the public devices white list

impl W<u32, Reg<u32, _BB_WLPRIVADDPTR>>

pub fn wlprivaddptr(&mut self) -> WLPRIVADDPTR_W

Bits 0:15 - Start address pointer of the private devices white list

impl W<u32, Reg<u32, _BB_WLNBDEV>>

pub fn nbprivdev(&mut self) -> NBPRIVDEV_W

Bits 8:15 - Number of private devices in the white list

pub fn nbpubdev(&mut self) -> NBPUBDEV_W

Bits 0:7 - Number of public devices in the white list

impl W<u32, Reg<u32, _BB_AESCNTL>>

pub fn aes_mode(&mut self) -> AES_MODE_W

Bit 1 - Cipher mode control

pub fn aes_start(&mut self) -> AES_START_W

Bit 0 - Starts AES-128 ciphering/deciphering process

impl W<u32, Reg<u32, _BB_AESKEY31_0>>

pub fn aeskey31_0(&mut self) -> AESKEY31_0_W

Bits 0:31 - AES encryption 128-bit key (bits 31 down to 0)

impl W<u32, Reg<u32, _BB_AESKEY63_32>>

pub fn aeskey63_32(&mut self) -> AESKEY63_32_W

Bits 0:31 - AES encryption 128-bit key (bits 63 down to 32)

impl W<u32, Reg<u32, _BB_AESKEY95_64>>

pub fn aeskey95_64(&mut self) -> AESKEY95_64_W

Bits 0:31 - AES encryption 128-bit key (bits 95 down to 64)

impl W<u32, Reg<u32, _BB_AESKEY127_96>>

pub fn aeskey127_96(&mut self) -> AESKEY127_96_W

Bits 0:31 - AES encryption 128-bit key (bits 127 down to 96)

impl W<u32, Reg<u32, _BB_AESPTR>>

pub fn aesptr(&mut self) -> AESPTR_W

Bits 0:15 - Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored.

impl W<u32, Reg<u32, _BB_RFTESTCNTL>>

pub fn infiniterx(&mut self) -> INFINITERX_W

Bit 31 - Applicable in RF test mode only

pub fn rxpktcnten(&mut self) -> RXPKTCNTEN_W

Bit 27 - Applicable in RF test mode only

pub fn infinitetx(&mut self) -> INFINITETX_W

Bit 15 - Applicable in RF test mode only

pub fn txlengthsrc(&mut self) -> TXLENGTHSRC_W

Bit 14 - Applicable only in Tx/Rx RF test mode

pub fn prbstype(&mut self) -> PRBSTYPE_W

Bit 13 - Applicable only in Tx/Rx RF test mode

pub fn txpldsrc(&mut self) -> TXPLDSRC_W

Bit 12 - Applicable only in Tx/Rx RF test mode

pub fn txpktcnten(&mut self) -> TXPKTCNTEN_W

Bit 11 - Applicable in RF test mode only

pub fn txlength(&mut self) -> TXLENGTH_W

Bits 0:8 - Tx packet length in number of byte

impl W<u32, Reg<u32, _BB_RFTESTTXSTAT>>

pub fn txpktcnt(&mut self) -> TXPKTCNT_W

Bits 0:31 - Reports number of transmitted packet during test modes

impl W<u32, Reg<u32, _BB_RFTESTRXSTAT>>

pub fn rxpktcnt(&mut self) -> RXPKTCNT_W

Bits 0:31 - Reports number of correctly received packet during test modes

impl W<u32, Reg<u32, _BB_TIMGENCNTL>>

pub fn apfm_en(&mut self) -> APFM_EN_W

Bit 31 - Controls the anticipated pre-fetch abort mechanism

pub fn prefetchabort_time(&mut self) -> PREFETCHABORT_TIME_W

Bits 16:25 - Defines the instant in us at which immediate abort is required after anticipated pre-fetch abort

pub fn prefetch_time(&mut self) -> PREFETCH_TIME_W

Bits 0:8 - Defines exchange table pre-fetch instant in us

impl W<u32, Reg<u32, _BB_GROSSTIMTGT>>

pub fn grosstarget(&mut self) -> GROSSTARGET_W

Bits 0:22 - Gross timer target value on which a ble_grosstgtim_irq must be generated (precision of 10ms)

impl W<u32, Reg<u32, _BB_FINETIMTGT>>

pub fn finetarget(&mut self) -> FINETARGET_W

Bits 0:26 - Fine timer target value on which a ble_finetgtim_irq must be generated (precision of 625us)

impl W<u32, Reg<u32, _BB_COEXIFCNTL0>>

pub fn mwsscanfreqmsk(&mut self) -> MWSSCANFREQMSK_W

Bits 24:25 - Determines how mws_scan_frequency impacts BLE Tx and Rx

pub fn wlcrxpriomode(&mut self) -> WLCRXPRIOMODE_W

Bits 20:21 - Defines BLE packet ble_rx mode behavior

pub fn wlctxpriomode(&mut self) -> WLCTXPRIOMODE_W

Bits 16:17 - Defines BLE packet ble_tx mode behavior

pub fn mwstxfreqmsk(&mut self) -> MWSTXFREQMSK_W

Bits 14:15 - Determines how MWS Tx Frequency impacts BLE Tx and Rx

pub fn mwsrxfreqmsk(&mut self) -> MWSRXFREQMSK_W

Bits 12:13 - Determines how MWS Rx Frequency impacts BLE Tx and Rx

pub fn mwstxmsk(&mut self) -> MWSTXMSK_W

Bits 10:11 - Determines how mws_tx impacts BLE Tx and Rx

pub fn mwsrxmsk(&mut self) -> MWSRXMSK_W

Bits 8:9 - Determines how mws_rx impacts BLE Tx and Rx

pub fn txmsk(&mut self) -> TXMSK_W

Bits 6:7 - Determines how TXx impact BLE Tx and Rx

pub fn rxmsk(&mut self) -> RXMSK_W

Bits 4:5 - Determines how RXx impact BLE Tx and Rx

pub fn mwswci_en(&mut self) -> MWSWCI_EN_W

Bit 3 - Enable / Disable control of the WCI MWS Coexistence interface / Valid in Dual Mode only

pub fn mwscoex_en(&mut self) -> MWSCOEX_EN_W

Bit 2 - Enable / Disable control of the MWS Coexistence control / Valid in Dual Mode only

pub fn syncgen_en(&mut self) -> SYNCGEN_EN_W

Bit 1 - Determines whether ble_sync is generated or not

pub fn coex_en(&mut self) -> COEX_EN_W

Bit 0 - Enable / disable control of the coexistence control

impl W<u32, Reg<u32, _BB_COEXIFCNTL1>>

pub fn wlcprxthr(&mut self) -> WLCPRXTHR_W

Bits 24:28 - Determines the threshold for Rx priority setting (applies on ble_rx if WLCRXPRIOMODE equals "10")

pub fn wlcptxthr(&mut self) -> WLCPTXTHR_W

Bits 16:20 - Determines the threshold for priority setting (applies on ble_tx if WLCTXPRIOMODE equals "10")

pub fn wlcpduration(&mut self) -> WLCPDURATION_W

Bits 8:14 - Determines how many us the priority information must be maintained (applies on ble_tx and ble_rx if WLCTXPRIOMODE equals "10")

pub fn wlcpdelay(&mut self) -> WLCPDELAY_W

Bits 0:6 - Determines the delay (in us) in Tx/Rx enables rises the time BLE Tx/Rx priority has to be provided (applies on ble_tx and ble_rx if WLCTXPRIOMODE equals "10")

impl W<u32, Reg<u32, _BB_COEXIFCNTL2>>

pub fn rx_ant_delay(&mut self) -> RX_ANT_DELAY_W

Bits 8:11 - Time (in us) by which is anticipated bt_rx to be provided before effective Radio receipt operation

pub fn tx_ant_delay(&mut self) -> TX_ANT_DELAY_W

Bits 0:3 - Time (in us) by which is anticipated bt_tx to be provided before effective Radio transmit operation

impl W<u32, Reg<u32, _BB_BBMPRIO0>>

pub fn blem7(&mut self) -> BLEM7_W

Bits 28:31 - Set priority value for passive scanning

pub fn blem6(&mut self) -> BLEM6_W

Bits 24:27 - Set priority value for non-connectable advertising

pub fn blem5(&mut self) -> BLEM5_W

Bits 20:23 - Set priority value for connectable advertising BLE message

pub fn blem4(&mut self) -> BLEM4_W

Bits 16:19 - Set priority value for active scanning BLE message

pub fn blem3(&mut self) -> BLEM3_W

Bits 12:15 - Set priority value for initiating (scanning) BLE message

pub fn blem2(&mut self) -> BLEM2_W

Bits 8:11 - Set priority value for data channel transmission BLE message

pub fn blem1(&mut self) -> BLEM1_W

Bits 4:7 - Set priority value for LLCP BLE message

pub fn blem0(&mut self) -> BLEM0_W

Bits 0:3 - Set priority value for initiating (connection request response) BLE message

impl W<u32, Reg<u32, _BB_BBMPRIO1>>

pub fn blemdefault(&mut self) -> BLEMDEFAULT_W

Bits 28:31 - Set default priority value for other BLE message than those defined above

pub fn blem9(&mut self) -> BLEM9_W

Bits 4:7 - Set default priority value for ISO Channel first Tx/Rx attempt

pub fn blem8(&mut self) -> BLEM8_W

Bits 0:3 - Set default priority value for ISO Channel subsequent Tx/Rx attempt

impl W<u32, Reg<u32, _BB_RALPTR>>

pub fn ralptr(&mut self) -> RALPTR_W

Bits 0:15 - Start address pointer of the RAL structure

impl W<u32, Reg<u32, _BB_RALNBDEV>>

pub fn ralnbdev(&mut self) -> RALNBDEV_W

Bits 0:7 - Number of devices in RAL Structure

impl W<u32, Reg<u32, _BB_RAL_LOCAL_RND>>

pub fn lrnd_init(&mut self) -> LRND_INIT_W

Bit 31 - Writing a 1 initializes of local RPA random number generation LFSR

pub fn lrnd_val(&mut self) -> LRND_VAL_W

Bits 0:21 - Initialization value for local RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value

impl W<u32, Reg<u32, _BB_RAL_PEER_RND>>

pub fn prnd_init(&mut self) -> PRND_INIT_W

Bit 31 - Writing a 1 initializes of peer RPA random number generation LFSR

pub fn prnd_val(&mut self) -> PRND_VAL_W

Bits 0:21 - Initialization value for peer RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value

impl W<u32, Reg<u32, _BB_ISOCHANCNTL0>>

pub fn retxacken0(&mut self) -> RETXACKEN0_W

Bit 4 - Generate Tx ACK

pub fn syncgen0(&mut self) -> SYNCGEN0_W

Bit 3 - Enable audio syn_p generation

pub fn isochanen0(&mut self) -> ISOCHANEN0_W

Bit 2 - Enable ISO channel

pub fn isotype0(&mut self) -> ISOTYPE0_W

Bits 0:1 - ISO Channel Type

impl W<u32, Reg<u32, _BB_ISOMUTECNTL0>>

pub fn togo0(&mut self) -> TOGO0_W

Bit 31 - Indicates which buffer is in use (direct copy of ET-ISOBUFSEL)

pub fn mute_sink0(&mut self) -> MUTE_SINK0_W

Bit 19 - HW mute control

pub fn mute_source0(&mut self) -> MUTE_SOURCE0_W

Bit 18 - HW mute control

pub fn invl0_1(&mut self) -> INVL0_1_W

Bit 17 - SW mute status for ISO buffer 1 (i.e updated when ET-ISOBUFSEL = 0)

pub fn invl0_0(&mut self) -> INVL0_0_W

Bit 16 - SW mute status for ISO buffer 0 (i.e updated when ET-ISOBUFSEL = 1)

pub fn mute_pattern0(&mut self) -> MUTE_PATTERN0_W

Bits 0:7 - Value of the ISO channel 0 Mute Pattern to be used when HW muting is enabled

impl W<u32, Reg<u32, _BB_ISOCURRENTTXPTR0>>

pub fn iso0txptr0(&mut self) -> ISO0TXPTR0_W

Bits 16:31 - Tx ISO Buffer pointer 0 of ISO Channel 0

pub fn iso0txptr1(&mut self) -> ISO0TXPTR1_W

Bits 0:15 - Tx ISO Buffer pointer 1 of ISO Channel 0

impl W<u32, Reg<u32, _BB_ISOCURRENTRXPTR0>>

pub fn iso0rxptr0(&mut self) -> ISO0RXPTR0_W

Bits 16:31 - Rx ISO Buffer pointer 0 of ISO Channel 0

pub fn iso0rxptr1(&mut self) -> ISO0RXPTR1_W

Bits 0:15 - Rx ISO Buffer pointer 1 of ISO Channel 0

impl W<u32, Reg<u32, _BB_ISOTRCNL0>>

pub fn iso0rxlen(&mut self) -> ISO0RXLEN_W

Bits 16:23 - Negotiated, maximum expected number of bytes for ISO Channel 0 Rx payloads

pub fn iso0txlen(&mut self) -> ISO0TXLEN_W

Bits 0:7 - Negotiated, number of bytes for ISO Channel 0 Tx payloads

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETL0>>

pub fn evt_cnt_offsetl0(&mut self) -> EVT_CNT_OFFSETL0_W

Bits 0:31 - LSB part of EVT_CNT_OFFSET0[39:0] field

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETU0>>

pub fn evt_cnt_offsetu0(&mut self) -> EVT_CNT_OFFSETU0_W

Bits 0:6 - MSB part of EVT_CNT_OFFSET0[39:0] field

impl W<u32, Reg<u32, _BB_ISOCHANCNTL1>>

pub fn retxacken1(&mut self) -> RETXACKEN1_W

Bit 4 - Generate Tx ACK

pub fn syncgen1(&mut self) -> SYNCGEN1_W

Bit 3 - Enable audio syn_p generation

pub fn isochanen1(&mut self) -> ISOCHANEN1_W

Bit 2 - Enable ISO channel

pub fn isotype1(&mut self) -> ISOTYPE1_W

Bits 0:1 - ISO Channel Type

impl W<u32, Reg<u32, _BB_ISOMUTECNTL1>>

pub fn togo1(&mut self) -> TOGO1_W

Bit 31 - Indicates which buffer is in use (direct copy of ET-ISOBUFSEL)

pub fn mute_sink1(&mut self) -> MUTE_SINK1_W

Bit 19 - HW mute control

pub fn mute_source1(&mut self) -> MUTE_SOURCE1_W

Bit 18 - HW mute control

pub fn invl1_1(&mut self) -> INVL1_1_W

Bit 17 - SW mute status for ISO buffer 1 (i.e updated when ET-ISOBUFSEL = 0)

pub fn invl1_0(&mut self) -> INVL1_0_W

Bit 16 - SW mute status for ISO buffer 0 (i.e updated when ET-ISOBUFSEL = 1)

pub fn mute_pattern1(&mut self) -> MUTE_PATTERN1_W

Bits 0:7 - Value of the ISO channel 0 Mute Pattern to be used when HW muting is enabled

impl W<u32, Reg<u32, _BB_ISOCURRENTTXPTR1>>

pub fn iso1txptr0(&mut self) -> ISO1TXPTR0_W

Bits 16:31 - Tx ISO Buffer pointer 0 of ISO Channel 1

pub fn iso1txptr1(&mut self) -> ISO1TXPTR1_W

Bits 0:15 - Tx ISO Buffer pointer 1 of ISO Channel 1

impl W<u32, Reg<u32, _BB_ISOCURRENTRXPTR1>>

pub fn iso1rxptr0(&mut self) -> ISO1RXPTR0_W

Bits 16:31 - Rx ISO Buffer pointer 0 of ISO Channel 1

pub fn iso1rxptr1(&mut self) -> ISO1RXPTR1_W

Bits 0:15 - Rx ISO Buffer pointer 1 of ISO Channel 1

impl W<u32, Reg<u32, _BB_ISOTRCNL1>>

pub fn iso1rxlen(&mut self) -> ISO1RXLEN_W

Bits 16:23 - Negotiated, maximum expected number of bytes for ISO Channel 0 Rx payloads

pub fn iso1txlen(&mut self) -> ISO1TXLEN_W

Bits 0:7 - Negotiated, number of bytes for ISO Channel 0 Tx payloads

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETL1>>

pub fn evt_cnt_offsetl1(&mut self) -> EVT_CNT_OFFSETL1_W

Bits 0:31 - LSB part of EVT_CNT_OFFSET0[39:0] field

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETU1>>

pub fn evt_cnt_offsetu1(&mut self) -> EVT_CNT_OFFSETU1_W

Bits 0:6 - MSB part of EVT_CNT_OFFSET0[39:0] field

impl W<u32, Reg<u32, _BB_ISOCHANCNTL2>>

pub fn retxacken2(&mut self) -> RETXACKEN2_W

Bit 4 - Generate Tx ACK

pub fn syncgen2(&mut self) -> SYNCGEN2_W

Bit 3 - Enable audio syn_p generation

pub fn isochanen2(&mut self) -> ISOCHANEN2_W

Bit 2 - Enable ISO channel

pub fn isotype2(&mut self) -> ISOTYPE2_W

Bits 0:1 - ISO Channel Type

impl W<u32, Reg<u32, _BB_ISOMUTECNTL2>>

pub fn togo2(&mut self) -> TOGO2_W

Bit 31 - Indicates which buffer is in use (direct copy of ET-ISOBUFSEL)

pub fn mute_sink2(&mut self) -> MUTE_SINK2_W

Bit 19 - HW mute control

pub fn mute_source2(&mut self) -> MUTE_SOURCE2_W

Bit 18 - HW mute control

pub fn invl2_1(&mut self) -> INVL2_1_W

Bit 17 - SW mute status for ISO buffer 1 (i.e updated when ET-ISOBUFSEL = 0)

pub fn invl2_0(&mut self) -> INVL2_0_W

Bit 16 - SW mute status for ISO buffer 0 (i.e updated when ET-ISOBUFSEL = 1)

pub fn mute_pattern2(&mut self) -> MUTE_PATTERN2_W

Bits 0:7 - Value of the ISO channel 0 Mute Pattern to be used when HW muting is enabled

impl W<u32, Reg<u32, _BB_ISOCURRENTTXPTR2>>

pub fn iso2txptr0(&mut self) -> ISO2TXPTR0_W

Bits 16:31 - Tx ISO Buffer pointer 0 of ISO Channel 2

pub fn iso2txptr1(&mut self) -> ISO2TXPTR1_W

Bits 0:15 - Tx ISO Buffer pointer 1 of ISO Channel 2

impl W<u32, Reg<u32, _BB_ISOCURRENTRXPTR2>>

pub fn iso2rxptr0(&mut self) -> ISO2RXPTR0_W

Bits 16:31 - Rx ISO Buffer pointer 0 of ISO Channel 2

pub fn iso2rxptr1(&mut self) -> ISO2RXPTR1_W

Bits 0:15 - Rx ISO Buffer pointer 1 of ISO Channel 2

impl W<u32, Reg<u32, _BB_ISOTRCNL2>>

pub fn iso2rxlen(&mut self) -> ISO2RXLEN_W

Bits 16:23 - Negotiated, maximum expected number of bytes for ISO Channel 2 Rx payloads

pub fn iso2txlen(&mut self) -> ISO2TXLEN_W

Bits 0:7 - Negotiated, number of bytes for ISO Channel 2 Tx payloads

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETL2>>

pub fn evt_cnt_offsetl2(&mut self) -> EVT_CNT_OFFSETL2_W

Bits 0:31 - LSB part of EVT_CNT_OFFSET2[39:0] field

impl W<u32, Reg<u32, _BB_ISOEVTCNTLOFFSETU2>>

pub fn evt_cnt_offsetu2(&mut self) -> EVT_CNT_OFFSETU2_W

Bits 0:6 - MSB part of EVT_CNT_OFFSET2[39:0] field

impl W<u32, Reg<u32, _BB_BBPRIOSCHARB>>

pub fn blepriomode(&mut self) -> BLEPRIOMODE_W

Bit 15 - Determine BLE priority scheduling arbitration mode

pub fn blemargin(&mut self) -> BLEMARGIN_W

Bits 0:7 - Determine the decision instant margin for priority scheduling arbitration

impl W<u32, Reg<u32, _RF_REG00>>

pub fn datawhite_btle_dw_btle(&mut self) -> DATAWHITE_BTLE_DW_BTLE_W

Bit 31 - If set to 1, the data whitening specified in the Bluetooth LE standard is used. Note that the en_datawhite field of the CODING register has also to be set to 1

pub fn datawhite_btle_dw_btle_rst(&mut self) -> DATAWHITE_BTLE_DW_BTLE_RST_W

Bits 24:30 - Reset value to put on the Bluetooth LE data whitening shift register

pub fn fourfsk_coding_en_fourfsk_coding(
    &mut self
) -> FOURFSK_CODING_EN_FOURFSK_CODING_W

Bit 23 - If set to 1 the 4FSK coding is activated

pub fn fourfsk_coding_tx_fourfsk_coding(
    &mut self
) -> FOURFSK_CODING_TX_FOURFSK_CODING_W

Bits 20:22 - Set the 4FSK coding (Tx): bit 0 determine if the sign is given by the Q signal (0) or I signal (1), bit 1 select if the signal is inverted for the sign, it 2 select if the signal is inverted for the abs amplitude

pub fn fourfsk_coding_rx_fourfsk_coding(
    &mut self
) -> FOURFSK_CODING_RX_FOURFSK_CODING_W

Bits 16:18 - Set the 4FSK decoding (Rx): bit 0 determine if the sign is given by the Q signal (0) or I signal (1), bit 1 select if the signal is inverted for the sign, it 2 select if the signal is inverted for the abs amplitude

pub fn mode2_diff_coding(&mut self) -> MODE2_DIFF_CODING_W

Bit 14 - If set to 1 enables the differential coding/decoding

pub fn mode2_psk_nfsk(&mut self) -> MODE2_PSK_NFSK_W

Bit 13 - If set to 1, the PSK mode is selected, FSK otherwise.

pub fn mode2_testmode(&mut self) -> MODE2_TESTMODE_W

Bits 8:12 - set the output testmode

pub fn mode_not_to_idle(&mut self) -> MODE_NOT_TO_IDLE_W

Bit 7 - In FSM mode, if set to 1 indicates to the FSM to go in suspend mode after a Tx or Rx packet

pub fn mode_en_fsm(&mut self) -> MODE_EN_FSM_W

Bit 5 - If set to 1 enables the radio FSM

pub fn mode_en_deserializer(&mut self) -> MODE_EN_DESERIALIZER_W

Bit 4 - If set to 1 enables the deserializer

pub fn mode_en_serializer(&mut self) -> MODE_EN_SERIALIZER_W

Bit 3 - If set to 1 enables the serializer

pub fn mode_tx_nrx(&mut self) -> MODE_TX_NRX_W

Bit 2 - if set to 1 use the Tx, otherwise the Rx

pub fn mode_mode(&mut self) -> MODE_MODE_W

Bits 0:1 - Select the working mode of the digital baseband: 00) the digital baseband is off (no ck) 01) the clock is generated but the blocks are reset (Tx,Rx,FIFOs and FSM) 10) 10: the digital baseband is freezed 11) working

impl W<u32, Reg<u32, _RF_REG01>>

pub fn tau_phase_recov_tau_phase_recov(
    &mut self
) -> TAU_PHASE_RECOV_TAU_PHASE_RECOV_W

Bits 24:31 - Time constant of the fine carrier recovery block

pub fn tau_rough_recov_tau_rough_recov(
    &mut self
) -> TAU_ROUGH_RECOV_TAU_ROUGH_RECOV_W

Bits 16:23 - Time constant of the rough carrier recovery block

pub fn carrier_recovery_en_correct_cfreq_afc(
    &mut self
) -> CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC_W

Bit 15 - If set to 1, enables the automatic AFC correction.

pub fn carrier_recovery_correct_cfreq_if_neg(
    &mut self
) -> CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG_W

Bit 14 - If set to 1, the IF correction is negative

pub fn carrier_recovery_en_correct_cfreq_if(
    &mut self
) -> CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF_W

Bit 13 - If set to 1, enables the automatic IF correction

pub fn carrier_recovery_afc_neg(&mut self) -> CARRIER_RECOVERY_AFC_NEG_W

Bit 12 - If set to 1 correct the AFC negatively

pub fn carrier_recovery_starter_mode(
    &mut self
) -> CARRIER_RECOVERY_STARTER_MODE_W

Bit 11 - If set to 1 enables the starter mode, i.e. a 32x faster carrier recovery.

pub fn carrier_recovery_en_afc(&mut self) -> CARRIER_RECOVERY_EN_AFC_W

Bit 10 - if set to 1 enables the Automatic Frequency Control

pub fn carrier_recovery_en_fine_recov(
    &mut self
) -> CARRIER_RECOVERY_EN_FINE_RECOV_W

Bit 9 - If set to 1 enables the fine carrier recovery

pub fn carrier_recovery_en_rough_recov(
    &mut self
) -> CARRIER_RECOVERY_EN_ROUGH_RECOV_W

Bit 8 - If set to 1 enables the rough carrier recovery

pub fn mod_tx_pulse_nsym(&mut self) -> MOD_TX_PULSE_NSYM_W

Bit 6 - If set to 1, the Tx pulse shape is an odd function.

pub fn mod_tx_en_interp(&mut self) -> MOD_TX_EN_INTERP_W

Bit 5 - If set to 1, enables the Tx CIC interpolator.

pub fn mod_tx_ck_tx_m(&mut self) -> MOD_TX_CK_TX_M_W

Bits 0:4 - Unsigned value that determine the Tx CIC interpolator frequency. The formula is similar to the evaluation of the oversampling frequency.

impl W<u32, Reg<u32, _RF_REG02>>

pub fn fifo_fifo_flush_on_ovflw(&mut self) -> FIFO_FIFO_FLUSH_ON_OVFLW_W

Bit 31 - If set to 1, stops the Rx and flushes the FIFO in case of overflow

pub fn fifo_fifo_flush_on_addr_err(&mut self) -> FIFO_FIFO_FLUSH_ON_ADDR_ERR_W

Bit 30 - If set to 1, stops the Rx and flushes the FIFO in case of address error

pub fn fifo_fifo_flush_on_pl_err(&mut self) -> FIFO_FIFO_FLUSH_ON_PL_ERR_W

Bit 29 - If set to 1, stops the Rx and flushes the FIFO in case of packet length error

pub fn fifo_fifo_flush_on_crc_err(&mut self) -> FIFO_FIFO_FLUSH_ON_CRC_ERR_W

Bit 28 - If set to 1, stops the Rx and flushes the FIFO in case of CRC error

pub fn fifo_rx_fifo_ack(&mut self) -> FIFO_RX_FIFO_ACK_W

Bit 27 - If set to 1, the Rx FIFO needs an acknowledgement (packet received correctly) to change its state.

pub fn fifo_fifo_thr(&mut self) -> FIFO_FIFO_THR_W

Bits 24:26 - Threshold indicating the 'almost full' state

pub fn datarate_offset_datarate_offset(
    &mut self
) -> DATARATE_OFFSET_DATARATE_OFFSET_W

Bits 16:23 - Data-rate offset. Is a signed value and the full scale (0x7f) corresponds to a data-rate offset of 12.5 percent.

pub fn tau_datarate_recov_tau_datarate_recov(
    &mut self
) -> TAU_DATARATE_RECOV_TAU_DATARATE_RECOV_W

Bits 8:15 - Time constant of the data-rate recovery

pub fn tau_clk_recov_tau_clk_recov(&mut self) -> TAU_CLK_RECOV_TAU_CLK_RECOV_W

Bits 0:7 - Time constant of the clock recovery

impl W<u32, Reg<u32, _RF_REG03>>

pub fn pad_conf_2_pad_3_conf(&mut self) -> PAD_CONF_2_PAD_3_CONF_W

Bits 28:31 - Configuration of GPIO pad 3

pub fn pad_conf_2_pad_2_conf(&mut self) -> PAD_CONF_2_PAD_2_CONF_W

Bits 24:27 - Configuration of GPIO pad 2

pub fn pad_conf_1_pad_1_conf(&mut self) -> PAD_CONF_1_PAD_1_CONF_W

Bits 20:23 - Configuration of GPIO pad 1

pub fn pad_conf_1_pad_0_conf(&mut self) -> PAD_CONF_1_PAD_0_CONF_W

Bits 16:19 - Configuration of GPIO pad 0

pub fn irq_conf_irq_high_z(&mut self) -> IRQ_CONF_IRQ_HIGH_Z_W

Bit 15 - If set to 1, the pads are set to High-Z when the IRQ is not active.

pub fn irq_conf_irq_active_low(&mut self) -> IRQ_CONF_IRQ_ACTIVE_LOW_W

Bit 14 - If set to 1, the IRQ are active low

pub fn irq_conf_irqs_mask(&mut self) -> IRQ_CONF_IRQS_MASK_W

Bits 8:13 - Mask to determine which IRQs are enabled (active high)

pub fn fifo_2_fifo_thr_tx(&mut self) -> FIFO_2_FIFO_THR_TX_W

Bits 5:7 - Threshold indicating the 'almost empty' state

pub fn fifo_2_wait_txfifo_wr(&mut self) -> FIFO_2_WAIT_TXFIFO_WR_W

Bit 4 - If set to 1, the FSM will wait a Tx FIFO write before starting the Tx in case of an empty Tx FIFO.

pub fn fifo_2_stop_on_rxff_ovflw(&mut self) -> FIFO_2_STOP_ON_RXFF_OVFLW_W

Bit 3 - If set to 1, stops the reception in case of a FIFO overflow.

pub fn fifo_2_stop_on_txff_unflw(&mut self) -> FIFO_2_STOP_ON_TXFF_UNFLW_W

Bit 2 - If set to 1, stops the transmission in case of a FIFO underflow.

pub fn fifo_2_rxff_flush_on_start(&mut self) -> FIFO_2_RXFF_FLUSH_ON_START_W

Bit 1 - If set to 1, flushes the Rx FIFO when the Rx is enabled, in order to receive a packet with an empty FIFO.

pub fn fifo_2_txff_flush_on_stop(&mut self) -> FIFO_2_TXFF_FLUSH_ON_STOP_W

Bit 0 - If set to 1, flushes the Tx FIFO after the end of a packet transmission in order to have an empty FIFO.

impl W<u32, Reg<u32, _RF_REG04>>

pub fn mac_conf_mac_timer_gr(&mut self) -> MAC_CONF_MAC_TIMER_GR_W

Bits 30:31 - MAC timer granularity. The granularity is given by (2^(2mac_timer_gr))x1us

pub fn mac_conf_rx_mac_act(&mut self) -> MAC_CONF_RX_MAC_ACT_W

Bit 29 - If set to 1, the FSM will switch to Rx or Tx after an Rx mode.

pub fn mac_conf_rx_mac_tx_nrx(&mut self) -> MAC_CONF_RX_MAC_TX_NRX_W

Bit 28 - If set to 1, the FSM will switch to Tx after an Rx mode, Rx otherwise.

pub fn mac_conf_rx_mac_start_nstop(&mut self) -> MAC_CONF_RX_MAC_START_NSTOP_W

Bit 27 - If set to 1, the MAC timer is activated at the reception of the sync word, at the end of the packet otherwise.

pub fn mac_conf_tx_mac_act(&mut self) -> MAC_CONF_TX_MAC_ACT_W

Bit 26 - If set to 1, the FSM will switch to Rx or Tx after a Tx mode.

pub fn mac_conf_tx_mac_tx_nrx(&mut self) -> MAC_CONF_TX_MAC_TX_NRX_W

Bit 25 - If set to 1, the FSM will switch to Tx after an Tx mode, Rx otherwise.

pub fn mac_conf_tx_mac_start_nstop(&mut self) -> MAC_CONF_TX_MAC_START_NSTOP_W

Bit 24 - If set to 1, the MAC timer is activated at beginning of the packet, otherwise at the end of the packet transmission.

pub fn pad_conf_5_pad_9_conf(&mut self) -> PAD_CONF_5_PAD_9_CONF_W

Bits 20:23 - Configuration of GPIO pad 9

pub fn pad_conf_5_pad_8_conf(&mut self) -> PAD_CONF_5_PAD_8_CONF_W

Bits 16:19 - Configuration of GPIO pad 8

pub fn pad_conf_4_pad_7_conf(&mut self) -> PAD_CONF_4_PAD_7_CONF_W

Bits 12:15 - Configuration of GPIO pad 7

pub fn pad_conf_4_pad_6_conf(&mut self) -> PAD_CONF_4_PAD_6_CONF_W

Bits 8:11 - Configuration of GPIO pad 6

pub fn pad_conf_3_pad_5_conf(&mut self) -> PAD_CONF_3_PAD_5_CONF_W

Bits 4:7 - Configuration of GPIO pad 5

pub fn pad_conf_3_pad_4_conf(&mut self) -> PAD_CONF_3_PAD_4_CONF_W

Bits 0:3 - Configuration of GPIO pad 4

impl W<u32, Reg<u32, _RF_REG05>>

pub fn channel_switch_iq(&mut self) -> CHANNEL_SWITCH_IQ_W

Bit 30 - Switch I and Q channels

pub fn channel_channel(&mut self) -> CHANNEL_CHANNEL_W

Bits 24:29 - Channel number

pub fn bank_datarate_tx_nrx(&mut self) -> BANK_DATARATE_TX_NRX_W

Bit 18 - Select the data-rate register: 0-> Rx data-rate, 1-> Tx data-rate

pub fn bank_bank(&mut self) -> BANK_BANK_W

Bits 16:17 - Select the used bank

pub fn tx_mac_timer_tx_mac_timer(&mut self) -> TX_MAC_TIMER_TX_MAC_TIMER_W

Bits 8:15 - Time to wait after the Tx mode.

pub fn rx_mac_timer_rx_mac_timer(&mut self) -> RX_MAC_TIMER_RX_MAC_TIMER_W

Bits 0:7 - Time to wait after the Rx mode.

impl W<u32, Reg<u32, _RF_CENTER_FREQ>>

pub fn center_freq_adapt_cfreq(&mut self) -> CENTER_FREQ_ADAPT_CFREQ_W

Bit 31 - If set to 1, automatically adapt frequency between Tx and Rx.

pub fn center_freq_rx_div_5_n6(&mut self) -> CENTER_FREQ_RX_DIV_5_N6_W

Bit 30 - If set to 1, the ratio of the pll reference between Tx and Rx is 5 instead of 6.

pub fn center_freq_center_frequency(&mut self) -> CENTER_FREQ_CENTER_FREQUENCY_W

Bits 0:29 - Set the center frequency

impl W<u32, Reg<u32, _RF_REG07>>

pub fn channels_1_channel_spacing_lo(
    &mut self
) -> CHANNELS_1_CHANNEL_SPACING_LO_W

Bits 16:31 - channel spacing: the formula that determines this value is the same as for the central frequency. v=ch_sp/144e6*2^25

pub fn mod_info_rx_en_div_2_n3_rx(&mut self) -> MOD_INFO_RX_EN_DIV_2_N3_RX_W

Bit 14 - If set to 1 the clock divider will provide a clock divided by 2 instead of 3.

pub fn mod_info_rx_symbol_2bit_rx(&mut self) -> MOD_INFO_RX_SYMBOL_2BIT_RX_W

Bit 13 - If set to 1, each symbol is composed by 2 bits (OQPSK or 4FSK)

pub fn mod_info_rx_dr_m_rx(&mut self) -> MOD_INFO_RX_DR_M_RX_W

Bits 8:12 - Unsigned value that determine the oversampling frequency and consequently the data-rate. This frequency is the system frequency (16 or 24 MHz) divided by this value+1.

pub fn mod_info_tx_en_div_2_n3_tx(&mut self) -> MOD_INFO_TX_EN_DIV_2_N3_TX_W

Bit 6 - If set to 1 the clock divider will provide a clock divided by 2 instead of 3.

pub fn mod_info_tx_symbol_2bit_tx(&mut self) -> MOD_INFO_TX_SYMBOL_2BIT_TX_W

Bit 5 - If set to 1, each symbol is composed by 2 bits (OQPSK or 4FSK)

pub fn mod_info_tx_dr_m_tx(&mut self) -> MOD_INFO_TX_DR_M_TX_W

Bits 0:4 - Unsigned value that determine the oversampling frequency and consequently the data-rate. This frequency is the system frequency (16 or 24 MHz) divided by this value+1.

impl W<u32, Reg<u32, _RF_REG08>>

pub fn packet_length_packet_len(&mut self) -> PACKET_LENGTH_PACKET_LEN_W

Bits 24:31 - The packet length in the fixed packet length mode. In the variable packet length mode, it specifies the maximal packet length defined by the standard. In case of error a packet_len_err is raised.

pub fn packet_handling_lsb_first(&mut self) -> PACKET_HANDLING_LSB_FIRST_W

Bit 23 - If set to 1, the LSB is the first bit to be sent, the MSB otherwise

pub fn packet_handling_en_crc(&mut self) -> PACKET_HANDLING_EN_CRC_W

Bit 22 - If set to 1, enables the automatic CRC evaluation and insertion

pub fn packet_handling_en_crc_on_pktlen(
    &mut self
) -> PACKET_HANDLING_EN_CRC_ON_PKTLEN_W

Bit 21 - If set to 1, enables the CRC calculation on the packet length part of the packet.

pub fn packet_handling_en_preamble(&mut self) -> PACKET_HANDLING_EN_PREAMBLE_W

Bit 20 - If set to 1, enables the automatic preamble insertion

pub fn packet_handling_en_multi_frame(
    &mut self
) -> PACKET_HANDLING_EN_MULTI_FRAME_W

Bit 19 - If set to 1, enables the multi-frame packet (preamble-pattern-data-CRC-data-CRC-...)

pub fn packet_handling_enb_dw_on_crc(
    &mut self
) -> PACKET_HANDLING_ENB_DW_ON_CRC_W

Bit 18 - Enables the data-whitening on the CRC (active low)

pub fn packet_handling_en_pattern(&mut self) -> PACKET_HANDLING_EN_PATTERN_W

Bit 17 - If set to 1, enables the automatic pattern insertion and recognition

pub fn packet_handling_en_packet(&mut self) -> PACKET_HANDLING_EN_PACKET_W

Bit 16 - If set to 1 enables the packet handler

pub fn coding_en_datawhite(&mut self) -> CODING_EN_DATAWHITE_W

Bit 15 - If set to 1 enables the data-whitening

pub fn coding_i_nq_delayed(&mut self) -> CODING_I_NQ_DELAYED_W

Bit 14 - If set to 1, the channel I is considered 'delayed' in case of a 2bit per symbol modulaton

pub fn coding_offset(&mut self) -> CODING_OFFSET_W

Bit 13 - If set to 1, an offset (delay) is introduced in one of the two channels (2 bits per symbol modulation).

pub fn coding_bit_invert(&mut self) -> CODING_BIT_INVERT_W

Bit 12 - If set to 1, it inverts the bit value (Tx and Rx)

pub fn coding_even_before_odd(&mut self) -> CODING_EVEN_BEFORE_ODD_W

Bit 11 - Determines the bit order in case of a 2 bits per symbol modulation: if set to 1 the first bit (bit 0, even) goes to the I path

pub fn coding_en_802154_l2f(&mut self) -> CODING_EN_802154_L2F_W

Bit 10 - If set to 1 enables the linear to frequency encoding needed in order to modulate an OQPSK as an MSK.

pub fn coding_en_802154_b2c(&mut self) -> CODING_EN_802154_B2C_W

Bit 9 - If set to 1 enables the bit to chips encoding used in the IEEE 802.15.4 standard

pub fn coding_en_manchester(&mut self) -> CODING_EN_MANCHESTER_W

Bit 8 - If set to 1 enables the Manchester encoding

pub fn channels_2_en_channel_sel(&mut self) -> CHANNELS_2_EN_CHANNEL_SEL_W

Bit 7 - If set to 1 enables the definition of channels

pub fn channels_2_channel_spacing_hi(
    &mut self
) -> CHANNELS_2_CHANNEL_SPACING_HI_W

Bits 0:3 - channel spacing: the formula that determines this value is the same as for the central frequency. v=ch_sp/144e6*2^25

impl W<u32, Reg<u32, _RF_REG09>>

pub fn address_conf_address_len(&mut self) -> ADDRESS_CONF_ADDRESS_LEN_W

Bit 27 - If set to 1 the address length is 16 bits, 8 otherwise.

pub fn address_conf_en_address_rx_br(
    &mut self
) -> ADDRESS_CONF_EN_ADDRESS_RX_BR_W

Bit 26 - If set to 1 enables the broadcast address detection on Rx.

pub fn address_conf_en_address_rx(&mut self) -> ADDRESS_CONF_EN_ADDRESS_RX_W

Bit 25 - If set to 1 enables the address detection on Rx

pub fn address_conf_en_address_tx(&mut self) -> ADDRESS_CONF_EN_ADDRESS_TX_W

Bit 24 - If set to 1 enables the address insertion on Tx

pub fn preamble_length_preamble_len(&mut self) -> PREAMBLE_LENGTH_PREAMBLE_LEN_W

Bits 16:23 - Length of the preamble -1

pub fn preamble_preamble(&mut self) -> PREAMBLE_PREAMBLE_W

Bits 8:15 - Preamble to be inserted

pub fn packet_length_opts_en_packet_len_fix(
    &mut self
) -> PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX_W

Bit 6 - If set to 1, the packet length is fixed and specified in the PACKET_LEN register

pub fn packet_length_opts_packet_len_corr(
    &mut self
) -> PACKET_LENGTH_OPTS_PACKET_LEN_CORR_W

Bits 2:5 - Signed value that specifies the correction to apply to the specified packet length (due to differences between standards). The packet length here is specified by the byte number after the packet length byte, with the exclusion of the CRC.

pub fn packet_length_opts_packet_len_pos(
    &mut self
) -> PACKET_LENGTH_OPTS_PACKET_LEN_POS_W

Bits 0:1 - Unsigned value that specifies the position of the packet length after the pattern

impl W<u32, Reg<u32, _RF_REG0A>>

pub fn address_broadcast_address_br(&mut self) -> ADDRESS_BROADCAST_ADDRESS_BR_W

Bits 16:31 - Broadcast address

pub fn address_address(&mut self) -> ADDRESS_ADDRESS_W

Bits 0:15 - Address of the node

impl W<u32, Reg<u32, _RF_SYNC_PATTERN>>

pub fn pattern(&mut self) -> PATTERN_W

Bits 0:31 - Pattern (sync word) to be inserted or recognized.

impl W<u32, Reg<u32, _RF_REG0C>>

pub fn conv_codes_poly_cc_poly_2(&mut self) -> CONV_CODES_POLY_CC_POLY_2_W

Bits 26:30 - polynom of the third convolutional code

pub fn conv_codes_poly_cc_poly_1(&mut self) -> CONV_CODES_POLY_CC_POLY_1_W

Bits 21:25 - polynom of the second convolutional code

pub fn conv_codes_poly_cc_poly_0(&mut self) -> CONV_CODES_POLY_CC_POLY_0_W

Bits 16:20 - polynom of the first convolutional code

pub fn conv_codes_conf_cc_viterbi_len(
    &mut self
) -> CONV_CODES_CONF_CC_VITERBI_LEN_W

Bits 10:11 - Set the memory length of the viterbi decoder: 00 => 5, 01 => 10, 10 => 20, 11 => 30

pub fn conv_codes_conf_cc_en_tx_stop(
    &mut self
) -> CONV_CODES_CONF_CC_EN_TX_STOP_W

Bit 9 - if set to 1 enables the stop word at the end of the transmission. Necessary in order to keep a stream coherent with the convolutional coding

pub fn conv_codes_conf_en_conv_code(&mut self) -> CONV_CODES_CONF_EN_CONV_CODE_W

Bit 8 - If set to 1 enablse the convolutional codes

pub fn packet_extra_stop_word_len(&mut self) -> PACKET_EXTRA_STOP_WORD_LEN_W

Bits 6:7 - length of the stop word, same as the pattern word length

pub fn packet_extra_en_stop_word(&mut self) -> PACKET_EXTRA_EN_STOP_WORD_W

Bit 5 - If set to 1 adds the stop word (0x00) after the CRC

pub fn packet_extra_pkt_info_pre_npost(
    &mut self
) -> PACKET_EXTRA_PKT_INFO_PRE_NPOST_W

Bit 4 - If set to 1 the packet information are sampled at the end of the packet instead of the sync word detection.

pub fn packet_extra_pattern_max_err(&mut self) -> PACKET_EXTRA_PATTERN_MAX_ERR_W

Bits 2:3 - unsigned value that specifies the maximum number of errors in the pattern recognition

pub fn packet_extra_pattern_word_len(
    &mut self
) -> PACKET_EXTRA_PATTERN_WORD_LEN_W

Bits 0:1 - Pattern word length: 00 => 8bits, 01 => 16 bits, 10 => 24 bits, 11 => 32 bits

impl W<u32, Reg<u32, _RF_CRC_POLYNOMIAL>>

pub fn crc_polynomial_crc_poly(&mut self) -> CRC_POLYNOMIAL_CRC_POLY_W

Bits 0:31 - CRC polynomial. It is coded using the Koopman notation, i.e. the nth bit codes the (n+1) coefficient. Example: x^16+x^12+x^5+1 => 0x8810

impl W<u32, Reg<u32, _RF_CRC_RST>>

pub fn crc_rst_crc_rst(&mut self) -> CRC_RST_CRC_RST_W

Bits 0:31 - CRC reset value

impl W<u32, Reg<u32, _RF_REG0F>>

pub fn rx_frac_conf_rx_frac_den(&mut self) -> RX_FRAC_CONF_RX_FRAC_DEN_W

Bits 28:31

pub fn rx_frac_conf_rx_frac_num(&mut self) -> RX_FRAC_CONF_RX_FRAC_NUM_W

Bits 24:27

pub fn frac_conf_tx_frac_gain(&mut self) -> FRAC_CONF_TX_FRAC_GAIN_W

Bit 19

pub fn frac_conf_rx_frac_gain(&mut self) -> FRAC_CONF_RX_FRAC_GAIN_W

Bit 18

pub fn frac_conf_tx_en_frac(&mut self) -> FRAC_CONF_TX_EN_FRAC_W

Bit 17

pub fn frac_conf_rx_en_frac(&mut self) -> FRAC_CONF_RX_EN_FRAC_W

Bit 16

pub fn conv_codes_punct_cc_punct_2(&mut self) -> CONV_CODES_PUNCT_CC_PUNCT_2_W

Bits 10:14 - puncture of the third convolutional code

pub fn conv_codes_punct_cc_punct_1(&mut self) -> CONV_CODES_PUNCT_CC_PUNCT_1_W

Bits 5:9 - puncture of the second convolutional code

pub fn conv_codes_punct_cc_punct_0(&mut self) -> CONV_CODES_PUNCT_CC_PUNCT_0_W

Bits 0:4 - puncture of the first convolutional code

impl W<u32, Reg<u32, _RF_REG10>>

pub fn frontend2_resample_ph_gain(&mut self) -> FRONTEND2_RESAMPLE_PH_GAIN_W

Bits 29:31 - Gain of the phase resampling block

pub fn frontend2_resample_rssi_g2(&mut self) -> FRONTEND2_RESAMPLE_RSSI_G2_W

Bits 26:28 - Gain of the decimator in the RSSI resampling block

pub fn frontend2_resample_rssi_g1(&mut self) -> FRONTEND2_RESAMPLE_RSSI_G1_W

Bits 24:25 - Gain of the interpolator in the RSSI resampling block

pub fn frontend_en_phadc_deglitch(&mut self) -> FRONTEND_EN_PHADC_DEGLITCH_W

Bit 22 - If set to 1 enables the phADC deglitcher

pub fn frontend_en_resample_rssi(&mut self) -> FRONTEND_EN_RESAMPLE_RSSI_W

Bit 21 - If set to 1 enables the RSSI resampling

pub fn frontend_en_resample_phadc(&mut self) -> FRONTEND_EN_RESAMPLE_PHADC_W

Bit 20 - If set to 1 enables the phase resampling

pub fn frontend_div_phadc(&mut self) -> FRONTEND_DIV_PHADC_W

Bits 16:19 - Unsigned value that specifies the divider to obtain the phADC clock (and RSSI).

pub fn tx_mult_tx_mult_exp(&mut self) -> TX_MULT_TX_MULT_EXP_W

Bits 12:15 - Exponent of the Tx multiplier

pub fn tx_mult_tx_mult_man(&mut self) -> TX_MULT_TX_MULT_MAN_W

Bits 8:11 - Mantissa of the Tx multiplier

pub fn tx_frac_conf_tx_frac_den(&mut self) -> TX_FRAC_CONF_TX_FRAC_DEN_W

Bits 4:7

pub fn tx_frac_conf_tx_frac_num(&mut self) -> TX_FRAC_CONF_TX_FRAC_NUM_W

Bits 0:3

impl W<u32, Reg<u32, _RF_TX_PULSE0>>

pub fn tx_pulse_shape_1_tx_coef4(&mut self) -> TX_PULSE_SHAPE_1_TX_COEF4_W

Bits 24:31

pub fn tx_pulse_shape_1_tx_coef3(&mut self) -> TX_PULSE_SHAPE_1_TX_COEF3_W

Bits 16:23

pub fn tx_pulse_shape_1_tx_coef2(&mut self) -> TX_PULSE_SHAPE_1_TX_COEF2_W

Bits 8:15

pub fn tx_pulse_shape_1_tx_coef1(&mut self) -> TX_PULSE_SHAPE_1_TX_COEF1_W

Bits 0:7 - These registers specify the Tx pulse shape. The pulse shape is formed by: coef1-coef16-coef16-coef1. Since the oversampling ratio is 8, the pulse shape is 4 symbols long. Every coefficient is an 8 bits signed.

impl W<u32, Reg<u32, _RF_TX_PULSE1>>

pub fn tx_pulse_shape_2_tx_coef8(&mut self) -> TX_PULSE_SHAPE_2_TX_COEF8_W

Bits 24:31

pub fn tx_pulse_shape_2_tx_coef7(&mut self) -> TX_PULSE_SHAPE_2_TX_COEF7_W

Bits 16:23

pub fn tx_pulse_shape_2_tx_coef6(&mut self) -> TX_PULSE_SHAPE_2_TX_COEF6_W

Bits 8:15

pub fn tx_pulse_shape_2_tx_coef5(&mut self) -> TX_PULSE_SHAPE_2_TX_COEF5_W

Bits 0:7

impl W<u32, Reg<u32, _RF_TX_PULSE2>>

pub fn tx_pulse_shape_3_tx_coef12(&mut self) -> TX_PULSE_SHAPE_3_TX_COEF12_W

Bits 24:31

pub fn tx_pulse_shape_3_tx_coef11(&mut self) -> TX_PULSE_SHAPE_3_TX_COEF11_W

Bits 16:23

pub fn tx_pulse_shape_3_tx_coef10(&mut self) -> TX_PULSE_SHAPE_3_TX_COEF10_W

Bits 8:15

pub fn tx_pulse_shape_3_tx_coef9(&mut self) -> TX_PULSE_SHAPE_3_TX_COEF9_W

Bits 0:7

impl W<u32, Reg<u32, _RF_TX_PULSE3>>

pub fn tx_pulse_shape_4_tx_coef16(&mut self) -> TX_PULSE_SHAPE_4_TX_COEF16_W

Bits 24:31

pub fn tx_pulse_shape_4_tx_coef15(&mut self) -> TX_PULSE_SHAPE_4_TX_COEF15_W

Bits 16:23

pub fn tx_pulse_shape_4_tx_coef14(&mut self) -> TX_PULSE_SHAPE_4_TX_COEF14_W

Bits 8:15

pub fn tx_pulse_shape_4_tx_coef13(&mut self) -> TX_PULSE_SHAPE_4_TX_COEF13_W

Bits 0:7

impl W<u32, Reg<u32, _RF_RX_PULSE>>

pub fn rx_pulse_shape_rx_coef8(&mut self) -> RX_PULSE_SHAPE_RX_COEF8_W

Bits 28:31

pub fn rx_pulse_shape_rx_coef7(&mut self) -> RX_PULSE_SHAPE_RX_COEF7_W

Bits 24:27

pub fn rx_pulse_shape_rx_coef6(&mut self) -> RX_PULSE_SHAPE_RX_COEF6_W

Bits 20:23

pub fn rx_pulse_shape_rx_coef5(&mut self) -> RX_PULSE_SHAPE_RX_COEF5_W

Bits 16:19

pub fn rx_pulse_shape_rx_coef4(&mut self) -> RX_PULSE_SHAPE_RX_COEF4_W

Bits 12:15

pub fn rx_pulse_shape_rx_coef3(&mut self) -> RX_PULSE_SHAPE_RX_COEF3_W

Bits 8:11

pub fn rx_pulse_shape_rx_coef2(&mut self) -> RX_PULSE_SHAPE_RX_COEF2_W

Bits 4:7

pub fn rx_pulse_shape_rx_coef1(&mut self) -> RX_PULSE_SHAPE_RX_COEF1_W

Bits 0:3 - These registers specify the Rx pulse shape. The pulse shape is formed by: coef1-coef8-coef8-coef1. Since the oversampling ratio is 8, the pulse shape is 2 symbols long. Coefficients from coef4 to coef8 are unsigned, while coef1 to coef3 are signed.

impl W<u32, Reg<u32, _RF_REG16>>

pub fn rx_if_resample_ph_if(&mut self) -> RX_IF_RESAMPLE_PH_IF_W

Bits 25:28 - IF value for the phase resampler.

pub fn rx_if_if2_clk_os(&mut self) -> RX_IF_IF2_CLK_OS_W

Bits 16:24 - IF value for the carrier recovery

pub fn fsk_fcr_amp_1_fsk_fcr_amp1(&mut self) -> FSK_FCR_AMP_1_FSK_FCR_AMP1_W

Bits 8:15 - FSK amplitude 1 (lowest): in FSK w/o ISI is used to specify the expected amplitude. In 4FSK is the lowest amplitude (+/-1). in FSK w/ ISI it specify the lowest amplitude (generally it corresponds to a sequence 0-1-0.

pub fn filter_gain_dr_limit(&mut self) -> FILTER_GAIN_DR_LIMIT_W

Bits 6:7 - Set the data-rate recovery limits: 00 => 0 percent, 01 => 3.125 percent, 10 => 6.25 percent, 11 => 12.5 percent

pub fn filter_gain_filter_gain_m(&mut self) -> FILTER_GAIN_FILTER_GAIN_M_W

Bits 3:5 - Mantissa of the final stage gain of the matched filter

pub fn filter_gain_filter_gain_e(&mut self) -> FILTER_GAIN_FILTER_GAIN_E_W

Bits 0:2 - Exponent of the final stage gain of the matched filter

impl W<u32, Reg<u32, _RF_REG17>>

pub fn fsk_fcr_amp_3_fsk_fcr_amp3(&mut self) -> FSK_FCR_AMP_3_FSK_FCR_AMP3_W

Bits 24:31 - FSK amplitude 3 (highest): in 4FSK is the high amplitude (+/-3). in FSK w/ ISI it specify the highet amplitude (generally it corresponds to a sequence 1-1-1.

pub fn fsk_fcr_amp_2_fsk_fcr_amp2(&mut self) -> FSK_FCR_AMP_2_FSK_FCR_AMP2_W

Bits 16:23 - FSK amplitude 2 (mid): in 4FSK is the threshold. in FSK w/ ISI it specify the mid amplitude (generally it corresponds to a sequence 0-1-1 or 1-1-0.

pub fn carrier_recovery_extra_max_err_in_dl_sync(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_MAX_ERR_IN_DL_SYNC_W

Bits 13:14 - Set the maximum errors in the delay line sync detection

pub fn carrier_recovery_extra_en_sync_ok_delay_line(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_EN_SYNC_OK_DELAY_LINE_W

Bit 12 - If set to 1 uses the pattern_ok signal in delay line to synchronize the deserializer

pub fn carrier_recovery_extra_nc_sel_out(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_NC_SEL_OUT_W

Bits 9:11 - Select the output position for the 'not-causal processing': 000 => 4 symbol, 001 => 6 symbols, 010 => 8 symbols, 011 => 12 symbols, 100 => 16 symbols, 101 => 24 symbols, 110 => 32 symbols, 111 => 40 symbols

pub fn carrier_recovery_extra_en_not_causal(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_EN_NOT_CAUSAL_W

Bit 8 - if set to 1 enables the not causal processing

pub fn carrier_recovery_extra_freq_limit_man(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN_W

Bits 4:6 - Mantissa of the carrier recovery frequency limit (unsigned).

pub fn carrier_recovery_extra_freq_limit_exp(
    &mut self
) -> CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP_W

Bits 0:2 - Exponent of the carrier recovery frequency limit (signed). Formula: carrier_offset_max=(1+m/8)2^e/4f_sym

impl W<u32, Reg<u32, _RF_REG18>>

pub fn correct_cfreq_if_correct_cfreq_if(
    &mut self
) -> CORRECT_CFREQ_IF_CORRECT_CFREQ_IF_W

Bits 16:31 - Unsigned value that specifies the IF for the Rx mode.

pub fn rssi_bank_rssi_tri_ck_div(&mut self) -> RSSI_BANK_RSSI_TRI_CK_DIV_W

Bits 14:15 - Speed on the RSSI triangular dithering signal (cf reg RSSI_TUN)

pub fn rssi_bank_fast_rssi(&mut self) -> RSSI_BANK_FAST_RSSI_W

Bit 13 - If set to 1, the RSSI filtering is 8x faster

pub fn rssi_bank_en_fast_pre_sync(&mut self) -> RSSI_BANK_EN_FAST_PRE_SYNC_W

Bit 12 - If the packet mode is set, indicates to switch the fast modes during the preamble reception

pub fn rssi_bank_tau_rssi_filtering(&mut self) -> RSSI_BANK_TAU_RSSI_FILTERING_W

Bits 8:11 - Time constant of the RSSI filtering block: 0: 4symbols, 1: 8symbols, 2: 16 symbols, 3: 32symbols, 4: 64symbols, 5: 128symbols, 6: 256symbols, 7: 512symbols, 8: 1024symbols

pub fn decision_use_vit_soft(&mut self) -> DECISION_USE_VIT_SOFT_W

Bit 4 - If set to 1 uses the viterbi soft decoding

pub fn decision_viterbi_len(&mut self) -> DECISION_VITERBI_LEN_W

Bits 2:3 - Sets the Viterbi path length: 00: 1 bit, 01: 2 bits, 10: 4 bits, 11: 8 bits

pub fn decision_viterbi_pow_nlin(&mut self) -> DECISION_VITERBI_POW_NLIN_W

Bit 1 - if set to 1, the Viterbi algorithm uses power instead of amplitude to evaluate the error on the path

pub fn decision_en_viterbi_gfsk(&mut self) -> DECISION_EN_VITERBI_GFSK_W

Bit 0 - If set to 1 enables the Viterbi algorithm for the GFSK decoding; this will override the old ISI correction algorithm.

impl W<u32, Reg<u32, _RF_REG19>>

pub fn pll_bank_pll_filter_res_trim_tx(
    &mut self
) -> PLL_BANK_PLL_FILTER_RES_TRIM_TX_W

Bits 28:29 - Same as pll_filter_res_trim but for Tx case. Real value in Tx is pll_filter_res_trim xor pll_filter_res_trim_tx. If set to 0, Tx and Rx have the same value.

pub fn pll_bank_iq_pll_0_tx(&mut self) -> PLL_BANK_IQ_PLL_0_TX_W

Bits 24:27 - Charge pump bias for Tx case. Real value in Tx is iq_pll_0 xor iq_pll_0_tx. If set to 0, Tx and Rx have the same value.

pub fn pll_bank_low_dr_tx(&mut self) -> PLL_BANK_LOW_DR_TX_W

Bit 22 - If set to 1 the Tx will work in low data-rate mode

pub fn pll_bank_pll_filter_res_trim(&mut self) -> PLL_BANK_PLL_FILTER_RES_TRIM_W

Bits 20:21 - Allow to modify the value of the loop filter resistor R2 when bit 5 is high (TX mode): 00 => normal resistor (R_2_typ), 01 => 123 percent, 10 => 130 percent 11 => 170 percent

pub fn pll_bank_iq_pll_0(&mut self) -> PLL_BANK_IQ_PLL_0_W

Bits 16:19 - Charge pump bias

pub fn pa_pwr_min_pa_pwr(&mut self) -> PA_PWR_MIN_PA_PWR_W

Bit 13 - Sets the minimum power during the PA ramp-up: if 0 the ramp-up starts at -3, if 1 the ramp-up

pub fn pa_pwr_pa_pwr(&mut self) -> PA_PWR_PA_PWR_W

Bits 8:12 - Signed value that sets the PA power: minimum value is -3 (-40dBm), max value is 12 (3.3dBm).

pub fn clk_ch_filter_div_rssi(&mut self) -> CLK_CH_FILTER_DIV_RSSI_W

Bits 4:7 - Unsigned value that specifies the division factor for the clock controlling the RSSI.

pub fn clk_ch_filter_div_filt(&mut self) -> CLK_CH_FILTER_DIV_FILT_W

Bits 0:3 - Unsigned value that specifies the division factor for the clock controlling the channel filter.

impl W<u32, Reg<u32, _RF_REG1A>>

pub fn att_ctrl_att_ctrl_max(&mut self) -> ATT_CTRL_ATT_CTRL_MAX_W

Bits 28:31 - Maximum attenuation level in AGC algorithm

pub fn att_ctrl_set_rx_att_ctrl(&mut self) -> ATT_CTRL_SET_RX_ATT_CTRL_W

Bits 24:27 - Attuenuation level if the AGC is bypassed

pub fn rssi_ctrl_agc_decay_tau(&mut self) -> RSSI_CTRL_AGC_DECAY_TAU_W

Bits 22:23 - Time constant of the decay speed; high values corresponds to a slow decay

pub fn rssi_ctrl_agc_use_lna(&mut self) -> RSSI_CTRL_AGC_USE_LNA_W

Bit 21 - If set to 1 the AGC algorithm uses the LNA bias.

pub fn rssi_ctrl_agc_mode(&mut self) -> RSSI_CTRL_AGC_MODE_W

Bit 20 - Select the AGC algorithm: 0 -> old algorithm, 1 -> new algorithm

pub fn rssi_ctrl_agc_wait(&mut self) -> RSSI_CTRL_AGC_WAIT_W

Bits 18:19 - Sets the wait time of the AGC after switching between states: 00 => don't wait, 01 => wait 1x RSSI filtering period, 10 => wait 2x RSSI filtering period, 11 => wait 3x RSSI filtering period

pub fn rssi_ctrl_payload_blocks_agc(&mut self) -> RSSI_CTRL_PAYLOAD_BLOCKS_AGC_W

Bit 17 - If set to 1, the AGC is blocked during the payload

pub fn rssi_ctrl_bypass_agc(&mut self) -> RSSI_CTRL_BYPASS_AGC_W

Bit 16 - If set to 1, the AGC algorithm is bypassed

pub fn filter_bias_iq_fi_bw(&mut self) -> FILTER_BIAS_IQ_FI_BW_W

Bits 8:12 - Bias for the bandwidth of the channel filter

pub fn filter_bias_iq_fi_fc(&mut self) -> FILTER_BIAS_IQ_FI_FC_W

Bits 0:4 - Bias for the central frequency of the channel filter

impl W<u32, Reg<u32, _RF_REG1B>>

pub fn ieee802154_opts_en_dw_test(&mut self) -> IEEE802154_OPTS_EN_DW_TEST_W

Bit 31 - If set to 1 enables the Tx data-whitening before the convolutional code block

pub fn ieee802154_opts_ber_clk_mode(&mut self) -> IEEE802154_OPTS_BER_CLK_MODE_W

Bits 29:30 - sets the clock output mode for BER mode or RW mode: 00 => data change on falling edge, 01 => data change on rising edge, 10 => clock signal is a toggled signal, 11 => enable signal from clock recovery

pub fn ieee802154_opts_rx_data_not_sampled(
    &mut self
) -> IEEE802154_OPTS_RX_DATA_NOT_SAMPLED_W

Bit 28 - If set to 1, the signal rx_data in testmodes is not sampled. Used for debug purposes

pub fn ieee802154_opts_en_l2f_rx(&mut self) -> IEEE802154_OPTS_EN_L2F_RX_W

Bit 27 - if set to 1 enables the frequency to linear conversion in the Rx side (always controlled by the en_802154_l2f configuration bit).

pub fn ieee802154_opts_c2b_thr(&mut self) -> IEEE802154_OPTS_C2B_THR_W

Bits 24:26 - Threshold of the chip2bit correlator of the IEEE 802.15.4 protocol.

pub fn agc_peak_det_peak_det_tau(&mut self) -> AGC_PEAK_DET_PEAK_DET_TAU_W

Bits 20:23 - Time constant of the peak detector monostable circuit; if set to 0 the monostable is bypassed

pub fn agc_peak_det_peak_det_thr_low(
    &mut self
) -> AGC_PEAK_DET_PEAK_DET_THR_LOW_W

Bits 18:19 - Threshold for the low level of the peak detector: 0 => 0, 1 => 1, 2 => 2, 3 => N.A.

pub fn agc_peak_det_peak_det_thr_high(
    &mut self
) -> AGC_PEAK_DET_PEAK_DET_THR_HIGH_W

Bit 17 - Threshold for the high level of the peak detector: 0 => 2, 1 => 3

pub fn agc_peak_det_en_agc_peak(&mut self) -> AGC_PEAK_DET_EN_AGC_PEAK_W

Bit 16 - If set to 1 enables the AGC peak detector

pub fn agc_thr_high_agc_thr_high(&mut self) -> AGC_THR_HIGH_AGC_THR_HIGH_W

Bits 8:15 - AGC threshold high level

pub fn agc_thr_low_agc_thr_low(&mut self) -> AGC_THR_LOW_AGC_THR_LOW_W

Bits 0:7 - AGC threshold low level

impl W<u32, Reg<u32, _RF_AGC_LUT1>>

pub fn agc_lut_1_agc_level_2_lo(&mut self) -> AGC_LUT_1_AGC_LEVEL_2_LO_W

Bits 22:31 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_1_agc_level_1(&mut self) -> AGC_LUT_1_AGC_LEVEL_1_W

Bits 11:21 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_1_agc_level_0(&mut self) -> AGC_LUT_1_AGC_LEVEL_0_W

Bits 0:10 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

impl W<u32, Reg<u32, _RF_AGC_LUT2>>

pub fn agc_lut_2_agc_level_5_lo(&mut self) -> AGC_LUT_2_AGC_LEVEL_5_LO_W

Bits 23:31 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_2_agc_level_4(&mut self) -> AGC_LUT_2_AGC_LEVEL_4_W

Bits 12:22 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_2_agc_level_3(&mut self) -> AGC_LUT_2_AGC_LEVEL_3_W

Bits 1:11 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_2_agc_level_2_hi(&mut self) -> AGC_LUT_2_AGC_LEVEL_2_HI_W

Bit 0 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

impl W<u32, Reg<u32, _RF_AGC_LUT3>>

pub fn agc_lut_3_agc_level_8_lo(&mut self) -> AGC_LUT_3_AGC_LEVEL_8_LO_W

Bits 24:31 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_3_agc_level_7(&mut self) -> AGC_LUT_3_AGC_LEVEL_7_W

Bits 13:23 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_3_agc_level_6(&mut self) -> AGC_LUT_3_AGC_LEVEL_6_W

Bits 2:12 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_3_agc_level_5_hi(&mut self) -> AGC_LUT_3_AGC_LEVEL_5_HI_W

Bits 0:1 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

impl W<u32, Reg<u32, _RF_AGC_LUT4>>

pub fn agc_lut_4_agc_level_11_lo(&mut self) -> AGC_LUT_4_AGC_LEVEL_11_LO_W

Bits 25:31 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_4_agc_level_10(&mut self) -> AGC_LUT_4_AGC_LEVEL_10_W

Bits 14:24 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_4_agc_level_9(&mut self) -> AGC_LUT_4_AGC_LEVEL_9_W

Bits 3:13 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

pub fn agc_lut_4_agc_level_8_hi(&mut self) -> AGC_LUT_4_AGC_LEVEL_8_HI_W

Bits 0:2 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

impl W<u32, Reg<u32, _RF_REG20>>

pub fn timings_3_t_dll(&mut self) -> TIMINGS_3_T_DLL_W

Bits 28:31 - Time needed by the DLL blocks to switch on.

pub fn timings_3_t_pll_tx(&mut self) -> TIMINGS_3_T_PLL_TX_W

Bits 24:27 - Time needed by the PLL blocks in Tx mode to switch on.

pub fn timings_2_t_subband_tx(&mut self) -> TIMINGS_2_T_SUBBAND_TX_W

Bits 20:23 - Time needed by the subband algorithm to calibrate in Tx.

pub fn timings_2_t_tx_rf(&mut self) -> TIMINGS_2_T_TX_RF_W

Bits 16:19 - Time needed by the Tx RF blocks to switch on.

pub fn timings_1_t_granularity_tx(&mut self) -> TIMINGS_1_T_GRANULARITY_TX_W

Bits 12:14 - Fixes the granularity of the timer in Tx mode. The granularity is given by (2^(t_granularity-2))x1us

pub fn timings_1_t_granularity_rx(&mut self) -> TIMINGS_1_T_GRANULARITY_RX_W

Bits 8:10 - Fixes the granularity of the timer in Rx mode. The granularity is given by (2^(t_granularity))x1us

pub fn agc_lut_5_agc_level_11_hi(&mut self) -> AGC_LUT_5_AGC_LEVEL_11_HI_W

Bits 0:3 - Look up table with the AGC values: agc_level_0 is supposed the lowest attenuation, while agc_level_11 is the one with a maximum of attenuation.

impl W<u32, Reg<u32, _RF_AGC_ATT1>>

pub fn agc_att_1_agc_att_ab_lo(&mut self) -> AGC_ATT_1_AGC_ATT_AB_LO_W

Bits 30:31

pub fn agc_att_1_agc_att_9a(&mut self) -> AGC_ATT_1_AGC_ATT_9A_W

Bits 27:29

pub fn agc_att_1_agc_att_89(&mut self) -> AGC_ATT_1_AGC_ATT_89_W

Bits 24:26

pub fn agc_att_1_agc_att_78(&mut self) -> AGC_ATT_1_AGC_ATT_78_W

Bits 21:23

pub fn agc_att_1_agc_att_67(&mut self) -> AGC_ATT_1_AGC_ATT_67_W

Bits 18:20

pub fn agc_att_1_agc_att_56(&mut self) -> AGC_ATT_1_AGC_ATT_56_W

Bits 15:17

pub fn agc_att_1_agc_att_45(&mut self) -> AGC_ATT_1_AGC_ATT_45_W

Bits 12:14

pub fn agc_att_1_agc_att_34(&mut self) -> AGC_ATT_1_AGC_ATT_34_W

Bits 9:11

pub fn agc_att_1_agc_att_23(&mut self) -> AGC_ATT_1_AGC_ATT_23_W

Bits 6:8

pub fn agc_att_1_agc_att_12(&mut self) -> AGC_ATT_1_AGC_ATT_12_W

Bits 3:5

pub fn agc_att_1_agc_att_01(&mut self) -> AGC_ATT_1_AGC_ATT_01_W

Bits 0:2 - These fields specify the attenuation levels

impl W<u32, Reg<u32, _RF_REG22>>

pub fn timing_fast_rx_en_fast_rx_txfilt(
    &mut self
) -> TIMING_FAST_RX_EN_FAST_RX_TXFILT_W

Bit 29 - If set to 1 enables filter Tx configuration for the fast Rx PLL

pub fn timing_fast_rx_en_fast_rx(&mut self) -> TIMING_FAST_RX_EN_FAST_RX_W

Bit 28 - If set to 1 enables the fast Rx PLL

pub fn timing_fast_rx_t_rx_fast_chp(&mut self) -> TIMING_FAST_RX_T_RX_FAST_CHP_W

Bits 24:27 - Time to switch off the fast CHP in Rx mode

pub fn timings_5_t_rx_rf(&mut self) -> TIMINGS_5_T_RX_RF_W

Bits 20:23 - Time needed by the Rx RF blocks to switch on.

pub fn timings_5_t_rx_bb(&mut self) -> TIMINGS_5_T_RX_BB_W

Bits 16:19 - Time needed by the Rx BB blocks to switch on.

pub fn timings_4_t_subband_rx(&mut self) -> TIMINGS_4_T_SUBBAND_RX_W

Bits 12:15 - Time needed by the subband algorithm to calibrate in Rx

pub fn timings_4_t_pll_rx(&mut self) -> TIMINGS_4_T_PLL_RX_W

Bits 8:11 - Time needed by the PLL blocks in Rx mode to switch on.

pub fn agc_att_2_agc_att_1db(&mut self) -> AGC_ATT_2_AGC_ATT_1DB_W

Bit 1 - If set to 1 the attenuation are specified by 1dB steps from 4dB to 11dB

pub fn agc_att_2_agc_att_ab_hi(&mut self) -> AGC_ATT_2_AGC_ATT_AB_HI_W

Bit 0

impl W<u32, Reg<u32, _RF_REG23>>

pub fn bias_1_iq_rxtx_3(&mut self) -> BIAS_1_IQ_RXTX_3_W

Bits 28:31 - PrePA Casc bias

pub fn bias_1_iq_rxtx_2(&mut self) -> BIAS_1_IQ_RXTX_2_W

Bits 24:27 - PrePA In bias

pub fn bias_0_iq_rxtx_1(&mut self) -> BIAS_0_IQ_RXTX_1_W

Bits 20:23 - PA backoff bias

pub fn bias_0_iq_rxtx_0(&mut self) -> BIAS_0_IQ_RXTX_0_W

Bits 16:19 - PA bias

pub fn interface_conf_apb_wait_state(
    &mut self
) -> INTERFACE_CONF_APB_WAIT_STATE_W

Bits 12:14 - Select the number of wait states during the APB transaction

pub fn interface_conf_spi_select(&mut self) -> INTERFACE_CONF_SPI_SELECT_W

Bits 8:9 - Select the spi mode: 00 legacy spi, 01 advanced spi, 10 BLIM4SME spi

pub fn timeout_en_rx_timeout(&mut self) -> TIMEOUT_EN_RX_TIMEOUT_W

Bit 7 - If set to 1 enables the timeout of the Rx when the system is on FSM mode

pub fn timeout_t_timeout_gr(&mut self) -> TIMEOUT_T_TIMEOUT_GR_W

Bits 4:6 - Granularity of the timer in timeout Rx mode

pub fn timeout_t_rx_timeout(&mut self) -> TIMEOUT_T_RX_TIMEOUT_W

Bits 0:3 - Time that has to occur before the timeout.

impl W<u32, Reg<u32, _RF_REG24>>

pub fn bias_5_iq_pll_4_rx(&mut self) -> BIAS_5_IQ_PLL_4_RX_W

Bits 28:31 - VCO bias for Rx

pub fn bias_5_iq_pll_4_tx(&mut self) -> BIAS_5_IQ_PLL_4_TX_W

Bits 24:27 - VCO bias for Tx

pub fn bias_4_iq_pll_2(&mut self) -> BIAS_4_IQ_PLL_2_W

Bits 20:23 - Sub-band comparator bias

pub fn bias_4_iq_pll_1(&mut self) -> BIAS_4_IQ_PLL_1_W

Bits 16:19 - Dynamic divider bias

pub fn bias_3_iq_rxtx_8(&mut self) -> BIAS_3_IQ_RXTX_8_W

Bits 12:15 - IFA ctrl_c bias

pub fn bias_3_iq_rxtx_7(&mut self) -> BIAS_3_IQ_RXTX_7_W

Bits 8:11 - IFA ctrl_r bias

pub fn bias_2_iq_rxtx_6(&mut self) -> BIAS_2_IQ_RXTX_6_W

Bits 4:7 - VCOM_MX bias

pub fn bias_2_iq_rxtx_5(&mut self) -> BIAS_2_IQ_RXTX_5_W

Bits 0:3 - VCOM_LO bias

impl W<u32, Reg<u32, _RF_REG25>>

pub fn bias_9_iq_bb_6(&mut self) -> BIAS_9_IQ_BB_6_W

Bits 28:31 - Peak detector threshold bias 0

pub fn bias_9_iq_bb_5(&mut self) -> BIAS_9_IQ_BB_5_W

Bits 24:27 - Peak detector bias

pub fn bias_8_iq_bb_4(&mut self) -> BIAS_8_IQ_BB_4_W

Bits 20:23 - RSSI_D bias

pub fn bias_8_iq_bb_3(&mut self) -> BIAS_8_IQ_BB_3_W

Bits 16:19 - RSSI_G bias

pub fn bias_7_iq_bb_2(&mut self) -> BIAS_7_IQ_BB_2_W

Bits 12:15 - ACD_L bias

pub fn bias_7_iq_bb_1(&mut self) -> BIAS_7_IQ_BB_1_W

Bits 8:11 - ACD_C bias

pub fn bias_6_iq_bb_0(&mut self) -> BIAS_6_IQ_BB_0_W

Bits 4:7 - ACD_O bias

pub fn bias_6_iq_pll_3(&mut self) -> BIAS_6_IQ_PLL_3_W

Bits 0:3 - DLL bias

impl W<u32, Reg<u32, _RF_REG26>>

pub fn sd_mash_mash_enable(&mut self) -> SD_MASH_MASH_ENABLE_W

Bit 28 - Enable the sigma delta mash

pub fn sd_mash_mash_dither(&mut self) -> SD_MASH_MASH_DITHER_W

Bit 27 - Enable dithering on the sigma delta mash

pub fn sd_mash_mash_order(&mut self) -> SD_MASH_MASH_ORDER_W

Bits 25:26 - Order of the sigma delta mash

pub fn sd_mash_mash_rstb(&mut self) -> SD_MASH_MASH_RSTB_W

Bit 24 - Reset of the sigma delta mash (active low)

pub fn bias_12_lna_agc_bias_3(&mut self) -> BIAS_12_LNA_AGC_BIAS_3_W

Bits 20:23 - LNA bias for AGC lvl 3

pub fn bias_12_lna_agc_bias_2(&mut self) -> BIAS_12_LNA_AGC_BIAS_2_W

Bits 16:19 - LNA bias for AGC lvl 2

pub fn bias_11_lna_agc_bias_1(&mut self) -> BIAS_11_LNA_AGC_BIAS_1_W

Bits 12:15 - LNA bias for AGC lvl 1

pub fn bias_11_lna_agc_bias_0(&mut self) -> BIAS_11_LNA_AGC_BIAS_0_W

Bits 8:11 - LNA bias for AGC lvl 0

pub fn bias_10_iq_bb_8(&mut self) -> BIAS_10_IQ_BB_8_W

Bits 4:7 - Peak detector threshold bias 1

pub fn bias_10_iq_bb_7(&mut self) -> BIAS_10_IQ_BB_7_W

Bits 0:3 - Peak detector threshold bias 2

impl W<u32, Reg<u32, _RF_REG27>>

pub fn ctrl_adc_one_ck_rssi_phadc(&mut self) -> CTRL_ADC_ONE_CK_RSSI_PHADC_W

Bit 31 - If set to 1, the RSSI and the phADC share the same clock

pub fn ctrl_adc_phadc_dellatch(&mut self) -> CTRL_ADC_PHADC_DELLATCH_W

Bits 29:30 - phADC delay latch trimming

pub fn ctrl_adc_ctrl_adc(&mut self) -> CTRL_ADC_CTRL_ADC_W

Bits 24:28 - bits(1:0) => phADC reset delay, bits(3:2) phADC clock delay, bit(4) phADC latch idle

pub fn bias_en_2_en_ptat(&mut self) -> BIAS_EN_2_EN_PTAT_W

Bit 19 - Enable PTAT

pub fn bias_en_2_en_bias_bb_hi(&mut self) -> BIAS_EN_2_EN_BIAS_BB_HI_W

Bits 16:18 - Bias enable for BB (same order as biases)

pub fn bias_en_1_en_bias_bb_lo(&mut self) -> BIAS_EN_1_EN_BIAS_BB_LO_W

Bits 12:15 - Bias enable for BB (same order as biases)

pub fn bias_en_1_en_bias_pll(&mut self) -> BIAS_EN_1_EN_BIAS_PLL_W

Bits 7:11 - Bias enable for PLL (same order as biases)

pub fn bias_en_1_en_bias_rxtx(&mut self) -> BIAS_EN_1_EN_BIAS_RXTX_W

Bits 0:6 - Bias enable for RxTx (same order as biases)

impl W<u32, Reg<u32, _RF_REG28>>

pub fn ctrl_rx_switch_lp(&mut self) -> CTRL_RX_SWITCH_LP_W

Bit 31 - If set to 1 switch the low-pass filter in the Rx chain

pub fn ctrl_rx_use_peak_detector(&mut self) -> CTRL_RX_USE_PEAK_DETECTOR_W

Bit 30 - If set to 1, the peak detector is powered on during the Rx by the FSM

pub fn ctrl_rx_start_mix_on_cal(&mut self) -> CTRL_RX_START_MIX_ON_CAL_W

Bit 29 - If set to 1, the mixer is enabled during the sub-band selection phase

pub fn ctrl_rx_ctrl_rx(&mut self) -> CTRL_RX_CTRL_RX_W

Bits 24:28 - bits(1:0) => resonance 1 LNA, bits(3:2) => resonance 2 LNA, bit(4) => IFA PTAT-R only

pub fn swcap_fsm_sb_cap_rx(&mut self) -> SWCAP_FSM_SB_CAP_RX_W

Bits 20:23 - VCO subband selection (Rx in FSM mode)

pub fn swcap_fsm_sb_cap_tx(&mut self) -> SWCAP_FSM_SB_CAP_TX_W

Bits 16:19 - VCO subband selection (Tx in FSM mode)

pub fn dll_ctrl_ck_last_sel_delay(&mut self) -> DLL_CTRL_CK_LAST_SEL_DELAY_W

Bit 10

pub fn dll_ctrl_ck_first_sel_delay(&mut self) -> DLL_CTRL_CK_FIRST_SEL_DELAY_W

Bit 9

pub fn dll_ctrl_ck_ext_sel(&mut self) -> DLL_CTRL_CK_EXT_SEL_W

Bit 8 - Low: input clock comes from ck_xtal pin (default). High: input clock comes from ck_ext pin

pub fn dll_ctrl_ck_dig_en(&mut self) -> DLL_CTRL_CK_DIG_EN_W

Bit 7 - Debug: enable to use the alternate ck_dig pin to output the PLL reference clock signal

pub fn dll_ctrl_ck_test_en(&mut self) -> DLL_CTRL_CK_TEST_EN_W

Bit 6 - Debug: enable to output on GPIO the PLL reference clock signal via ck_test pin

pub fn dll_ctrl_too_fast_enb(&mut self) -> DLL_CTRL_TOO_FAST_ENB_W

Bit 5 - When low, enable auxiliary wide lock range phase detector when fast mode locking is enabled (fast_enb = 0). When high, only the narrow lock range phase detector is enabled and bit 2 (fast_enb) must be high to avoid false frequency lock (slow mode locking)

pub fn dll_ctrl_locked_det_en(&mut self) -> DLL_CTRL_LOCKED_DET_EN_W

Bit 4 - Enable reference frequency multiplier locked detector. When this signal is high, the dll_locked output goes high when the output multiplied clock is nearly about three times the frequency of the input clock.

pub fn dll_ctrl_locked_auto_check_en(
    &mut self
) -> DLL_CTRL_LOCKED_AUTO_CHECK_EN_W

Bit 3 - If for some reason the reference frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing) and this signal is high, the frequency multiplier will try to lock again automatically. Otherwise, a manual reset should be performed via dll_rstb input(see Table 3) to relock the frequency multiplier. This mode only works if bit 4 is also high (locked detector enabled, see below)

pub fn dll_ctrl_fast_enb(&mut self) -> DLL_CTRL_FAST_ENB_W

Bit 2 - Enable, when low, fast mode locking of the reference frequency multiplier (default). Bit 5 must also be set low in this mode of operation (see below)

pub fn dll_ctrl_ck_sel(&mut self) -> DLL_CTRL_CK_SEL_W

Bits 0:1 - Selection of the clock used as frequency reference of the PLL (also to ck_test and ck_dig outputs): 00 => ref = ck_xtal ot ck_ext (if bit 8 is high), 01 => ref = same as ck_sel = 00 if dll_en = 0, otherwise frequency(ref) = 3x frequency(ck_xtal) or 3x frequency(ck_ext) (if bit 8 is high), 10 => ref = same as ck_sel = 01 but output frequency divided by 2 (used in normal RX mode when dll_en = 0), 11 => ref = same as ck_sel = 01 but output frequency divided by 5 (used for RX mode with external signal at 132 MHz when dll_en = 0)

impl W<u32, Reg<u32, _RF_PLL_CTRL>>

pub fn xtal_trim_xtal_trim(&mut self) -> XTAL_TRIM_XTAL_TRIM_W

Bits 24:31 - trimming of the xtal: 5MSB thermometric, 3LSB direct

pub fn pll_ctrl_2_pll_rx_48meg(&mut self) -> PLL_CTRL_2_PLL_RX_48MEG_W

Bit 20 - If set to 1 the PLL is set to 48MHz in Rx instead of 24MHz (need also to change ck_sel)

pub fn pll_ctrl_2_swcap_tx_same_rx(&mut self) -> PLL_CTRL_2_SWCAP_TX_SAME_RX_W

Bit 19 - If set to 1, in case of swcap_fsm=1, the register for Rx and Tx swcap is the same

pub fn pll_ctrl_2_swcap_fsm(&mut self) -> PLL_CTRL_2_SWCAP_FSM_W

Bit 18 - If set to 1 use the swcap_fsm register as reference for the sub-band selection

pub fn pll_ctrl_2_dll_rstb(&mut self) -> PLL_CTRL_2_DLL_RSTB_W

Bit 17 - Reset signal of the DLL (active low)

pub fn pll_ctrl_2_vco_subband_trim_hi(
    &mut self
) -> PLL_CTRL_2_VCO_SUBBAND_TRIM_HI_W

Bit 16 - VCO sub-band selection bits

pub fn pll_ctrl_1_vco_subband_trim_lo(
    &mut self
) -> PLL_CTRL_1_VCO_SUBBAND_TRIM_LO_W

Bits 13:15 - VCO sub-band selection bits

pub fn pll_ctrl_1_sub_sel_offs_en(&mut self) -> PLL_CTRL_1_SUB_SEL_OFFS_EN_W

Bit 12 - Add offset to sub-band selection comparator

pub fn pll_ctrl_1_div2_clkvco_test_en(
    &mut self
) -> PLL_CTRL_1_DIV2_CLKVCO_TEST_EN_W

Bit 11 - Debug: VCO signal divided by the programmable divider is divided by a: 0 => division ratio set to 1, 1 => division ratio set to 2; before to be outputted to ck_div_test

pub fn pll_ctrl_1_vcodiv_clk_test_en(
    &mut self
) -> PLL_CTRL_1_VCODIV_CLK_TEST_EN_W

Bit 10 - Debug: enable to output on GPIO the VCO signal divided by the programmable divider

pub fn pll_ctrl_1_en_low_chp_bias(&mut self) -> PLL_CTRL_1_EN_LOW_CHP_BIAS_W

Bit 9 - When high, allow to decrease half time the bias current for the same output pumping current. Should be always high in IcyTRX.

pub fn pll_ctrl_1_chp_dead_zone_en(&mut self) -> PLL_CTRL_1_CHP_DEAD_ZONE_EN_W

Bit 8 - Debug: enable charge-pump dead zone (degraded PLL characteristics for test)

pub fn pll_ctrl_1_chp_curr_offset_trim(
    &mut self
) -> PLL_CTRL_1_CHP_CURR_OFFSET_TRIM_W

Bits 6:7 - Debug: charge-pump offset current values selection bits (see bit 6 to enable this mode): 00 => d_phi = 15, 01 => d_phi=22.5, 10 => d_phi = 30, 11 => d_phi = 60. Also sets the bias current of the common mode control block of the charge-pump. Must be sets to 01 to ensure a proper operation of the VCO tuning voltage comparator for sub-band selection, if used

pub fn pll_ctrl_1_high_bw_filter_en(&mut self) -> PLL_CTRL_1_HIGH_BW_FILTER_EN_W

Bit 5 - Enable the PLL filter high bandwidth needed in TX (must be high together with bit 4 in TX, low in RX)

pub fn pll_ctrl_1_fast_chp_en(&mut self) -> PLL_CTRL_1_FAST_CHP_EN_W

Bit 4 - Enable the high current output of the charge-pump for PLL TX high bandwidth mode (must be high together with bit 5 in TX, low in RX)

pub fn pll_ctrl_1_chp_mode_trim(&mut self) -> PLL_CTRL_1_CHP_MODE_TRIM_W

Bits 2:3 - Charge-pump active if 00 else this allow to open the PLL and force the VCO tune voltage to reach: 01 => minimum frequency inside sub-band selection, 10 => medium frequency inside sub-band selection, 11 => maximum frequency inside sub-band selection.

pub fn pll_ctrl_1_chp_cmc_en(&mut self) -> PLL_CTRL_1_CHP_CMC_EN_W

Bit 1 - Enable the common mode control block of the charge-pump. Must be high to ensure proper operation of the VCO tuning voltage comparator for sub-band selection, if used

pub fn pll_ctrl_1_chp_curr_offset_en(
    &mut self
) -> PLL_CTRL_1_CHP_CURR_OFFSET_EN_W

Bit 0 - Debug: enable the charge-pump offset current (see bits 7:6 for offset current value)

impl W<u32, Reg<u32, _RF_REG2A>>

pub fn enables_separate_ppa_casc(&mut self) -> ENABLES_SEPARATE_PPA_CASC_W

Bit 28 - If set to 1, the en PPA cascode bit is independent from the en PA

pub fn enables_en_rxtx(&mut self) -> ENABLES_EN_RXTX_W

Bits 22:27 - Enable signals: 0 => LNA, 1 => LNA, 2 => IFA, 3 => Tx, 4 => PA, 5 => PPA casc

pub fn enables_en_bb(&mut self) -> ENABLES_EN_BB_W

Bits 16:21 - Enable signals for the BB: 0 => Filter, 1 => Filter central frequency bias, 2 => Filter bandwidth bias, 3 => ADC, 4 => RSSI, 5 => peak detector

pub fn rssi_tun_rssi_tun_gain(&mut self) -> RSSI_TUN_RSSI_TUN_GAIN_W

Bits 13:15 - RSSI tuning for gain

pub fn rssi_tun_rssi_odd_offset(&mut self) -> RSSI_TUN_RSSI_ODD_OFFSET_W

Bits 8:12 - RSSI tuning for odd stages: offset to the even triangular wave

pub fn rssi_tun_rssi_even_max(&mut self) -> RSSI_TUN_RSSI_EVEN_MAX_W

Bits 4:7 - RSSI tuning for even stages: maximum value of the triangular wave. If max = min, static signal.

pub fn rssi_tun_rssi_even_min(&mut self) -> RSSI_TUN_RSSI_EVEN_MIN_W

Bits 0:3 - RSSI tuning for even stages: minimum value of the triangular wave

impl W<u32, Reg<u32, _RF_XTAL_CTRL>>

pub fn xtal_ctrl_xo_thr_high(&mut self) -> XTAL_CTRL_XO_THR_HIGH_W

Bits 28:31 - High threshold for xtal trimming

pub fn xtal_ctrl_xo_thr_low(&mut self) -> XTAL_CTRL_XO_THR_LOW_W

Bits 24:27 - Low threshold for xtal trimming

pub fn xtal_ctrl_xo_a_s_curr_sel_high(
    &mut self
) -> XTAL_CTRL_XO_A_S_CURR_SEL_HIGH_W

Bits 22:23 - Value of after_startup_curr_sel when level is higher than xo_thr_high

pub fn xtal_ctrl_xo_a_s_curr_sel_low(
    &mut self
) -> XTAL_CTRL_XO_A_S_CURR_SEL_LOW_W

Bits 20:21 - Value of after_startup_curr_sel when level is lower than xo_thr_low

pub fn xtal_ctrl_xtal_ctrl_bypass(&mut self) -> XTAL_CTRL_XTAL_CTRL_BYPASS_W

Bit 18 - Bypass the Xtal control algorithm

pub fn xtal_ctrl_dig_clk_in_sel(&mut self) -> XTAL_CTRL_DIG_CLK_IN_SEL_W

Bit 17 - If set to 1 selects the clk_in_dig signal for the digital block, otherwise the internal xtal

pub fn xtal_ctrl_xo_en_b_reg(&mut self) -> XTAL_CTRL_XO_EN_B_REG_W

Bit 16 - Xtal oscillator enable (active low)

pub fn xtal_ctrl_xtal_ckdiv(&mut self) -> XTAL_CTRL_XTAL_CKDIV_W

Bits 14:15 - Xtal trimming speed: 00 => 43us, 01 => 85us, 10 => 171us, 11 => 341us

pub fn xtal_ctrl_clk_out_en_b(&mut self) -> XTAL_CTRL_CLK_OUT_EN_B_W

Bit 13 - When high, disable the output clock to go to main IP (clk_out output stay low).

pub fn xtal_ctrl_reg_value_sel(&mut self) -> XTAL_CTRL_REG_VALUE_SEL_W

Bit 12 - When low, all main ctrl signals are used instead of corresponding ctrl signal or some control bits of xtal_reg. They are: xo_en_b, ext_clk_mode and lp_mode. When high, corresponding ctrl signal and some control bits of xtal_reg are used instead of main ctrl signals. They are: xo_en_b_reg, ext_clk_mode (bit 0) and lp_mode (bit 1).

pub fn xtal_ctrl_afterstartup_curr_sel(
    &mut self
) -> XTAL_CTRL_AFTERSTARTUP_CURR_SEL_W

Bits 10:11 - Selection of the current before amplitude stabilization but after starting-up in active transistors of the core oscillator: '00': typ. 0.15 mA, '01': typ. 0.24 mA, '10': typ. 0.40 mA, '11': typ. 0.61 mA

pub fn xtal_ctrl_startup_curr_sel(&mut self) -> XTAL_CTRL_STARTUP_CURR_SEL_W

Bits 8:9 - Selection of the starting-up current in active transistors of the core oscillator: '00': typ. 0.41 mA, '01': typ. 0.59 mA, '10': typ. 0.88 mA, '11': typ. 1.24 mA

pub fn xtal_ctrl_inv_clk_dig(&mut self) -> XTAL_CTRL_INV_CLK_DIG_W

Bit 7 - Invert clock on clk_dig output

pub fn xtal_ctrl_inv_clk_pll(&mut self) -> XTAL_CTRL_INV_CLK_PLL_W

Bit 6 - Invert clock on clk_pll output

pub fn xtal_ctrl_force_clk_ready(&mut self) -> XTAL_CTRL_FORCE_CLK_READY_W

Bit 5 - Debug: allow to force output clocks on clk_pll, clk_dig and clk_out (if these outputs are enabled) and bypass the xtal internal clock detector that gates these clock outputs.

pub fn xtal_ctrl_clk_dig_en_b(&mut self) -> XTAL_CTRL_CLK_DIG_EN_B_W

Bit 4 - When high, disable the output clock to go to digital (clk_dig output stay low).

pub fn xtal_ctrl_buff_en_b(&mut self) -> XTAL_CTRL_BUFF_EN_B_W

Bit 3 - When low (and if xtal_en_b(_reg) is low), the xtal buffer is enabled otherwise it is disabled. Could be used to decrease the power consumption of the xtal while maintaining oscillation in the xtal oscillator

pub fn xtal_ctrl_hp_mode(&mut self) -> XTAL_CTRL_HP_MODE_W

Bit 2 - When high, bias current in the clock buffer is increased compared to normal operation (high bandwidth mode in 132 MHz clock input buffer).

pub fn xtal_ctrl_lp_mode(&mut self) -> XTAL_CTRL_LP_MODE_W

Bit 1 - When high, bias current in the clock buffer is reduced compared to normal operation (low power mode). Usable only if bit 12 is high (see below) otherwise it is bypassed by lp_mode pin input on main interface

pub fn xtal_ctrl_ext_clk_mode(&mut self) -> XTAL_CTRL_EXT_CLK_MODE_W

Bit 0 - When high, allow to uses xtal_p (and eventually xtal_n) has external clock input(s). The XTAL oscillator core is disabled. Usable only if bit 12 is high (see below) otherwise it is bypassed by ext_clk_mode pin input on main interface

impl W<u32, Reg<u32, _RF_REG2C>>

pub fn subband_offset_sb_offset(&mut self) -> SUBBAND_OFFSET_SB_OFFSET_W

Bits 24:31 - Offset to add in frequency count in order to compensate the offset of the varicap.

pub fn swcap_lim_sb_max_val(&mut self) -> SWCAP_LIM_SB_MAX_VAL_W

Bits 20:23 - maximum subband value in linear search subband (freq and comp)

pub fn swcap_lim_sb_min_val(&mut self) -> SWCAP_LIM_SB_MIN_VAL_W

Bits 16:19 - minimum subband value in linear search subband (freq and comp)

pub fn subband_conf_sb_fll_mode(&mut self) -> SUBBAND_CONF_SB_FLL_MODE_W

Bit 15 - Enables the FLL mode for the subband selection (overrides other settings)

pub fn subband_conf_sb_inv_band(&mut self) -> SUBBAND_CONF_SB_INV_BAND_W

Bit 14 - invert the meaning of sb_high and sb_low

pub fn subband_conf_sb_freq_cnt(&mut self) -> SUBBAND_CONF_SB_FREQ_CNT_W

Bits 12:13 - The length to count in frequency mode: 00 => 256 (Rx: 10.7us, Tx: 2.13us),01 => 512 (Rx: 21.3us, Tx: 4.26us),11 => 1024 (Rx: 42.7us, Tx: 8.53us),01 => 4096 (Rx: 171us, Tx: 34.1us)

pub fn subband_conf_sb_wait_t(&mut self) -> SUBBAND_CONF_SB_WAIT_T_W

Bits 10:11 - time to wait to the PLL to settle: 00 => Rx 8us, Tx 2us, 01 => Rx 12us, Tx 3us, 10 => Rx 16us, Tx 4us, 11 => Rx 24us, Tx 6u

pub fn subband_conf_sb_mode(&mut self) -> SUBBAND_CONF_SB_MODE_W

Bits 8:9 - sub-band algorithm mode: 00 => SAR w/ comparators, 01 => linear w/ comparators, 00 => SAR w/ frequency ratios, 01 => linear w/ frequency ratios

pub fn pa_conf_sw_cn(&mut self) -> PA_CONF_SW_CN_W

Bits 4:5 - Harmonic 2 notch tuning

pub fn pa_conf_tx_switchpa(&mut self) -> PA_CONF_TX_SWITCHPA_W

Bit 3 - If set to 1, enables the PA only with the digital block, otherwise it's the RF Tx timing

pub fn pa_conf_tx_0dbm(&mut self) -> PA_CONF_TX_0DBM_W

Bit 2 - If set to 1 enables the PA, otherwise only the PPA is used (-20dBm)

pub fn pa_conf_ctrl_pa(&mut self) -> PA_CONF_CTRL_PA_W

Bits 0:1 - N.U.

impl W<u32, Reg<u32, _RF_REG2D>>

pub fn subband_corr_subband_corr_en(&mut self) -> SUBBAND_CORR_SUBBAND_CORR_EN_W

Bit 31 - Enable the subband correction

pub fn subband_corr_subband_corr_rx(&mut self) -> SUBBAND_CORR_SUBBAND_CORR_RX_W

Bits 28:30 - Subband correction in Rx

pub fn subband_corr_subband_corr_tx(&mut self) -> SUBBAND_CORR_SUBBAND_CORR_TX_W

Bits 24:26 - Subband correction in Tx

pub fn pll_conf_tx_nrx_inv_clk_pll_tx(
    &mut self
) -> PLL_CONF_TX_NRX_INV_CLK_PLL_TX_W

Bit 23

pub fn pll_conf_tx_nrx_inv_clk_dig_tx(
    &mut self
) -> PLL_CONF_TX_NRX_INV_CLK_DIG_TX_W

Bit 22

pub fn pll_conf_tx_nrx_ck_sel_tx(&mut self) -> PLL_CONF_TX_NRX_CK_SEL_TX_W

Bits 20:21 - Xor value between Tx and Rx for the ck_sel field of register DLL_CTRL

pub fn pll_conf_tx_nrx_chp_curr_off_trim_tx(
    &mut self
) -> PLL_CONF_TX_NRX_CHP_CURR_OFF_TRIM_TX_W

Bits 17:18

pub fn pll_conf_tx_nrx_chp_curr_off_en_tx(
    &mut self
) -> PLL_CONF_TX_NRX_CHP_CURR_OFF_EN_TX_W

Bit 16

pub fn pa_rampup_full_pa_rampup(&mut self) -> PA_RAMPUP_FULL_PA_RAMPUP_W

Bit 15 - If set to 1, the PA rampup uses the PA backoff enable bit (from -40 dBm)

pub fn pa_rampup_del_pa_rampup(&mut self) -> PA_RAMPUP_DEL_PA_RAMPUP_W

Bits 12:14 - time to wait to start the ramp-up after the PA enable is detected

pub fn pa_rampup_tau_pa_rampup(&mut self) -> PA_RAMPUP_TAU_PA_RAMPUP_W

Bits 10:11 - time constant of the Ramp-up/Ramp-down

pub fn pa_rampup_en_pa_rampdown(&mut self) -> PA_RAMPUP_EN_PA_RAMPDOWN_W

Bit 9 - if set to 1 enables the PA ramp-down. Only valid in case of ramp-up

pub fn pa_rampup_en_pa_rampup(&mut self) -> PA_RAMPUP_EN_PA_RAMPUP_W

Bit 8 - if set to 1 enables the PA ramp-up

pub fn misc_spares(&mut self) -> MISC_SPARES_W

Bits 3:7 - Unused bits

pub fn misc_rssi_pre_att(&mut self) -> MISC_RSSI_PRE_ATT_W

Bits 1:2 - RSSI pre-attenuator: 00 => 0dB, 01 => 4dB, 10 => 8dB, 11 => 12dB

pub fn misc_xtal_low_clk_ready_th_en(
    &mut self
) -> MISC_XTAL_LOW_CLK_READY_TH_EN_W

Bit 0 - XTAL: if set to 1, the clk_ready threshold is set to a lower value

impl W<u32, Reg<u32, _RF_REG2E>>

pub fn rssi_detect_abs_thr_rssi_det_abs_thr(
    &mut self
) -> RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR_W

Bits 24:31 - Threshold used for absolute RSSI detection

pub fn rssi_detect_diff_thr_rssi_det_diff_thr(
    &mut self
) -> RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR_W

Bits 16:23 - Threshold used for differential RSSI detection

pub fn demod_ctrl_en_delline_sync_det(
    &mut self
) -> DEMOD_CTRL_EN_DELLINE_SYNC_DET_W

Bit 14 - If set to 1 enable the sync word detection in the delay line. This implies that nc_sel_out = 0x7

pub fn demod_ctrl_rssi_det_filt(&mut self) -> DEMOD_CTRL_RSSI_DET_FILT_W

Bit 13 - Add an additional filtering on the RSSI value

pub fn demod_ctrl_en_fast_clk_recov(&mut self) -> DEMOD_CTRL_EN_FAST_CLK_RECOV_W

Bit 12 - If set to 1 speed up the clock recovery during the resto of the preamble

pub fn demod_ctrl_en_min_max_mf(&mut self) -> DEMOD_CTRL_EN_MIN_MAX_MF_W

Bit 11 - If set to 1 enables the min max algo after the matched filter

pub fn demod_ctrl_en_pre_sync(&mut self) -> DEMOD_CTRL_EN_PRE_SYNC_W

Bit 10 - If set to 1 enables the sync detection on the non-delayed path; not working in 4FSK

pub fn demod_ctrl_block_rssi_det(&mut self) -> DEMOD_CTRL_BLOCK_RSSI_DET_W

Bit 9 - If set to 1 blocks the rssi detection during the slow-down period

pub fn demod_ctrl_early_fine_recov(&mut self) -> DEMOD_CTRL_EARLY_FINE_RECOV_W

Bit 8 - If set to 1 enables the early fine recovery after the packet detection or pre-sync

pub fn rssi_detect_rssi_det_cr_len(&mut self) -> RSSI_DETECT_RSSI_DET_CR_LEN_W

Bits 6:7 - Number of samples to estimate the carrier offset: 0 -> 32, 1 -> 64, 2 -> 128, 3->256

pub fn rssi_detect_rssi_det_wait(&mut self) -> RSSI_DETECT_RSSI_DET_WAIT_W

Bits 4:5 - Symbols to wait after the RSSI detection: 00 -> 0, 01 -> 1, 10 -> 2, 11 -> 4

pub fn rssi_detect_rssi_det_diff_ll(&mut self) -> RSSI_DETECT_RSSI_DET_DIFF_LL_W

Bits 2:3 - Set the distance between the actual value and the subtracted one (0->1 sample,1->2 samples,etc)

pub fn rssi_detect_rssi_det_en_abs(&mut self) -> RSSI_DETECT_RSSI_DET_EN_ABS_W

Bit 1 - If set to 1 enables the absolute RSSI detection

pub fn rssi_detect_rssi_det_en_diff(&mut self) -> RSSI_DETECT_RSSI_DET_EN_DIFF_W

Bit 0 - If set to 1 enables the differential RSSI detection

impl W<u32, Reg<u32, _RF_REG2F>>

pub fn ck_div_1_6_ck_div_1_6(&mut self) -> CK_DIV_1_6_CK_DIV_1_6_W

Bits 24:26 - Clock division factor for ck_div_1_6

pub fn pads_pe_ds_gpio_ds(&mut self) -> PADS_PE_DS_GPIO_DS_W

Bit 22 - If set to 1 enables the increased drive strength of the digital pads

pub fn pads_pe_ds_gpio_pe(&mut self) -> PADS_PE_DS_GPIO_PE_W

Bit 21 - If set to 1 enables the pull-up of the GPIO pads

pub fn pads_pe_ds_nreset_pe(&mut self) -> PADS_PE_DS_NRESET_PE_W

Bit 20 - If set to 1 enables the pull-up of the nreset pad

pub fn pads_pe_ds_spi_miso_pe(&mut self) -> PADS_PE_DS_SPI_MISO_PE_W

Bit 19 - If set to 1 enables the pull-up of the MISO SPI pad

pub fn pads_pe_ds_spi_mosi_pe(&mut self) -> PADS_PE_DS_SPI_MOSI_PE_W

Bit 18 - If set to 1 enables the pull-up of the MOSI SPI pad

pub fn pads_pe_ds_spi_sclk_pe(&mut self) -> PADS_PE_DS_SPI_SCLK_PE_W

Bit 17 - If set to 1 enables the pull-up of the SCLK SPI pad

pub fn pads_pe_ds_spi_cs_n_pe(&mut self) -> PADS_PE_DS_SPI_CS_N_PE_W

Bit 16 - If set to 1 enables the pull-up of the CSN SPI pad

pub fn subband_fll_sb_fll_dither(&mut self) -> SUBBAND_FLL_SB_FLL_DITHER_W

Bits 14:15 - Select the dithering: 00 no dithering, 01 PN9 positive, 10 PN10 negative, PN9+PN10

pub fn subband_fll_sb_fll_cic_tau(&mut self) -> SUBBAND_FLL_SB_FLL_CIC_TAU_W

Bits 12:13 - Set the CIC decimator factor: 00 => 16, 01 => 32, 10 => 64, 11 => 128

pub fn subband_fll_sb_fll_ph_4_n8(&mut self) -> SUBBAND_FLL_SB_FLL_PH_4_N8_W

Bit 11 - If set to 1, it uses only 4 phases in the frequency detector. Default 8 phases

pub fn subband_fll_sb_fll_wait(&mut self) -> SUBBAND_FLL_SB_FLL_WAIT_W

Bits 8:10 - Set the number of CIC samples before stopping the FLL

pub fn sync_word_corr_en_sync_word_corr(
    &mut self
) -> SYNC_WORD_CORR_EN_SYNC_WORD_CORR_W

Bit 7 - If set to 1 enable the sync word bias correction with RSSI detection

pub fn sync_word_corr_sync_word_bias(
    &mut self
) -> SYNC_WORD_CORR_SYNC_WORD_BIAS_W

Bits 0:5 - set the sync word bias. Without the phADC rescaler, it's 8*mod_idx.

impl W<u32, Reg<u32, _RF_REG30>>

pub fn rxfifo_status_bist(&mut self) -> RXFIFO_STATUS_BIST_W

Bits 25:31 - Start the bist test on the Rx FIFO (code 0x5d)

pub fn rxfifo_status_flush(&mut self) -> RXFIFO_STATUS_FLUSH_W

Bit 24 - If set to 1 the Rx FIFO is flushed

pub fn txfifo_status_bist(&mut self) -> TXFIFO_STATUS_BIST_W

Bits 17:23 - Start the bist test on the Tx FIFO (code 0x5d)

pub fn txfifo_status_flush(&mut self) -> TXFIFO_STATUS_FLUSH_W

Bit 16 - If set to 1 the Tx FIFO is flushed

pub fn fsm_mode_reset(&mut self) -> FSM_MODE_RESET_W

Bit 3 - If set to 1, the FSM is reset. If mode is set to 0 the FSM is reset abrubtly. If is set to 1 the Tx or Rx (depending on tx_nrx) is stopped gently via the serializer or the deserializer

pub fn fsm_mode_tx_nrx(&mut self) -> FSM_MODE_TX_NRX_W

Bit 2 - Sets the Radio in Tx (1) or Rx (0) mode

pub fn fsm_mode_mode(&mut self) -> FSM_MODE_MODE_W

Bits 0:1 - Sets the FSM mode: 00: nothing is done, 01: activate, 10: calibrate the PLL, 11: calibrate the PLL then Tx/Rx

impl W<u32, Reg<u32, _RF_TXFIFO>>

pub fn txfifo_tx_data(&mut self) -> TXFIFO_TX_DATA_W

Bits 0:7 - Data to be sent

impl W<u32, Reg<u32, _SYSTICK_CTRL>>

pub fn clksource(&mut self) -> CLKSOURCE_W

Bit 2 - SYSTICK timer clock source

pub fn tickint(&mut self) -> TICKINT_W

Bit 1 - SYSTICK timer interrupt enable

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - SYSTICK timer enable

impl W<u32, Reg<u32, _SYSTICK_LOAD>>

pub fn reload(&mut self) -> RELOAD_W

Bits 0:23 - Counter reload value for the SYSTICK timer when it reaches 0

impl W<u32, Reg<u32, _SYSTICK_VAL>>

pub fn current(&mut self) -> CURRENT_W

Bits 0:23 - Current value of the SYSTICK counter value. Write to clear counter.

impl W<u32, Reg<u32, _DEBUG_DHCSR>>

pub fn dbgkey(&mut self) -> DBGKEY_W

Bits 16:31 - Debug key must be written to this field in order to write the rest of the register

pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W

Bit 5 - Set to break a stalled memory access

pub fn c_maskints(&mut self) -> C_MASKINTS_W

Bit 3 - Mask interrupts while stepping

pub fn c_step(&mut self) -> C_STEP_W

Bit 2 - Single step the processor

pub fn c_halt(&mut self) -> C_HALT_W

Bit 1 - Halt the processor

pub fn c_debugen(&mut self) -> C_DEBUGEN_W

Bit 0 - Enable halt mode debugging

impl W<u32, Reg<u32, _DEBUG_DCRSR>>

pub fn regwn_r(&mut self) -> REGWNR_W

Bit 16 - Indicates direction of register transfer

pub fn regsel(&mut self) -> REGSEL_W

Bits 0:4 - Indicates register to be accessed

impl W<u32, Reg<u32, _DEBUG_DCRDR>>

pub fn debug_regdata(&mut self) -> DEBUG_REGDATA_W

Bits 0:31 - Register read/write data for debugging

impl W<u32, Reg<u32, _DEBUG_DEMCR>>

pub fn trcena(&mut self) -> TRCENA_W

Bit 24 - Trace system enable

pub fn mon_req(&mut self) -> MON_REQ_W

Bit 19 - Indicates that the debug monitor is caused by a manual pending request rather than a hardware event

pub fn mon_step(&mut self) -> MON_STEP_W

Bit 18 - Single step the processor

pub fn mon_pend(&mut self) -> MON_PEND_W

Bit 17 - Pend the monitor exception request

pub fn mon_en(&mut self) -> MON_EN_W

Bit 16 - Enable the debug monitor exception

pub fn vc_harderr(&mut self) -> VC_HARDERR_W

Bit 10 - Debug trap on hard faults

pub fn vc_interr(&mut self) -> VC_INTERR_W

Bit 9 - Debug trap on interrupt service errors

pub fn vc_buserr(&mut self) -> VC_BUSERR_W

Bit 8 - Debug trap on bus faults

pub fn vc_staterr(&mut self) -> VC_STATERR_W

Bit 7 - Debug trap on usage fault state errors

pub fn vc_chkerr(&mut self) -> VC_CHKERR_W

Bit 6 - Debug trap on fault-enabled checking errors (e.g. unaligned access, divide by zero, etc.)

pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W

Bit 5 - Debug trap on usage fault no coprocessor errors

pub fn vc_mmerr(&mut self) -> VC_MMERR_W

Bit 4 - Debug trap on memory management fault

pub fn vc_corereset(&mut self) -> VC_CORERESET_W

Bit 0 - Debug trap on core reset