1#[repr(C)]
4pub struct __BindgenUnionField<T>(::core::marker::PhantomData<T>);
5impl<T> __BindgenUnionField<T> {
6 #[inline]
7 pub const fn new() -> Self {
8 __BindgenUnionField(::core::marker::PhantomData)
9 }
10 #[inline]
11 pub unsafe fn as_ref(&self) -> &T {
12 ::core::mem::transmute(self)
13 }
14 #[inline]
15 pub unsafe fn as_mut(&mut self) -> &mut T {
16 ::core::mem::transmute(self)
17 }
18}
19impl<T> ::core::default::Default for __BindgenUnionField<T> {
20 #[inline]
21 fn default() -> Self {
22 Self::new()
23 }
24}
25impl<T> ::core::clone::Clone for __BindgenUnionField<T> {
26 #[inline]
27 fn clone(&self) -> Self {
28 Self::new()
29 }
30}
31impl<T> ::core::marker::Copy for __BindgenUnionField<T> {}
32impl<T> ::core::fmt::Debug for __BindgenUnionField<T> {
33 fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
34 fmt.write_str("__BindgenUnionField")
35 }
36}
37impl<T> ::core::hash::Hash for __BindgenUnionField<T> {
38 fn hash<H: ::core::hash::Hasher>(&self, _state: &mut H) {}
39}
40impl<T> ::core::cmp::PartialEq for __BindgenUnionField<T> {
41 fn eq(&self, _other: &__BindgenUnionField<T>) -> bool {
42 true
43 }
44}
45impl<T> ::core::cmp::Eq for __BindgenUnionField<T> {}
46pub const PICO_DEFAULT_UART: u32 = 0;
47pub const PICO_DEFAULT_UART_TX_PIN: u32 = 0;
48pub const PICO_DEFAULT_UART_RX_PIN: u32 = 1;
49pub const PICO_DEFAULT_LED_PIN: u32 = 25;
50pub const PICO_FLASH_SPI_CLKDIV: u32 = 2;
51pub const PICO_FLASH_SIZE_BYTES: u32 = 2097152;
52pub const PICO_SMPS_MODE_PIN: u32 = 23;
53pub const PICO_FLOAT_SUPPORT_ROM_V1: u32 = 1;
54pub const PICO_DOUBLE_SUPPORT_ROM_V1: u32 = 1;
55pub const __WORDSIZE: u32 = 64;
56pub const __DARWIN_ONLY_64_BIT_INO_T: u32 = 0;
57pub const __DARWIN_ONLY_UNIX_CONFORMANCE: u32 = 1;
58pub const __DARWIN_ONLY_VERS_1050: u32 = 0;
59pub const __DARWIN_UNIX03: u32 = 1;
60pub const __DARWIN_64_BIT_INO_T: u32 = 1;
61pub const __DARWIN_VERS_1050: u32 = 1;
62pub const __DARWIN_NON_CANCELABLE: u32 = 0;
63pub const __DARWIN_SUF_64_BIT_INO_T: &'static [u8; 9usize] = b"$INODE64\0";
64pub const __DARWIN_SUF_1050: &'static [u8; 6usize] = b"$1050\0";
65pub const __DARWIN_SUF_EXTSN: &'static [u8; 14usize] = b"$DARWIN_EXTSN\0";
66pub const __DARWIN_C_ANSI: u32 = 4096;
67pub const __DARWIN_C_FULL: u32 = 900000;
68pub const __DARWIN_C_LEVEL: u32 = 900000;
69pub const __STDC_WANT_LIB_EXT1__: u32 = 1;
70pub const __DARWIN_NO_LONG_LONG: u32 = 0;
71pub const _DARWIN_FEATURE_64_BIT_INODE: u32 = 1;
72pub const _DARWIN_FEATURE_ONLY_UNIX_CONFORMANCE: u32 = 1;
73pub const _DARWIN_FEATURE_UNIX_CONFORMANCE: u32 = 3;
74pub const __PTHREAD_SIZE__: u32 = 8176;
75pub const __PTHREAD_ATTR_SIZE__: u32 = 56;
76pub const __PTHREAD_MUTEXATTR_SIZE__: u32 = 8;
77pub const __PTHREAD_MUTEX_SIZE__: u32 = 56;
78pub const __PTHREAD_CONDATTR_SIZE__: u32 = 8;
79pub const __PTHREAD_COND_SIZE__: u32 = 40;
80pub const __PTHREAD_ONCE_SIZE__: u32 = 8;
81pub const __PTHREAD_RWLOCK_SIZE__: u32 = 192;
82pub const __PTHREAD_RWLOCKATTR_SIZE__: u32 = 16;
83pub const INT8_MAX: u32 = 127;
84pub const INT16_MAX: u32 = 32767;
85pub const INT32_MAX: u32 = 2147483647;
86pub const INT64_MAX: u64 = 9223372036854775807;
87pub const INT8_MIN: i32 = -128;
88pub const INT16_MIN: i32 = -32768;
89pub const INT32_MIN: i32 = -2147483648;
90pub const INT64_MIN: i64 = -9223372036854775808;
91pub const UINT8_MAX: u32 = 255;
92pub const UINT16_MAX: u32 = 65535;
93pub const UINT32_MAX: u32 = 4294967295;
94pub const UINT64_MAX: i32 = -1;
95pub const INT_LEAST8_MIN: i32 = -128;
96pub const INT_LEAST16_MIN: i32 = -32768;
97pub const INT_LEAST32_MIN: i32 = -2147483648;
98pub const INT_LEAST64_MIN: i64 = -9223372036854775808;
99pub const INT_LEAST8_MAX: u32 = 127;
100pub const INT_LEAST16_MAX: u32 = 32767;
101pub const INT_LEAST32_MAX: u32 = 2147483647;
102pub const INT_LEAST64_MAX: u64 = 9223372036854775807;
103pub const UINT_LEAST8_MAX: u32 = 255;
104pub const UINT_LEAST16_MAX: u32 = 65535;
105pub const UINT_LEAST32_MAX: u32 = 4294967295;
106pub const UINT_LEAST64_MAX: i32 = -1;
107pub const INT_FAST8_MIN: i32 = -128;
108pub const INT_FAST16_MIN: i32 = -32768;
109pub const INT_FAST32_MIN: i32 = -2147483648;
110pub const INT_FAST64_MIN: i64 = -9223372036854775808;
111pub const INT_FAST8_MAX: u32 = 127;
112pub const INT_FAST16_MAX: u32 = 32767;
113pub const INT_FAST32_MAX: u32 = 2147483647;
114pub const INT_FAST64_MAX: u64 = 9223372036854775807;
115pub const UINT_FAST8_MAX: u32 = 255;
116pub const UINT_FAST16_MAX: u32 = 65535;
117pub const UINT_FAST32_MAX: u32 = 4294967295;
118pub const UINT_FAST64_MAX: i32 = -1;
119pub const INTPTR_MAX: u64 = 9223372036854775807;
120pub const INTPTR_MIN: i64 = -9223372036854775808;
121pub const UINTPTR_MAX: i32 = -1;
122pub const SIZE_MAX: i32 = -1;
123pub const RSIZE_MAX: i32 = -1;
124pub const WINT_MIN: i32 = -2147483648;
125pub const WINT_MAX: u32 = 2147483647;
126pub const SIG_ATOMIC_MIN: i32 = -2147483648;
127pub const SIG_ATOMIC_MAX: u32 = 2147483647;
128pub const true_: u32 = 1;
129pub const false_: u32 = 0;
130pub const __bool_true_false_are_defined: u32 = 1;
131pub const PICO_SDK_VERSION_MAJOR: u32 = 1;
132pub const PICO_SDK_VERSION_MINOR: u32 = 0;
133pub const PICO_SDK_VERSION_REVISION: u32 = 0;
134pub const PICO_SDK_VERSION_STRING: &'static [u8; 6usize] = b"1.0.0\0";
135pub const REG_ALIAS_RW_BITS: u32 = 0;
136pub const REG_ALIAS_XOR_BITS: u32 = 4096;
137pub const REG_ALIAS_SET_BITS: u32 = 8192;
138pub const REG_ALIAS_CLR_BITS: u32 = 12288;
139pub const ROM_BASE: u32 = 0;
140pub const XIP_BASE: u32 = 268435456;
141pub const XIP_MAIN_BASE: u32 = 268435456;
142pub const XIP_NOALLOC_BASE: u32 = 285212672;
143pub const XIP_NOCACHE_BASE: u32 = 301989888;
144pub const XIP_NOCACHE_NOALLOC_BASE: u32 = 318767104;
145pub const XIP_CTRL_BASE: u32 = 335544320;
146pub const XIP_SRAM_BASE: u32 = 352321536;
147pub const XIP_SRAM_END: u32 = 352337920;
148pub const XIP_SSI_BASE: u32 = 402653184;
149pub const SRAM_BASE: u32 = 536870912;
150pub const SRAM_STRIPED_BASE: u32 = 536870912;
151pub const SRAM_STRIPED_END: u32 = 537133056;
152pub const SRAM4_BASE: u32 = 537133056;
153pub const SRAM5_BASE: u32 = 537137152;
154pub const SRAM_END: u32 = 537141248;
155pub const SRAM0_BASE: u32 = 553648128;
156pub const SRAM1_BASE: u32 = 553713664;
157pub const SRAM2_BASE: u32 = 553779200;
158pub const SRAM3_BASE: u32 = 553844736;
159pub const SYSINFO_BASE: u32 = 1073741824;
160pub const SYSCFG_BASE: u32 = 1073758208;
161pub const CLOCKS_BASE: u32 = 1073774592;
162pub const RESETS_BASE: u32 = 1073790976;
163pub const PSM_BASE: u32 = 1073807360;
164pub const IO_BANK0_BASE: u32 = 1073823744;
165pub const IO_QSPI_BASE: u32 = 1073840128;
166pub const PADS_BANK0_BASE: u32 = 1073856512;
167pub const PADS_QSPI_BASE: u32 = 1073872896;
168pub const XOSC_BASE: u32 = 1073889280;
169pub const PLL_SYS_BASE: u32 = 1073905664;
170pub const PLL_USB_BASE: u32 = 1073922048;
171pub const BUSCTRL_BASE: u32 = 1073938432;
172pub const UART0_BASE: u32 = 1073954816;
173pub const UART1_BASE: u32 = 1073971200;
174pub const SPI0_BASE: u32 = 1073987584;
175pub const SPI1_BASE: u32 = 1074003968;
176pub const I2C0_BASE: u32 = 1074020352;
177pub const I2C1_BASE: u32 = 1074036736;
178pub const ADC_BASE: u32 = 1074053120;
179pub const PWM_BASE: u32 = 1074069504;
180pub const TIMER_BASE: u32 = 1074085888;
181pub const WATCHDOG_BASE: u32 = 1074102272;
182pub const RTC_BASE: u32 = 1074118656;
183pub const ROSC_BASE: u32 = 1074135040;
184pub const VREG_AND_CHIP_RESET_BASE: u32 = 1074151424;
185pub const TBMAN_BASE: u32 = 1074184192;
186pub const DMA_BASE: u32 = 1342177280;
187pub const USBCTRL_DPRAM_BASE: u32 = 1343225856;
188pub const USBCTRL_BASE: u32 = 1343225856;
189pub const USBCTRL_REGS_BASE: u32 = 1343291392;
190pub const PIO0_BASE: u32 = 1344274432;
191pub const PIO1_BASE: u32 = 1345323008;
192pub const XIP_AUX_BASE: u32 = 1346371584;
193pub const SIO_BASE: u32 = 3489660928;
194pub const PPB_BASE: u32 = 3758096384;
195pub const NUM_CORES: u32 = 2;
196pub const NUM_DMA_CHANNELS: u32 = 12;
197pub const NUM_IRQS: u32 = 32;
198pub const NUM_PIOS: u32 = 2;
199pub const NUM_PIO_STATE_MACHINES: u32 = 4;
200pub const NUM_PWM_SLICES: u32 = 8;
201pub const NUM_SPIN_LOCKS: u32 = 32;
202pub const NUM_UARTS: u32 = 2;
203pub const NUM_BANK0_GPIOS: u32 = 30;
204pub const PIO_INSTRUCTION_COUNT: u32 = 32;
205pub const XOSC_MHZ: u32 = 12;
206pub const PICO_STACK_SIZE: u32 = 2048;
207pub const PICO_HEAP_SIZE: u32 = 2048;
208pub const PICO_NO_RAM_VECTOR_TABLE: u32 = 0;
209pub const PARAM_ASSERTIONS_ENABLE_ALL: u32 = 0;
210pub const PARAM_ASSERTIONS_DISABLE_ALL: u32 = 0;
211pub const PICO_STDOUT_MUTEX: u32 = 1;
212pub const PICO_STDIO_ENABLE_CRLF_SUPPORT: u32 = 1;
213pub const PICO_STDIO_DEFAULT_CRLF: u32 = 1;
214pub const PICO_STDIO_STACK_BUFFER_SIZE: u32 = 128;
215pub const TIMER_TIMEHW_OFFSET: u32 = 0;
216pub const TIMER_TIMEHW_BITS: u32 = 4294967295;
217pub const TIMER_TIMEHW_RESET: u32 = 0;
218pub const TIMER_TIMEHW_MSB: u32 = 31;
219pub const TIMER_TIMEHW_LSB: u32 = 0;
220pub const TIMER_TIMEHW_ACCESS: &'static [u8; 3usize] = b"WF\0";
221pub const TIMER_TIMELW_OFFSET: u32 = 4;
222pub const TIMER_TIMELW_BITS: u32 = 4294967295;
223pub const TIMER_TIMELW_RESET: u32 = 0;
224pub const TIMER_TIMELW_MSB: u32 = 31;
225pub const TIMER_TIMELW_LSB: u32 = 0;
226pub const TIMER_TIMELW_ACCESS: &'static [u8; 3usize] = b"WF\0";
227pub const TIMER_TIMEHR_OFFSET: u32 = 8;
228pub const TIMER_TIMEHR_BITS: u32 = 4294967295;
229pub const TIMER_TIMEHR_RESET: u32 = 0;
230pub const TIMER_TIMEHR_MSB: u32 = 31;
231pub const TIMER_TIMEHR_LSB: u32 = 0;
232pub const TIMER_TIMEHR_ACCESS: &'static [u8; 3usize] = b"RO\0";
233pub const TIMER_TIMELR_OFFSET: u32 = 12;
234pub const TIMER_TIMELR_BITS: u32 = 4294967295;
235pub const TIMER_TIMELR_RESET: u32 = 0;
236pub const TIMER_TIMELR_MSB: u32 = 31;
237pub const TIMER_TIMELR_LSB: u32 = 0;
238pub const TIMER_TIMELR_ACCESS: &'static [u8; 3usize] = b"RO\0";
239pub const TIMER_ALARM0_OFFSET: u32 = 16;
240pub const TIMER_ALARM0_BITS: u32 = 4294967295;
241pub const TIMER_ALARM0_RESET: u32 = 0;
242pub const TIMER_ALARM0_MSB: u32 = 31;
243pub const TIMER_ALARM0_LSB: u32 = 0;
244pub const TIMER_ALARM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
245pub const TIMER_ALARM1_OFFSET: u32 = 20;
246pub const TIMER_ALARM1_BITS: u32 = 4294967295;
247pub const TIMER_ALARM1_RESET: u32 = 0;
248pub const TIMER_ALARM1_MSB: u32 = 31;
249pub const TIMER_ALARM1_LSB: u32 = 0;
250pub const TIMER_ALARM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
251pub const TIMER_ALARM2_OFFSET: u32 = 24;
252pub const TIMER_ALARM2_BITS: u32 = 4294967295;
253pub const TIMER_ALARM2_RESET: u32 = 0;
254pub const TIMER_ALARM2_MSB: u32 = 31;
255pub const TIMER_ALARM2_LSB: u32 = 0;
256pub const TIMER_ALARM2_ACCESS: &'static [u8; 3usize] = b"RW\0";
257pub const TIMER_ALARM3_OFFSET: u32 = 28;
258pub const TIMER_ALARM3_BITS: u32 = 4294967295;
259pub const TIMER_ALARM3_RESET: u32 = 0;
260pub const TIMER_ALARM3_MSB: u32 = 31;
261pub const TIMER_ALARM3_LSB: u32 = 0;
262pub const TIMER_ALARM3_ACCESS: &'static [u8; 3usize] = b"RW\0";
263pub const TIMER_ARMED_OFFSET: u32 = 32;
264pub const TIMER_ARMED_BITS: u32 = 15;
265pub const TIMER_ARMED_RESET: u32 = 0;
266pub const TIMER_ARMED_MSB: u32 = 3;
267pub const TIMER_ARMED_LSB: u32 = 0;
268pub const TIMER_ARMED_ACCESS: &'static [u8; 3usize] = b"WC\0";
269pub const TIMER_TIMERAWH_OFFSET: u32 = 36;
270pub const TIMER_TIMERAWH_BITS: u32 = 4294967295;
271pub const TIMER_TIMERAWH_RESET: u32 = 0;
272pub const TIMER_TIMERAWH_MSB: u32 = 31;
273pub const TIMER_TIMERAWH_LSB: u32 = 0;
274pub const TIMER_TIMERAWH_ACCESS: &'static [u8; 3usize] = b"RO\0";
275pub const TIMER_TIMERAWL_OFFSET: u32 = 40;
276pub const TIMER_TIMERAWL_BITS: u32 = 4294967295;
277pub const TIMER_TIMERAWL_RESET: u32 = 0;
278pub const TIMER_TIMERAWL_MSB: u32 = 31;
279pub const TIMER_TIMERAWL_LSB: u32 = 0;
280pub const TIMER_TIMERAWL_ACCESS: &'static [u8; 3usize] = b"RO\0";
281pub const TIMER_DBGPAUSE_OFFSET: u32 = 44;
282pub const TIMER_DBGPAUSE_BITS: u32 = 6;
283pub const TIMER_DBGPAUSE_RESET: u32 = 7;
284pub const TIMER_DBGPAUSE_DBG1_RESET: u32 = 1;
285pub const TIMER_DBGPAUSE_DBG1_BITS: u32 = 4;
286pub const TIMER_DBGPAUSE_DBG1_MSB: u32 = 2;
287pub const TIMER_DBGPAUSE_DBG1_LSB: u32 = 2;
288pub const TIMER_DBGPAUSE_DBG1_ACCESS: &'static [u8; 3usize] = b"RW\0";
289pub const TIMER_DBGPAUSE_DBG0_RESET: u32 = 1;
290pub const TIMER_DBGPAUSE_DBG0_BITS: u32 = 2;
291pub const TIMER_DBGPAUSE_DBG0_MSB: u32 = 1;
292pub const TIMER_DBGPAUSE_DBG0_LSB: u32 = 1;
293pub const TIMER_DBGPAUSE_DBG0_ACCESS: &'static [u8; 3usize] = b"RW\0";
294pub const TIMER_PAUSE_OFFSET: u32 = 48;
295pub const TIMER_PAUSE_BITS: u32 = 1;
296pub const TIMER_PAUSE_RESET: u32 = 0;
297pub const TIMER_PAUSE_MSB: u32 = 0;
298pub const TIMER_PAUSE_LSB: u32 = 0;
299pub const TIMER_PAUSE_ACCESS: &'static [u8; 3usize] = b"RW\0";
300pub const TIMER_INTR_OFFSET: u32 = 52;
301pub const TIMER_INTR_BITS: u32 = 15;
302pub const TIMER_INTR_RESET: u32 = 0;
303pub const TIMER_INTR_ALARM_3_RESET: u32 = 0;
304pub const TIMER_INTR_ALARM_3_BITS: u32 = 8;
305pub const TIMER_INTR_ALARM_3_MSB: u32 = 3;
306pub const TIMER_INTR_ALARM_3_LSB: u32 = 3;
307pub const TIMER_INTR_ALARM_3_ACCESS: &'static [u8; 3usize] = b"WC\0";
308pub const TIMER_INTR_ALARM_2_RESET: u32 = 0;
309pub const TIMER_INTR_ALARM_2_BITS: u32 = 4;
310pub const TIMER_INTR_ALARM_2_MSB: u32 = 2;
311pub const TIMER_INTR_ALARM_2_LSB: u32 = 2;
312pub const TIMER_INTR_ALARM_2_ACCESS: &'static [u8; 3usize] = b"WC\0";
313pub const TIMER_INTR_ALARM_1_RESET: u32 = 0;
314pub const TIMER_INTR_ALARM_1_BITS: u32 = 2;
315pub const TIMER_INTR_ALARM_1_MSB: u32 = 1;
316pub const TIMER_INTR_ALARM_1_LSB: u32 = 1;
317pub const TIMER_INTR_ALARM_1_ACCESS: &'static [u8; 3usize] = b"WC\0";
318pub const TIMER_INTR_ALARM_0_RESET: u32 = 0;
319pub const TIMER_INTR_ALARM_0_BITS: u32 = 1;
320pub const TIMER_INTR_ALARM_0_MSB: u32 = 0;
321pub const TIMER_INTR_ALARM_0_LSB: u32 = 0;
322pub const TIMER_INTR_ALARM_0_ACCESS: &'static [u8; 3usize] = b"WC\0";
323pub const TIMER_INTE_OFFSET: u32 = 56;
324pub const TIMER_INTE_BITS: u32 = 15;
325pub const TIMER_INTE_RESET: u32 = 0;
326pub const TIMER_INTE_ALARM_3_RESET: u32 = 0;
327pub const TIMER_INTE_ALARM_3_BITS: u32 = 8;
328pub const TIMER_INTE_ALARM_3_MSB: u32 = 3;
329pub const TIMER_INTE_ALARM_3_LSB: u32 = 3;
330pub const TIMER_INTE_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RW\0";
331pub const TIMER_INTE_ALARM_2_RESET: u32 = 0;
332pub const TIMER_INTE_ALARM_2_BITS: u32 = 4;
333pub const TIMER_INTE_ALARM_2_MSB: u32 = 2;
334pub const TIMER_INTE_ALARM_2_LSB: u32 = 2;
335pub const TIMER_INTE_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RW\0";
336pub const TIMER_INTE_ALARM_1_RESET: u32 = 0;
337pub const TIMER_INTE_ALARM_1_BITS: u32 = 2;
338pub const TIMER_INTE_ALARM_1_MSB: u32 = 1;
339pub const TIMER_INTE_ALARM_1_LSB: u32 = 1;
340pub const TIMER_INTE_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RW\0";
341pub const TIMER_INTE_ALARM_0_RESET: u32 = 0;
342pub const TIMER_INTE_ALARM_0_BITS: u32 = 1;
343pub const TIMER_INTE_ALARM_0_MSB: u32 = 0;
344pub const TIMER_INTE_ALARM_0_LSB: u32 = 0;
345pub const TIMER_INTE_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RW\0";
346pub const TIMER_INTF_OFFSET: u32 = 60;
347pub const TIMER_INTF_BITS: u32 = 15;
348pub const TIMER_INTF_RESET: u32 = 0;
349pub const TIMER_INTF_ALARM_3_RESET: u32 = 0;
350pub const TIMER_INTF_ALARM_3_BITS: u32 = 8;
351pub const TIMER_INTF_ALARM_3_MSB: u32 = 3;
352pub const TIMER_INTF_ALARM_3_LSB: u32 = 3;
353pub const TIMER_INTF_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RW\0";
354pub const TIMER_INTF_ALARM_2_RESET: u32 = 0;
355pub const TIMER_INTF_ALARM_2_BITS: u32 = 4;
356pub const TIMER_INTF_ALARM_2_MSB: u32 = 2;
357pub const TIMER_INTF_ALARM_2_LSB: u32 = 2;
358pub const TIMER_INTF_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RW\0";
359pub const TIMER_INTF_ALARM_1_RESET: u32 = 0;
360pub const TIMER_INTF_ALARM_1_BITS: u32 = 2;
361pub const TIMER_INTF_ALARM_1_MSB: u32 = 1;
362pub const TIMER_INTF_ALARM_1_LSB: u32 = 1;
363pub const TIMER_INTF_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RW\0";
364pub const TIMER_INTF_ALARM_0_RESET: u32 = 0;
365pub const TIMER_INTF_ALARM_0_BITS: u32 = 1;
366pub const TIMER_INTF_ALARM_0_MSB: u32 = 0;
367pub const TIMER_INTF_ALARM_0_LSB: u32 = 0;
368pub const TIMER_INTF_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RW\0";
369pub const TIMER_INTS_OFFSET: u32 = 64;
370pub const TIMER_INTS_BITS: u32 = 15;
371pub const TIMER_INTS_RESET: u32 = 0;
372pub const TIMER_INTS_ALARM_3_RESET: u32 = 0;
373pub const TIMER_INTS_ALARM_3_BITS: u32 = 8;
374pub const TIMER_INTS_ALARM_3_MSB: u32 = 3;
375pub const TIMER_INTS_ALARM_3_LSB: u32 = 3;
376pub const TIMER_INTS_ALARM_3_ACCESS: &'static [u8; 3usize] = b"RO\0";
377pub const TIMER_INTS_ALARM_2_RESET: u32 = 0;
378pub const TIMER_INTS_ALARM_2_BITS: u32 = 4;
379pub const TIMER_INTS_ALARM_2_MSB: u32 = 2;
380pub const TIMER_INTS_ALARM_2_LSB: u32 = 2;
381pub const TIMER_INTS_ALARM_2_ACCESS: &'static [u8; 3usize] = b"RO\0";
382pub const TIMER_INTS_ALARM_1_RESET: u32 = 0;
383pub const TIMER_INTS_ALARM_1_BITS: u32 = 2;
384pub const TIMER_INTS_ALARM_1_MSB: u32 = 1;
385pub const TIMER_INTS_ALARM_1_LSB: u32 = 1;
386pub const TIMER_INTS_ALARM_1_ACCESS: &'static [u8; 3usize] = b"RO\0";
387pub const TIMER_INTS_ALARM_0_RESET: u32 = 0;
388pub const TIMER_INTS_ALARM_0_BITS: u32 = 1;
389pub const TIMER_INTS_ALARM_0_MSB: u32 = 0;
390pub const TIMER_INTS_ALARM_0_LSB: u32 = 0;
391pub const TIMER_INTS_ALARM_0_ACCESS: &'static [u8; 3usize] = b"RO\0";
392pub const NUM_TIMERS: u32 = 4;
393pub const PARAM_ASSERTIONS_ENABLED_TIMER: u32 = 0;
394pub const PARAM_ASSERTIONS_ENABLED_TIME: u32 = 0;
395pub const PICO_TIME_SLEEP_OVERHEAD_ADJUST_US: u32 = 6;
396pub const PICO_TIME_DEFAULT_ALARM_POOL_DISABLED: u32 = 0;
397pub const PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM: u32 = 3;
398pub const PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS: u32 = 16;
399pub const SIO_CPUID_OFFSET: u32 = 0;
400pub const SIO_CPUID_BITS: u32 = 4294967295;
401pub const SIO_CPUID_RESET: &'static [u8; 2usize] = b"-\0";
402pub const SIO_CPUID_MSB: u32 = 31;
403pub const SIO_CPUID_LSB: u32 = 0;
404pub const SIO_CPUID_ACCESS: &'static [u8; 3usize] = b"RO\0";
405pub const SIO_GPIO_IN_OFFSET: u32 = 4;
406pub const SIO_GPIO_IN_BITS: u32 = 1073741823;
407pub const SIO_GPIO_IN_RESET: u32 = 0;
408pub const SIO_GPIO_IN_MSB: u32 = 29;
409pub const SIO_GPIO_IN_LSB: u32 = 0;
410pub const SIO_GPIO_IN_ACCESS: &'static [u8; 3usize] = b"RO\0";
411pub const SIO_GPIO_HI_IN_OFFSET: u32 = 8;
412pub const SIO_GPIO_HI_IN_BITS: u32 = 63;
413pub const SIO_GPIO_HI_IN_RESET: u32 = 0;
414pub const SIO_GPIO_HI_IN_MSB: u32 = 5;
415pub const SIO_GPIO_HI_IN_LSB: u32 = 0;
416pub const SIO_GPIO_HI_IN_ACCESS: &'static [u8; 3usize] = b"RO\0";
417pub const SIO_GPIO_OUT_OFFSET: u32 = 16;
418pub const SIO_GPIO_OUT_BITS: u32 = 1073741823;
419pub const SIO_GPIO_OUT_RESET: u32 = 0;
420pub const SIO_GPIO_OUT_MSB: u32 = 29;
421pub const SIO_GPIO_OUT_LSB: u32 = 0;
422pub const SIO_GPIO_OUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
423pub const SIO_GPIO_OUT_SET_OFFSET: u32 = 20;
424pub const SIO_GPIO_OUT_SET_BITS: u32 = 1073741823;
425pub const SIO_GPIO_OUT_SET_RESET: u32 = 0;
426pub const SIO_GPIO_OUT_SET_MSB: u32 = 29;
427pub const SIO_GPIO_OUT_SET_LSB: u32 = 0;
428pub const SIO_GPIO_OUT_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
429pub const SIO_GPIO_OUT_CLR_OFFSET: u32 = 24;
430pub const SIO_GPIO_OUT_CLR_BITS: u32 = 1073741823;
431pub const SIO_GPIO_OUT_CLR_RESET: u32 = 0;
432pub const SIO_GPIO_OUT_CLR_MSB: u32 = 29;
433pub const SIO_GPIO_OUT_CLR_LSB: u32 = 0;
434pub const SIO_GPIO_OUT_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
435pub const SIO_GPIO_OUT_XOR_OFFSET: u32 = 28;
436pub const SIO_GPIO_OUT_XOR_BITS: u32 = 1073741823;
437pub const SIO_GPIO_OUT_XOR_RESET: u32 = 0;
438pub const SIO_GPIO_OUT_XOR_MSB: u32 = 29;
439pub const SIO_GPIO_OUT_XOR_LSB: u32 = 0;
440pub const SIO_GPIO_OUT_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
441pub const SIO_GPIO_OE_OFFSET: u32 = 32;
442pub const SIO_GPIO_OE_BITS: u32 = 1073741823;
443pub const SIO_GPIO_OE_RESET: u32 = 0;
444pub const SIO_GPIO_OE_MSB: u32 = 29;
445pub const SIO_GPIO_OE_LSB: u32 = 0;
446pub const SIO_GPIO_OE_ACCESS: &'static [u8; 3usize] = b"RW\0";
447pub const SIO_GPIO_OE_SET_OFFSET: u32 = 36;
448pub const SIO_GPIO_OE_SET_BITS: u32 = 1073741823;
449pub const SIO_GPIO_OE_SET_RESET: u32 = 0;
450pub const SIO_GPIO_OE_SET_MSB: u32 = 29;
451pub const SIO_GPIO_OE_SET_LSB: u32 = 0;
452pub const SIO_GPIO_OE_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
453pub const SIO_GPIO_OE_CLR_OFFSET: u32 = 40;
454pub const SIO_GPIO_OE_CLR_BITS: u32 = 1073741823;
455pub const SIO_GPIO_OE_CLR_RESET: u32 = 0;
456pub const SIO_GPIO_OE_CLR_MSB: u32 = 29;
457pub const SIO_GPIO_OE_CLR_LSB: u32 = 0;
458pub const SIO_GPIO_OE_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
459pub const SIO_GPIO_OE_XOR_OFFSET: u32 = 44;
460pub const SIO_GPIO_OE_XOR_BITS: u32 = 1073741823;
461pub const SIO_GPIO_OE_XOR_RESET: u32 = 0;
462pub const SIO_GPIO_OE_XOR_MSB: u32 = 29;
463pub const SIO_GPIO_OE_XOR_LSB: u32 = 0;
464pub const SIO_GPIO_OE_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
465pub const SIO_GPIO_HI_OUT_OFFSET: u32 = 48;
466pub const SIO_GPIO_HI_OUT_BITS: u32 = 63;
467pub const SIO_GPIO_HI_OUT_RESET: u32 = 0;
468pub const SIO_GPIO_HI_OUT_MSB: u32 = 5;
469pub const SIO_GPIO_HI_OUT_LSB: u32 = 0;
470pub const SIO_GPIO_HI_OUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
471pub const SIO_GPIO_HI_OUT_SET_OFFSET: u32 = 52;
472pub const SIO_GPIO_HI_OUT_SET_BITS: u32 = 63;
473pub const SIO_GPIO_HI_OUT_SET_RESET: u32 = 0;
474pub const SIO_GPIO_HI_OUT_SET_MSB: u32 = 5;
475pub const SIO_GPIO_HI_OUT_SET_LSB: u32 = 0;
476pub const SIO_GPIO_HI_OUT_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
477pub const SIO_GPIO_HI_OUT_CLR_OFFSET: u32 = 56;
478pub const SIO_GPIO_HI_OUT_CLR_BITS: u32 = 63;
479pub const SIO_GPIO_HI_OUT_CLR_RESET: u32 = 0;
480pub const SIO_GPIO_HI_OUT_CLR_MSB: u32 = 5;
481pub const SIO_GPIO_HI_OUT_CLR_LSB: u32 = 0;
482pub const SIO_GPIO_HI_OUT_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
483pub const SIO_GPIO_HI_OUT_XOR_OFFSET: u32 = 60;
484pub const SIO_GPIO_HI_OUT_XOR_BITS: u32 = 63;
485pub const SIO_GPIO_HI_OUT_XOR_RESET: u32 = 0;
486pub const SIO_GPIO_HI_OUT_XOR_MSB: u32 = 5;
487pub const SIO_GPIO_HI_OUT_XOR_LSB: u32 = 0;
488pub const SIO_GPIO_HI_OUT_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
489pub const SIO_GPIO_HI_OE_OFFSET: u32 = 64;
490pub const SIO_GPIO_HI_OE_BITS: u32 = 63;
491pub const SIO_GPIO_HI_OE_RESET: u32 = 0;
492pub const SIO_GPIO_HI_OE_MSB: u32 = 5;
493pub const SIO_GPIO_HI_OE_LSB: u32 = 0;
494pub const SIO_GPIO_HI_OE_ACCESS: &'static [u8; 3usize] = b"RW\0";
495pub const SIO_GPIO_HI_OE_SET_OFFSET: u32 = 68;
496pub const SIO_GPIO_HI_OE_SET_BITS: u32 = 63;
497pub const SIO_GPIO_HI_OE_SET_RESET: u32 = 0;
498pub const SIO_GPIO_HI_OE_SET_MSB: u32 = 5;
499pub const SIO_GPIO_HI_OE_SET_LSB: u32 = 0;
500pub const SIO_GPIO_HI_OE_SET_ACCESS: &'static [u8; 3usize] = b"RW\0";
501pub const SIO_GPIO_HI_OE_CLR_OFFSET: u32 = 72;
502pub const SIO_GPIO_HI_OE_CLR_BITS: u32 = 63;
503pub const SIO_GPIO_HI_OE_CLR_RESET: u32 = 0;
504pub const SIO_GPIO_HI_OE_CLR_MSB: u32 = 5;
505pub const SIO_GPIO_HI_OE_CLR_LSB: u32 = 0;
506pub const SIO_GPIO_HI_OE_CLR_ACCESS: &'static [u8; 3usize] = b"RW\0";
507pub const SIO_GPIO_HI_OE_XOR_OFFSET: u32 = 76;
508pub const SIO_GPIO_HI_OE_XOR_BITS: u32 = 63;
509pub const SIO_GPIO_HI_OE_XOR_RESET: u32 = 0;
510pub const SIO_GPIO_HI_OE_XOR_MSB: u32 = 5;
511pub const SIO_GPIO_HI_OE_XOR_LSB: u32 = 0;
512pub const SIO_GPIO_HI_OE_XOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
513pub const SIO_FIFO_ST_OFFSET: u32 = 80;
514pub const SIO_FIFO_ST_BITS: u32 = 15;
515pub const SIO_FIFO_ST_RESET: u32 = 2;
516pub const SIO_FIFO_ST_ROE_RESET: u32 = 0;
517pub const SIO_FIFO_ST_ROE_BITS: u32 = 8;
518pub const SIO_FIFO_ST_ROE_MSB: u32 = 3;
519pub const SIO_FIFO_ST_ROE_LSB: u32 = 3;
520pub const SIO_FIFO_ST_ROE_ACCESS: &'static [u8; 3usize] = b"WC\0";
521pub const SIO_FIFO_ST_WOF_RESET: u32 = 0;
522pub const SIO_FIFO_ST_WOF_BITS: u32 = 4;
523pub const SIO_FIFO_ST_WOF_MSB: u32 = 2;
524pub const SIO_FIFO_ST_WOF_LSB: u32 = 2;
525pub const SIO_FIFO_ST_WOF_ACCESS: &'static [u8; 3usize] = b"WC\0";
526pub const SIO_FIFO_ST_RDY_RESET: u32 = 1;
527pub const SIO_FIFO_ST_RDY_BITS: u32 = 2;
528pub const SIO_FIFO_ST_RDY_MSB: u32 = 1;
529pub const SIO_FIFO_ST_RDY_LSB: u32 = 1;
530pub const SIO_FIFO_ST_RDY_ACCESS: &'static [u8; 3usize] = b"RO\0";
531pub const SIO_FIFO_ST_VLD_RESET: u32 = 0;
532pub const SIO_FIFO_ST_VLD_BITS: u32 = 1;
533pub const SIO_FIFO_ST_VLD_MSB: u32 = 0;
534pub const SIO_FIFO_ST_VLD_LSB: u32 = 0;
535pub const SIO_FIFO_ST_VLD_ACCESS: &'static [u8; 3usize] = b"RO\0";
536pub const SIO_FIFO_WR_OFFSET: u32 = 84;
537pub const SIO_FIFO_WR_BITS: u32 = 4294967295;
538pub const SIO_FIFO_WR_RESET: u32 = 0;
539pub const SIO_FIFO_WR_MSB: u32 = 31;
540pub const SIO_FIFO_WR_LSB: u32 = 0;
541pub const SIO_FIFO_WR_ACCESS: &'static [u8; 3usize] = b"WF\0";
542pub const SIO_FIFO_RD_OFFSET: u32 = 88;
543pub const SIO_FIFO_RD_BITS: u32 = 4294967295;
544pub const SIO_FIFO_RD_RESET: &'static [u8; 2usize] = b"-\0";
545pub const SIO_FIFO_RD_MSB: u32 = 31;
546pub const SIO_FIFO_RD_LSB: u32 = 0;
547pub const SIO_FIFO_RD_ACCESS: &'static [u8; 3usize] = b"RF\0";
548pub const SIO_SPINLOCK_ST_OFFSET: u32 = 92;
549pub const SIO_SPINLOCK_ST_BITS: u32 = 4294967295;
550pub const SIO_SPINLOCK_ST_RESET: u32 = 0;
551pub const SIO_SPINLOCK_ST_MSB: u32 = 31;
552pub const SIO_SPINLOCK_ST_LSB: u32 = 0;
553pub const SIO_SPINLOCK_ST_ACCESS: &'static [u8; 3usize] = b"RO\0";
554pub const SIO_DIV_UDIVIDEND_OFFSET: u32 = 96;
555pub const SIO_DIV_UDIVIDEND_BITS: u32 = 4294967295;
556pub const SIO_DIV_UDIVIDEND_RESET: u32 = 0;
557pub const SIO_DIV_UDIVIDEND_MSB: u32 = 31;
558pub const SIO_DIV_UDIVIDEND_LSB: u32 = 0;
559pub const SIO_DIV_UDIVIDEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
560pub const SIO_DIV_UDIVISOR_OFFSET: u32 = 100;
561pub const SIO_DIV_UDIVISOR_BITS: u32 = 4294967295;
562pub const SIO_DIV_UDIVISOR_RESET: u32 = 0;
563pub const SIO_DIV_UDIVISOR_MSB: u32 = 31;
564pub const SIO_DIV_UDIVISOR_LSB: u32 = 0;
565pub const SIO_DIV_UDIVISOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
566pub const SIO_DIV_SDIVIDEND_OFFSET: u32 = 104;
567pub const SIO_DIV_SDIVIDEND_BITS: u32 = 4294967295;
568pub const SIO_DIV_SDIVIDEND_RESET: u32 = 0;
569pub const SIO_DIV_SDIVIDEND_MSB: u32 = 31;
570pub const SIO_DIV_SDIVIDEND_LSB: u32 = 0;
571pub const SIO_DIV_SDIVIDEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
572pub const SIO_DIV_SDIVISOR_OFFSET: u32 = 108;
573pub const SIO_DIV_SDIVISOR_BITS: u32 = 4294967295;
574pub const SIO_DIV_SDIVISOR_RESET: u32 = 0;
575pub const SIO_DIV_SDIVISOR_MSB: u32 = 31;
576pub const SIO_DIV_SDIVISOR_LSB: u32 = 0;
577pub const SIO_DIV_SDIVISOR_ACCESS: &'static [u8; 3usize] = b"RW\0";
578pub const SIO_DIV_QUOTIENT_OFFSET: u32 = 112;
579pub const SIO_DIV_QUOTIENT_BITS: u32 = 4294967295;
580pub const SIO_DIV_QUOTIENT_RESET: u32 = 0;
581pub const SIO_DIV_QUOTIENT_MSB: u32 = 31;
582pub const SIO_DIV_QUOTIENT_LSB: u32 = 0;
583pub const SIO_DIV_QUOTIENT_ACCESS: &'static [u8; 3usize] = b"RW\0";
584pub const SIO_DIV_REMAINDER_OFFSET: u32 = 116;
585pub const SIO_DIV_REMAINDER_BITS: u32 = 4294967295;
586pub const SIO_DIV_REMAINDER_RESET: u32 = 0;
587pub const SIO_DIV_REMAINDER_MSB: u32 = 31;
588pub const SIO_DIV_REMAINDER_LSB: u32 = 0;
589pub const SIO_DIV_REMAINDER_ACCESS: &'static [u8; 3usize] = b"RW\0";
590pub const SIO_DIV_CSR_OFFSET: u32 = 120;
591pub const SIO_DIV_CSR_BITS: u32 = 3;
592pub const SIO_DIV_CSR_RESET: u32 = 1;
593pub const SIO_DIV_CSR_DIRTY_RESET: u32 = 0;
594pub const SIO_DIV_CSR_DIRTY_BITS: u32 = 2;
595pub const SIO_DIV_CSR_DIRTY_MSB: u32 = 1;
596pub const SIO_DIV_CSR_DIRTY_LSB: u32 = 1;
597pub const SIO_DIV_CSR_DIRTY_ACCESS: &'static [u8; 3usize] = b"RO\0";
598pub const SIO_DIV_CSR_READY_RESET: u32 = 1;
599pub const SIO_DIV_CSR_READY_BITS: u32 = 1;
600pub const SIO_DIV_CSR_READY_MSB: u32 = 0;
601pub const SIO_DIV_CSR_READY_LSB: u32 = 0;
602pub const SIO_DIV_CSR_READY_ACCESS: &'static [u8; 3usize] = b"RO\0";
603pub const SIO_INTERP0_ACCUM0_OFFSET: u32 = 128;
604pub const SIO_INTERP0_ACCUM0_BITS: u32 = 4294967295;
605pub const SIO_INTERP0_ACCUM0_RESET: u32 = 0;
606pub const SIO_INTERP0_ACCUM0_MSB: u32 = 31;
607pub const SIO_INTERP0_ACCUM0_LSB: u32 = 0;
608pub const SIO_INTERP0_ACCUM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
609pub const SIO_INTERP0_ACCUM1_OFFSET: u32 = 132;
610pub const SIO_INTERP0_ACCUM1_BITS: u32 = 4294967295;
611pub const SIO_INTERP0_ACCUM1_RESET: u32 = 0;
612pub const SIO_INTERP0_ACCUM1_MSB: u32 = 31;
613pub const SIO_INTERP0_ACCUM1_LSB: u32 = 0;
614pub const SIO_INTERP0_ACCUM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
615pub const SIO_INTERP0_BASE0_OFFSET: u32 = 136;
616pub const SIO_INTERP0_BASE0_BITS: u32 = 4294967295;
617pub const SIO_INTERP0_BASE0_RESET: u32 = 0;
618pub const SIO_INTERP0_BASE0_MSB: u32 = 31;
619pub const SIO_INTERP0_BASE0_LSB: u32 = 0;
620pub const SIO_INTERP0_BASE0_ACCESS: &'static [u8; 3usize] = b"RW\0";
621pub const SIO_INTERP0_BASE1_OFFSET: u32 = 140;
622pub const SIO_INTERP0_BASE1_BITS: u32 = 4294967295;
623pub const SIO_INTERP0_BASE1_RESET: u32 = 0;
624pub const SIO_INTERP0_BASE1_MSB: u32 = 31;
625pub const SIO_INTERP0_BASE1_LSB: u32 = 0;
626pub const SIO_INTERP0_BASE1_ACCESS: &'static [u8; 3usize] = b"RW\0";
627pub const SIO_INTERP0_BASE2_OFFSET: u32 = 144;
628pub const SIO_INTERP0_BASE2_BITS: u32 = 4294967295;
629pub const SIO_INTERP0_BASE2_RESET: u32 = 0;
630pub const SIO_INTERP0_BASE2_MSB: u32 = 31;
631pub const SIO_INTERP0_BASE2_LSB: u32 = 0;
632pub const SIO_INTERP0_BASE2_ACCESS: &'static [u8; 3usize] = b"RW\0";
633pub const SIO_INTERP0_POP_LANE0_OFFSET: u32 = 148;
634pub const SIO_INTERP0_POP_LANE0_BITS: u32 = 4294967295;
635pub const SIO_INTERP0_POP_LANE0_RESET: u32 = 0;
636pub const SIO_INTERP0_POP_LANE0_MSB: u32 = 31;
637pub const SIO_INTERP0_POP_LANE0_LSB: u32 = 0;
638pub const SIO_INTERP0_POP_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
639pub const SIO_INTERP0_POP_LANE1_OFFSET: u32 = 152;
640pub const SIO_INTERP0_POP_LANE1_BITS: u32 = 4294967295;
641pub const SIO_INTERP0_POP_LANE1_RESET: u32 = 0;
642pub const SIO_INTERP0_POP_LANE1_MSB: u32 = 31;
643pub const SIO_INTERP0_POP_LANE1_LSB: u32 = 0;
644pub const SIO_INTERP0_POP_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
645pub const SIO_INTERP0_POP_FULL_OFFSET: u32 = 156;
646pub const SIO_INTERP0_POP_FULL_BITS: u32 = 4294967295;
647pub const SIO_INTERP0_POP_FULL_RESET: u32 = 0;
648pub const SIO_INTERP0_POP_FULL_MSB: u32 = 31;
649pub const SIO_INTERP0_POP_FULL_LSB: u32 = 0;
650pub const SIO_INTERP0_POP_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
651pub const SIO_INTERP0_PEEK_LANE0_OFFSET: u32 = 160;
652pub const SIO_INTERP0_PEEK_LANE0_BITS: u32 = 4294967295;
653pub const SIO_INTERP0_PEEK_LANE0_RESET: u32 = 0;
654pub const SIO_INTERP0_PEEK_LANE0_MSB: u32 = 31;
655pub const SIO_INTERP0_PEEK_LANE0_LSB: u32 = 0;
656pub const SIO_INTERP0_PEEK_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
657pub const SIO_INTERP0_PEEK_LANE1_OFFSET: u32 = 164;
658pub const SIO_INTERP0_PEEK_LANE1_BITS: u32 = 4294967295;
659pub const SIO_INTERP0_PEEK_LANE1_RESET: u32 = 0;
660pub const SIO_INTERP0_PEEK_LANE1_MSB: u32 = 31;
661pub const SIO_INTERP0_PEEK_LANE1_LSB: u32 = 0;
662pub const SIO_INTERP0_PEEK_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
663pub const SIO_INTERP0_PEEK_FULL_OFFSET: u32 = 168;
664pub const SIO_INTERP0_PEEK_FULL_BITS: u32 = 4294967295;
665pub const SIO_INTERP0_PEEK_FULL_RESET: u32 = 0;
666pub const SIO_INTERP0_PEEK_FULL_MSB: u32 = 31;
667pub const SIO_INTERP0_PEEK_FULL_LSB: u32 = 0;
668pub const SIO_INTERP0_PEEK_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
669pub const SIO_INTERP0_CTRL_LANE0_OFFSET: u32 = 172;
670pub const SIO_INTERP0_CTRL_LANE0_BITS: u32 = 62914559;
671pub const SIO_INTERP0_CTRL_LANE0_RESET: u32 = 0;
672pub const SIO_INTERP0_CTRL_LANE0_OVERF_RESET: u32 = 0;
673pub const SIO_INTERP0_CTRL_LANE0_OVERF_BITS: u32 = 33554432;
674pub const SIO_INTERP0_CTRL_LANE0_OVERF_MSB: u32 = 25;
675pub const SIO_INTERP0_CTRL_LANE0_OVERF_LSB: u32 = 25;
676pub const SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS: &'static [u8; 3usize] = b"RO\0";
677pub const SIO_INTERP0_CTRL_LANE0_OVERF1_RESET: u32 = 0;
678pub const SIO_INTERP0_CTRL_LANE0_OVERF1_BITS: u32 = 16777216;
679pub const SIO_INTERP0_CTRL_LANE0_OVERF1_MSB: u32 = 24;
680pub const SIO_INTERP0_CTRL_LANE0_OVERF1_LSB: u32 = 24;
681pub const SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS: &'static [u8; 3usize] = b"RO\0";
682pub const SIO_INTERP0_CTRL_LANE0_OVERF0_RESET: u32 = 0;
683pub const SIO_INTERP0_CTRL_LANE0_OVERF0_BITS: u32 = 8388608;
684pub const SIO_INTERP0_CTRL_LANE0_OVERF0_MSB: u32 = 23;
685pub const SIO_INTERP0_CTRL_LANE0_OVERF0_LSB: u32 = 23;
686pub const SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS: &'static [u8; 3usize] = b"RO\0";
687pub const SIO_INTERP0_CTRL_LANE0_BLEND_RESET: u32 = 0;
688pub const SIO_INTERP0_CTRL_LANE0_BLEND_BITS: u32 = 2097152;
689pub const SIO_INTERP0_CTRL_LANE0_BLEND_MSB: u32 = 21;
690pub const SIO_INTERP0_CTRL_LANE0_BLEND_LSB: u32 = 21;
691pub const SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS: &'static [u8; 3usize] = b"RW\0";
692pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET: u32 = 0;
693pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS: u32 = 1572864;
694pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB: u32 = 20;
695pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB: u32 = 19;
696pub const SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
697pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET: u32 = 0;
698pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS: u32 = 262144;
699pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB: u32 = 18;
700pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB: u32 = 18;
701pub const SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
702pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET: u32 = 0;
703pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS: u32 = 131072;
704pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB: u32 = 17;
705pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB: u32 = 17;
706pub const SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
707pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET: u32 = 0;
708pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS: u32 = 65536;
709pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB: u32 = 16;
710pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB: u32 = 16;
711pub const SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
712pub const SIO_INTERP0_CTRL_LANE0_SIGNED_RESET: u32 = 0;
713pub const SIO_INTERP0_CTRL_LANE0_SIGNED_BITS: u32 = 32768;
714pub const SIO_INTERP0_CTRL_LANE0_SIGNED_MSB: u32 = 15;
715pub const SIO_INTERP0_CTRL_LANE0_SIGNED_LSB: u32 = 15;
716pub const SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
717pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET: u32 = 0;
718pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS: u32 = 31744;
719pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB: u32 = 14;
720pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB: u32 = 10;
721pub const SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
722pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET: u32 = 0;
723pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS: u32 = 992;
724pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB: u32 = 9;
725pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB: u32 = 5;
726pub const SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
727pub const SIO_INTERP0_CTRL_LANE0_SHIFT_RESET: u32 = 0;
728pub const SIO_INTERP0_CTRL_LANE0_SHIFT_BITS: u32 = 31;
729pub const SIO_INTERP0_CTRL_LANE0_SHIFT_MSB: u32 = 4;
730pub const SIO_INTERP0_CTRL_LANE0_SHIFT_LSB: u32 = 0;
731pub const SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
732pub const SIO_INTERP0_CTRL_LANE1_OFFSET: u32 = 176;
733pub const SIO_INTERP0_CTRL_LANE1_BITS: u32 = 2097151;
734pub const SIO_INTERP0_CTRL_LANE1_RESET: u32 = 0;
735pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET: u32 = 0;
736pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS: u32 = 1572864;
737pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB: u32 = 20;
738pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB: u32 = 19;
739pub const SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
740pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET: u32 = 0;
741pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS: u32 = 262144;
742pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB: u32 = 18;
743pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB: u32 = 18;
744pub const SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
745pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET: u32 = 0;
746pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS: u32 = 131072;
747pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB: u32 = 17;
748pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB: u32 = 17;
749pub const SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
750pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET: u32 = 0;
751pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS: u32 = 65536;
752pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB: u32 = 16;
753pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB: u32 = 16;
754pub const SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
755pub const SIO_INTERP0_CTRL_LANE1_SIGNED_RESET: u32 = 0;
756pub const SIO_INTERP0_CTRL_LANE1_SIGNED_BITS: u32 = 32768;
757pub const SIO_INTERP0_CTRL_LANE1_SIGNED_MSB: u32 = 15;
758pub const SIO_INTERP0_CTRL_LANE1_SIGNED_LSB: u32 = 15;
759pub const SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
760pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET: u32 = 0;
761pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS: u32 = 31744;
762pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB: u32 = 14;
763pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB: u32 = 10;
764pub const SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
765pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET: u32 = 0;
766pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS: u32 = 992;
767pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB: u32 = 9;
768pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB: u32 = 5;
769pub const SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
770pub const SIO_INTERP0_CTRL_LANE1_SHIFT_RESET: u32 = 0;
771pub const SIO_INTERP0_CTRL_LANE1_SHIFT_BITS: u32 = 31;
772pub const SIO_INTERP0_CTRL_LANE1_SHIFT_MSB: u32 = 4;
773pub const SIO_INTERP0_CTRL_LANE1_SHIFT_LSB: u32 = 0;
774pub const SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
775pub const SIO_INTERP0_ACCUM0_ADD_OFFSET: u32 = 180;
776pub const SIO_INTERP0_ACCUM0_ADD_BITS: u32 = 16777215;
777pub const SIO_INTERP0_ACCUM0_ADD_RESET: u32 = 0;
778pub const SIO_INTERP0_ACCUM0_ADD_MSB: u32 = 23;
779pub const SIO_INTERP0_ACCUM0_ADD_LSB: u32 = 0;
780pub const SIO_INTERP0_ACCUM0_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
781pub const SIO_INTERP0_ACCUM1_ADD_OFFSET: u32 = 184;
782pub const SIO_INTERP0_ACCUM1_ADD_BITS: u32 = 16777215;
783pub const SIO_INTERP0_ACCUM1_ADD_RESET: u32 = 0;
784pub const SIO_INTERP0_ACCUM1_ADD_MSB: u32 = 23;
785pub const SIO_INTERP0_ACCUM1_ADD_LSB: u32 = 0;
786pub const SIO_INTERP0_ACCUM1_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
787pub const SIO_INTERP0_BASE_1AND0_OFFSET: u32 = 188;
788pub const SIO_INTERP0_BASE_1AND0_BITS: u32 = 4294967295;
789pub const SIO_INTERP0_BASE_1AND0_RESET: u32 = 0;
790pub const SIO_INTERP0_BASE_1AND0_MSB: u32 = 31;
791pub const SIO_INTERP0_BASE_1AND0_LSB: u32 = 0;
792pub const SIO_INTERP0_BASE_1AND0_ACCESS: &'static [u8; 3usize] = b"WO\0";
793pub const SIO_INTERP1_ACCUM0_OFFSET: u32 = 192;
794pub const SIO_INTERP1_ACCUM0_BITS: u32 = 4294967295;
795pub const SIO_INTERP1_ACCUM0_RESET: u32 = 0;
796pub const SIO_INTERP1_ACCUM0_MSB: u32 = 31;
797pub const SIO_INTERP1_ACCUM0_LSB: u32 = 0;
798pub const SIO_INTERP1_ACCUM0_ACCESS: &'static [u8; 3usize] = b"RW\0";
799pub const SIO_INTERP1_ACCUM1_OFFSET: u32 = 196;
800pub const SIO_INTERP1_ACCUM1_BITS: u32 = 4294967295;
801pub const SIO_INTERP1_ACCUM1_RESET: u32 = 0;
802pub const SIO_INTERP1_ACCUM1_MSB: u32 = 31;
803pub const SIO_INTERP1_ACCUM1_LSB: u32 = 0;
804pub const SIO_INTERP1_ACCUM1_ACCESS: &'static [u8; 3usize] = b"RW\0";
805pub const SIO_INTERP1_BASE0_OFFSET: u32 = 200;
806pub const SIO_INTERP1_BASE0_BITS: u32 = 4294967295;
807pub const SIO_INTERP1_BASE0_RESET: u32 = 0;
808pub const SIO_INTERP1_BASE0_MSB: u32 = 31;
809pub const SIO_INTERP1_BASE0_LSB: u32 = 0;
810pub const SIO_INTERP1_BASE0_ACCESS: &'static [u8; 3usize] = b"RW\0";
811pub const SIO_INTERP1_BASE1_OFFSET: u32 = 204;
812pub const SIO_INTERP1_BASE1_BITS: u32 = 4294967295;
813pub const SIO_INTERP1_BASE1_RESET: u32 = 0;
814pub const SIO_INTERP1_BASE1_MSB: u32 = 31;
815pub const SIO_INTERP1_BASE1_LSB: u32 = 0;
816pub const SIO_INTERP1_BASE1_ACCESS: &'static [u8; 3usize] = b"RW\0";
817pub const SIO_INTERP1_BASE2_OFFSET: u32 = 208;
818pub const SIO_INTERP1_BASE2_BITS: u32 = 4294967295;
819pub const SIO_INTERP1_BASE2_RESET: u32 = 0;
820pub const SIO_INTERP1_BASE2_MSB: u32 = 31;
821pub const SIO_INTERP1_BASE2_LSB: u32 = 0;
822pub const SIO_INTERP1_BASE2_ACCESS: &'static [u8; 3usize] = b"RW\0";
823pub const SIO_INTERP1_POP_LANE0_OFFSET: u32 = 212;
824pub const SIO_INTERP1_POP_LANE0_BITS: u32 = 4294967295;
825pub const SIO_INTERP1_POP_LANE0_RESET: u32 = 0;
826pub const SIO_INTERP1_POP_LANE0_MSB: u32 = 31;
827pub const SIO_INTERP1_POP_LANE0_LSB: u32 = 0;
828pub const SIO_INTERP1_POP_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
829pub const SIO_INTERP1_POP_LANE1_OFFSET: u32 = 216;
830pub const SIO_INTERP1_POP_LANE1_BITS: u32 = 4294967295;
831pub const SIO_INTERP1_POP_LANE1_RESET: u32 = 0;
832pub const SIO_INTERP1_POP_LANE1_MSB: u32 = 31;
833pub const SIO_INTERP1_POP_LANE1_LSB: u32 = 0;
834pub const SIO_INTERP1_POP_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
835pub const SIO_INTERP1_POP_FULL_OFFSET: u32 = 220;
836pub const SIO_INTERP1_POP_FULL_BITS: u32 = 4294967295;
837pub const SIO_INTERP1_POP_FULL_RESET: u32 = 0;
838pub const SIO_INTERP1_POP_FULL_MSB: u32 = 31;
839pub const SIO_INTERP1_POP_FULL_LSB: u32 = 0;
840pub const SIO_INTERP1_POP_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
841pub const SIO_INTERP1_PEEK_LANE0_OFFSET: u32 = 224;
842pub const SIO_INTERP1_PEEK_LANE0_BITS: u32 = 4294967295;
843pub const SIO_INTERP1_PEEK_LANE0_RESET: u32 = 0;
844pub const SIO_INTERP1_PEEK_LANE0_MSB: u32 = 31;
845pub const SIO_INTERP1_PEEK_LANE0_LSB: u32 = 0;
846pub const SIO_INTERP1_PEEK_LANE0_ACCESS: &'static [u8; 3usize] = b"RO\0";
847pub const SIO_INTERP1_PEEK_LANE1_OFFSET: u32 = 228;
848pub const SIO_INTERP1_PEEK_LANE1_BITS: u32 = 4294967295;
849pub const SIO_INTERP1_PEEK_LANE1_RESET: u32 = 0;
850pub const SIO_INTERP1_PEEK_LANE1_MSB: u32 = 31;
851pub const SIO_INTERP1_PEEK_LANE1_LSB: u32 = 0;
852pub const SIO_INTERP1_PEEK_LANE1_ACCESS: &'static [u8; 3usize] = b"RO\0";
853pub const SIO_INTERP1_PEEK_FULL_OFFSET: u32 = 232;
854pub const SIO_INTERP1_PEEK_FULL_BITS: u32 = 4294967295;
855pub const SIO_INTERP1_PEEK_FULL_RESET: u32 = 0;
856pub const SIO_INTERP1_PEEK_FULL_MSB: u32 = 31;
857pub const SIO_INTERP1_PEEK_FULL_LSB: u32 = 0;
858pub const SIO_INTERP1_PEEK_FULL_ACCESS: &'static [u8; 3usize] = b"RO\0";
859pub const SIO_INTERP1_CTRL_LANE0_OFFSET: u32 = 236;
860pub const SIO_INTERP1_CTRL_LANE0_BITS: u32 = 65011711;
861pub const SIO_INTERP1_CTRL_LANE0_RESET: u32 = 0;
862pub const SIO_INTERP1_CTRL_LANE0_OVERF_RESET: u32 = 0;
863pub const SIO_INTERP1_CTRL_LANE0_OVERF_BITS: u32 = 33554432;
864pub const SIO_INTERP1_CTRL_LANE0_OVERF_MSB: u32 = 25;
865pub const SIO_INTERP1_CTRL_LANE0_OVERF_LSB: u32 = 25;
866pub const SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS: &'static [u8; 3usize] = b"RO\0";
867pub const SIO_INTERP1_CTRL_LANE0_OVERF1_RESET: u32 = 0;
868pub const SIO_INTERP1_CTRL_LANE0_OVERF1_BITS: u32 = 16777216;
869pub const SIO_INTERP1_CTRL_LANE0_OVERF1_MSB: u32 = 24;
870pub const SIO_INTERP1_CTRL_LANE0_OVERF1_LSB: u32 = 24;
871pub const SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS: &'static [u8; 3usize] = b"RO\0";
872pub const SIO_INTERP1_CTRL_LANE0_OVERF0_RESET: u32 = 0;
873pub const SIO_INTERP1_CTRL_LANE0_OVERF0_BITS: u32 = 8388608;
874pub const SIO_INTERP1_CTRL_LANE0_OVERF0_MSB: u32 = 23;
875pub const SIO_INTERP1_CTRL_LANE0_OVERF0_LSB: u32 = 23;
876pub const SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS: &'static [u8; 3usize] = b"RO\0";
877pub const SIO_INTERP1_CTRL_LANE0_CLAMP_RESET: u32 = 0;
878pub const SIO_INTERP1_CTRL_LANE0_CLAMP_BITS: u32 = 4194304;
879pub const SIO_INTERP1_CTRL_LANE0_CLAMP_MSB: u32 = 22;
880pub const SIO_INTERP1_CTRL_LANE0_CLAMP_LSB: u32 = 22;
881pub const SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS: &'static [u8; 3usize] = b"RW\0";
882pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET: u32 = 0;
883pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS: u32 = 1572864;
884pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB: u32 = 20;
885pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB: u32 = 19;
886pub const SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
887pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET: u32 = 0;
888pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS: u32 = 262144;
889pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB: u32 = 18;
890pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB: u32 = 18;
891pub const SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
892pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET: u32 = 0;
893pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS: u32 = 131072;
894pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB: u32 = 17;
895pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB: u32 = 17;
896pub const SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
897pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET: u32 = 0;
898pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS: u32 = 65536;
899pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB: u32 = 16;
900pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB: u32 = 16;
901pub const SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
902pub const SIO_INTERP1_CTRL_LANE0_SIGNED_RESET: u32 = 0;
903pub const SIO_INTERP1_CTRL_LANE0_SIGNED_BITS: u32 = 32768;
904pub const SIO_INTERP1_CTRL_LANE0_SIGNED_MSB: u32 = 15;
905pub const SIO_INTERP1_CTRL_LANE0_SIGNED_LSB: u32 = 15;
906pub const SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
907pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET: u32 = 0;
908pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS: u32 = 31744;
909pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB: u32 = 14;
910pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB: u32 = 10;
911pub const SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
912pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET: u32 = 0;
913pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS: u32 = 992;
914pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB: u32 = 9;
915pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB: u32 = 5;
916pub const SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
917pub const SIO_INTERP1_CTRL_LANE0_SHIFT_RESET: u32 = 0;
918pub const SIO_INTERP1_CTRL_LANE0_SHIFT_BITS: u32 = 31;
919pub const SIO_INTERP1_CTRL_LANE0_SHIFT_MSB: u32 = 4;
920pub const SIO_INTERP1_CTRL_LANE0_SHIFT_LSB: u32 = 0;
921pub const SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
922pub const SIO_INTERP1_CTRL_LANE1_OFFSET: u32 = 240;
923pub const SIO_INTERP1_CTRL_LANE1_BITS: u32 = 2097151;
924pub const SIO_INTERP1_CTRL_LANE1_RESET: u32 = 0;
925pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET: u32 = 0;
926pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS: u32 = 1572864;
927pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB: u32 = 20;
928pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB: u32 = 19;
929pub const SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
930pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET: u32 = 0;
931pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS: u32 = 262144;
932pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB: u32 = 18;
933pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB: u32 = 18;
934pub const SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS: &'static [u8; 3usize] = b"RW\0";
935pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET: u32 = 0;
936pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS: u32 = 131072;
937pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB: u32 = 17;
938pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB: u32 = 17;
939pub const SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS: &'static [u8; 3usize] = b"RW\0";
940pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET: u32 = 0;
941pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS: u32 = 65536;
942pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB: u32 = 16;
943pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB: u32 = 16;
944pub const SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS: &'static [u8; 3usize] = b"RW\0";
945pub const SIO_INTERP1_CTRL_LANE1_SIGNED_RESET: u32 = 0;
946pub const SIO_INTERP1_CTRL_LANE1_SIGNED_BITS: u32 = 32768;
947pub const SIO_INTERP1_CTRL_LANE1_SIGNED_MSB: u32 = 15;
948pub const SIO_INTERP1_CTRL_LANE1_SIGNED_LSB: u32 = 15;
949pub const SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS: &'static [u8; 3usize] = b"RW\0";
950pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET: u32 = 0;
951pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS: u32 = 31744;
952pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB: u32 = 14;
953pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB: u32 = 10;
954pub const SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
955pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET: u32 = 0;
956pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS: u32 = 992;
957pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB: u32 = 9;
958pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB: u32 = 5;
959pub const SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS: &'static [u8; 3usize] = b"RW\0";
960pub const SIO_INTERP1_CTRL_LANE1_SHIFT_RESET: u32 = 0;
961pub const SIO_INTERP1_CTRL_LANE1_SHIFT_BITS: u32 = 31;
962pub const SIO_INTERP1_CTRL_LANE1_SHIFT_MSB: u32 = 4;
963pub const SIO_INTERP1_CTRL_LANE1_SHIFT_LSB: u32 = 0;
964pub const SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS: &'static [u8; 3usize] = b"RW\0";
965pub const SIO_INTERP1_ACCUM0_ADD_OFFSET: u32 = 244;
966pub const SIO_INTERP1_ACCUM0_ADD_BITS: u32 = 16777215;
967pub const SIO_INTERP1_ACCUM0_ADD_RESET: u32 = 0;
968pub const SIO_INTERP1_ACCUM0_ADD_MSB: u32 = 23;
969pub const SIO_INTERP1_ACCUM0_ADD_LSB: u32 = 0;
970pub const SIO_INTERP1_ACCUM0_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
971pub const SIO_INTERP1_ACCUM1_ADD_OFFSET: u32 = 248;
972pub const SIO_INTERP1_ACCUM1_ADD_BITS: u32 = 16777215;
973pub const SIO_INTERP1_ACCUM1_ADD_RESET: u32 = 0;
974pub const SIO_INTERP1_ACCUM1_ADD_MSB: u32 = 23;
975pub const SIO_INTERP1_ACCUM1_ADD_LSB: u32 = 0;
976pub const SIO_INTERP1_ACCUM1_ADD_ACCESS: &'static [u8; 3usize] = b"RW\0";
977pub const SIO_INTERP1_BASE_1AND0_OFFSET: u32 = 252;
978pub const SIO_INTERP1_BASE_1AND0_BITS: u32 = 4294967295;
979pub const SIO_INTERP1_BASE_1AND0_RESET: u32 = 0;
980pub const SIO_INTERP1_BASE_1AND0_MSB: u32 = 31;
981pub const SIO_INTERP1_BASE_1AND0_LSB: u32 = 0;
982pub const SIO_INTERP1_BASE_1AND0_ACCESS: &'static [u8; 3usize] = b"WO\0";
983pub const SIO_SPINLOCK0_OFFSET: u32 = 256;
984pub const SIO_SPINLOCK0_BITS: u32 = 4294967295;
985pub const SIO_SPINLOCK0_RESET: u32 = 0;
986pub const SIO_SPINLOCK0_MSB: u32 = 31;
987pub const SIO_SPINLOCK0_LSB: u32 = 0;
988pub const SIO_SPINLOCK0_ACCESS: &'static [u8; 3usize] = b"RO\0";
989pub const SIO_SPINLOCK1_OFFSET: u32 = 260;
990pub const SIO_SPINLOCK1_BITS: u32 = 4294967295;
991pub const SIO_SPINLOCK1_RESET: u32 = 0;
992pub const SIO_SPINLOCK1_MSB: u32 = 31;
993pub const SIO_SPINLOCK1_LSB: u32 = 0;
994pub const SIO_SPINLOCK1_ACCESS: &'static [u8; 3usize] = b"RO\0";
995pub const SIO_SPINLOCK2_OFFSET: u32 = 264;
996pub const SIO_SPINLOCK2_BITS: u32 = 4294967295;
997pub const SIO_SPINLOCK2_RESET: u32 = 0;
998pub const SIO_SPINLOCK2_MSB: u32 = 31;
999pub const SIO_SPINLOCK2_LSB: u32 = 0;
1000pub const SIO_SPINLOCK2_ACCESS: &'static [u8; 3usize] = b"RO\0";
1001pub const SIO_SPINLOCK3_OFFSET: u32 = 268;
1002pub const SIO_SPINLOCK3_BITS: u32 = 4294967295;
1003pub const SIO_SPINLOCK3_RESET: u32 = 0;
1004pub const SIO_SPINLOCK3_MSB: u32 = 31;
1005pub const SIO_SPINLOCK3_LSB: u32 = 0;
1006pub const SIO_SPINLOCK3_ACCESS: &'static [u8; 3usize] = b"RO\0";
1007pub const SIO_SPINLOCK4_OFFSET: u32 = 272;
1008pub const SIO_SPINLOCK4_BITS: u32 = 4294967295;
1009pub const SIO_SPINLOCK4_RESET: u32 = 0;
1010pub const SIO_SPINLOCK4_MSB: u32 = 31;
1011pub const SIO_SPINLOCK4_LSB: u32 = 0;
1012pub const SIO_SPINLOCK4_ACCESS: &'static [u8; 3usize] = b"RO\0";
1013pub const SIO_SPINLOCK5_OFFSET: u32 = 276;
1014pub const SIO_SPINLOCK5_BITS: u32 = 4294967295;
1015pub const SIO_SPINLOCK5_RESET: u32 = 0;
1016pub const SIO_SPINLOCK5_MSB: u32 = 31;
1017pub const SIO_SPINLOCK5_LSB: u32 = 0;
1018pub const SIO_SPINLOCK5_ACCESS: &'static [u8; 3usize] = b"RO\0";
1019pub const SIO_SPINLOCK6_OFFSET: u32 = 280;
1020pub const SIO_SPINLOCK6_BITS: u32 = 4294967295;
1021pub const SIO_SPINLOCK6_RESET: u32 = 0;
1022pub const SIO_SPINLOCK6_MSB: u32 = 31;
1023pub const SIO_SPINLOCK6_LSB: u32 = 0;
1024pub const SIO_SPINLOCK6_ACCESS: &'static [u8; 3usize] = b"RO\0";
1025pub const SIO_SPINLOCK7_OFFSET: u32 = 284;
1026pub const SIO_SPINLOCK7_BITS: u32 = 4294967295;
1027pub const SIO_SPINLOCK7_RESET: u32 = 0;
1028pub const SIO_SPINLOCK7_MSB: u32 = 31;
1029pub const SIO_SPINLOCK7_LSB: u32 = 0;
1030pub const SIO_SPINLOCK7_ACCESS: &'static [u8; 3usize] = b"RO\0";
1031pub const SIO_SPINLOCK8_OFFSET: u32 = 288;
1032pub const SIO_SPINLOCK8_BITS: u32 = 4294967295;
1033pub const SIO_SPINLOCK8_RESET: u32 = 0;
1034pub const SIO_SPINLOCK8_MSB: u32 = 31;
1035pub const SIO_SPINLOCK8_LSB: u32 = 0;
1036pub const SIO_SPINLOCK8_ACCESS: &'static [u8; 3usize] = b"RO\0";
1037pub const SIO_SPINLOCK9_OFFSET: u32 = 292;
1038pub const SIO_SPINLOCK9_BITS: u32 = 4294967295;
1039pub const SIO_SPINLOCK9_RESET: u32 = 0;
1040pub const SIO_SPINLOCK9_MSB: u32 = 31;
1041pub const SIO_SPINLOCK9_LSB: u32 = 0;
1042pub const SIO_SPINLOCK9_ACCESS: &'static [u8; 3usize] = b"RO\0";
1043pub const SIO_SPINLOCK10_OFFSET: u32 = 296;
1044pub const SIO_SPINLOCK10_BITS: u32 = 4294967295;
1045pub const SIO_SPINLOCK10_RESET: u32 = 0;
1046pub const SIO_SPINLOCK10_MSB: u32 = 31;
1047pub const SIO_SPINLOCK10_LSB: u32 = 0;
1048pub const SIO_SPINLOCK10_ACCESS: &'static [u8; 3usize] = b"RO\0";
1049pub const SIO_SPINLOCK11_OFFSET: u32 = 300;
1050pub const SIO_SPINLOCK11_BITS: u32 = 4294967295;
1051pub const SIO_SPINLOCK11_RESET: u32 = 0;
1052pub const SIO_SPINLOCK11_MSB: u32 = 31;
1053pub const SIO_SPINLOCK11_LSB: u32 = 0;
1054pub const SIO_SPINLOCK11_ACCESS: &'static [u8; 3usize] = b"RO\0";
1055pub const SIO_SPINLOCK12_OFFSET: u32 = 304;
1056pub const SIO_SPINLOCK12_BITS: u32 = 4294967295;
1057pub const SIO_SPINLOCK12_RESET: u32 = 0;
1058pub const SIO_SPINLOCK12_MSB: u32 = 31;
1059pub const SIO_SPINLOCK12_LSB: u32 = 0;
1060pub const SIO_SPINLOCK12_ACCESS: &'static [u8; 3usize] = b"RO\0";
1061pub const SIO_SPINLOCK13_OFFSET: u32 = 308;
1062pub const SIO_SPINLOCK13_BITS: u32 = 4294967295;
1063pub const SIO_SPINLOCK13_RESET: u32 = 0;
1064pub const SIO_SPINLOCK13_MSB: u32 = 31;
1065pub const SIO_SPINLOCK13_LSB: u32 = 0;
1066pub const SIO_SPINLOCK13_ACCESS: &'static [u8; 3usize] = b"RO\0";
1067pub const SIO_SPINLOCK14_OFFSET: u32 = 312;
1068pub const SIO_SPINLOCK14_BITS: u32 = 4294967295;
1069pub const SIO_SPINLOCK14_RESET: u32 = 0;
1070pub const SIO_SPINLOCK14_MSB: u32 = 31;
1071pub const SIO_SPINLOCK14_LSB: u32 = 0;
1072pub const SIO_SPINLOCK14_ACCESS: &'static [u8; 3usize] = b"RO\0";
1073pub const SIO_SPINLOCK15_OFFSET: u32 = 316;
1074pub const SIO_SPINLOCK15_BITS: u32 = 4294967295;
1075pub const SIO_SPINLOCK15_RESET: u32 = 0;
1076pub const SIO_SPINLOCK15_MSB: u32 = 31;
1077pub const SIO_SPINLOCK15_LSB: u32 = 0;
1078pub const SIO_SPINLOCK15_ACCESS: &'static [u8; 3usize] = b"RO\0";
1079pub const SIO_SPINLOCK16_OFFSET: u32 = 320;
1080pub const SIO_SPINLOCK16_BITS: u32 = 4294967295;
1081pub const SIO_SPINLOCK16_RESET: u32 = 0;
1082pub const SIO_SPINLOCK16_MSB: u32 = 31;
1083pub const SIO_SPINLOCK16_LSB: u32 = 0;
1084pub const SIO_SPINLOCK16_ACCESS: &'static [u8; 3usize] = b"RO\0";
1085pub const SIO_SPINLOCK17_OFFSET: u32 = 324;
1086pub const SIO_SPINLOCK17_BITS: u32 = 4294967295;
1087pub const SIO_SPINLOCK17_RESET: u32 = 0;
1088pub const SIO_SPINLOCK17_MSB: u32 = 31;
1089pub const SIO_SPINLOCK17_LSB: u32 = 0;
1090pub const SIO_SPINLOCK17_ACCESS: &'static [u8; 3usize] = b"RO\0";
1091pub const SIO_SPINLOCK18_OFFSET: u32 = 328;
1092pub const SIO_SPINLOCK18_BITS: u32 = 4294967295;
1093pub const SIO_SPINLOCK18_RESET: u32 = 0;
1094pub const SIO_SPINLOCK18_MSB: u32 = 31;
1095pub const SIO_SPINLOCK18_LSB: u32 = 0;
1096pub const SIO_SPINLOCK18_ACCESS: &'static [u8; 3usize] = b"RO\0";
1097pub const SIO_SPINLOCK19_OFFSET: u32 = 332;
1098pub const SIO_SPINLOCK19_BITS: u32 = 4294967295;
1099pub const SIO_SPINLOCK19_RESET: u32 = 0;
1100pub const SIO_SPINLOCK19_MSB: u32 = 31;
1101pub const SIO_SPINLOCK19_LSB: u32 = 0;
1102pub const SIO_SPINLOCK19_ACCESS: &'static [u8; 3usize] = b"RO\0";
1103pub const SIO_SPINLOCK20_OFFSET: u32 = 336;
1104pub const SIO_SPINLOCK20_BITS: u32 = 4294967295;
1105pub const SIO_SPINLOCK20_RESET: u32 = 0;
1106pub const SIO_SPINLOCK20_MSB: u32 = 31;
1107pub const SIO_SPINLOCK20_LSB: u32 = 0;
1108pub const SIO_SPINLOCK20_ACCESS: &'static [u8; 3usize] = b"RO\0";
1109pub const SIO_SPINLOCK21_OFFSET: u32 = 340;
1110pub const SIO_SPINLOCK21_BITS: u32 = 4294967295;
1111pub const SIO_SPINLOCK21_RESET: u32 = 0;
1112pub const SIO_SPINLOCK21_MSB: u32 = 31;
1113pub const SIO_SPINLOCK21_LSB: u32 = 0;
1114pub const SIO_SPINLOCK21_ACCESS: &'static [u8; 3usize] = b"RO\0";
1115pub const SIO_SPINLOCK22_OFFSET: u32 = 344;
1116pub const SIO_SPINLOCK22_BITS: u32 = 4294967295;
1117pub const SIO_SPINLOCK22_RESET: u32 = 0;
1118pub const SIO_SPINLOCK22_MSB: u32 = 31;
1119pub const SIO_SPINLOCK22_LSB: u32 = 0;
1120pub const SIO_SPINLOCK22_ACCESS: &'static [u8; 3usize] = b"RO\0";
1121pub const SIO_SPINLOCK23_OFFSET: u32 = 348;
1122pub const SIO_SPINLOCK23_BITS: u32 = 4294967295;
1123pub const SIO_SPINLOCK23_RESET: u32 = 0;
1124pub const SIO_SPINLOCK23_MSB: u32 = 31;
1125pub const SIO_SPINLOCK23_LSB: u32 = 0;
1126pub const SIO_SPINLOCK23_ACCESS: &'static [u8; 3usize] = b"RO\0";
1127pub const SIO_SPINLOCK24_OFFSET: u32 = 352;
1128pub const SIO_SPINLOCK24_BITS: u32 = 4294967295;
1129pub const SIO_SPINLOCK24_RESET: u32 = 0;
1130pub const SIO_SPINLOCK24_MSB: u32 = 31;
1131pub const SIO_SPINLOCK24_LSB: u32 = 0;
1132pub const SIO_SPINLOCK24_ACCESS: &'static [u8; 3usize] = b"RO\0";
1133pub const SIO_SPINLOCK25_OFFSET: u32 = 356;
1134pub const SIO_SPINLOCK25_BITS: u32 = 4294967295;
1135pub const SIO_SPINLOCK25_RESET: u32 = 0;
1136pub const SIO_SPINLOCK25_MSB: u32 = 31;
1137pub const SIO_SPINLOCK25_LSB: u32 = 0;
1138pub const SIO_SPINLOCK25_ACCESS: &'static [u8; 3usize] = b"RO\0";
1139pub const SIO_SPINLOCK26_OFFSET: u32 = 360;
1140pub const SIO_SPINLOCK26_BITS: u32 = 4294967295;
1141pub const SIO_SPINLOCK26_RESET: u32 = 0;
1142pub const SIO_SPINLOCK26_MSB: u32 = 31;
1143pub const SIO_SPINLOCK26_LSB: u32 = 0;
1144pub const SIO_SPINLOCK26_ACCESS: &'static [u8; 3usize] = b"RO\0";
1145pub const SIO_SPINLOCK27_OFFSET: u32 = 364;
1146pub const SIO_SPINLOCK27_BITS: u32 = 4294967295;
1147pub const SIO_SPINLOCK27_RESET: u32 = 0;
1148pub const SIO_SPINLOCK27_MSB: u32 = 31;
1149pub const SIO_SPINLOCK27_LSB: u32 = 0;
1150pub const SIO_SPINLOCK27_ACCESS: &'static [u8; 3usize] = b"RO\0";
1151pub const SIO_SPINLOCK28_OFFSET: u32 = 368;
1152pub const SIO_SPINLOCK28_BITS: u32 = 4294967295;
1153pub const SIO_SPINLOCK28_RESET: u32 = 0;
1154pub const SIO_SPINLOCK28_MSB: u32 = 31;
1155pub const SIO_SPINLOCK28_LSB: u32 = 0;
1156pub const SIO_SPINLOCK28_ACCESS: &'static [u8; 3usize] = b"RO\0";
1157pub const SIO_SPINLOCK29_OFFSET: u32 = 372;
1158pub const SIO_SPINLOCK29_BITS: u32 = 4294967295;
1159pub const SIO_SPINLOCK29_RESET: u32 = 0;
1160pub const SIO_SPINLOCK29_MSB: u32 = 31;
1161pub const SIO_SPINLOCK29_LSB: u32 = 0;
1162pub const SIO_SPINLOCK29_ACCESS: &'static [u8; 3usize] = b"RO\0";
1163pub const SIO_SPINLOCK30_OFFSET: u32 = 376;
1164pub const SIO_SPINLOCK30_BITS: u32 = 4294967295;
1165pub const SIO_SPINLOCK30_RESET: u32 = 0;
1166pub const SIO_SPINLOCK30_MSB: u32 = 31;
1167pub const SIO_SPINLOCK30_LSB: u32 = 0;
1168pub const SIO_SPINLOCK30_ACCESS: &'static [u8; 3usize] = b"RO\0";
1169pub const SIO_SPINLOCK31_OFFSET: u32 = 380;
1170pub const SIO_SPINLOCK31_BITS: u32 = 4294967295;
1171pub const SIO_SPINLOCK31_RESET: u32 = 0;
1172pub const SIO_SPINLOCK31_MSB: u32 = 31;
1173pub const SIO_SPINLOCK31_LSB: u32 = 0;
1174pub const SIO_SPINLOCK31_ACCESS: &'static [u8; 3usize] = b"RO\0";
1175pub const PADS_BANK0_VOLTAGE_SELECT_OFFSET: u32 = 0;
1176pub const PADS_BANK0_VOLTAGE_SELECT_BITS: u32 = 1;
1177pub const PADS_BANK0_VOLTAGE_SELECT_RESET: u32 = 0;
1178pub const PADS_BANK0_VOLTAGE_SELECT_MSB: u32 = 0;
1179pub const PADS_BANK0_VOLTAGE_SELECT_LSB: u32 = 0;
1180pub const PADS_BANK0_VOLTAGE_SELECT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1181pub const PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3: u32 = 0;
1182pub const PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8: u32 = 1;
1183pub const PADS_BANK0_GPIO0_OFFSET: u32 = 4;
1184pub const PADS_BANK0_GPIO0_BITS: u32 = 255;
1185pub const PADS_BANK0_GPIO0_RESET: u32 = 86;
1186pub const PADS_BANK0_GPIO0_OD_RESET: u32 = 0;
1187pub const PADS_BANK0_GPIO0_OD_BITS: u32 = 128;
1188pub const PADS_BANK0_GPIO0_OD_MSB: u32 = 7;
1189pub const PADS_BANK0_GPIO0_OD_LSB: u32 = 7;
1190pub const PADS_BANK0_GPIO0_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1191pub const PADS_BANK0_GPIO0_IE_RESET: u32 = 1;
1192pub const PADS_BANK0_GPIO0_IE_BITS: u32 = 64;
1193pub const PADS_BANK0_GPIO0_IE_MSB: u32 = 6;
1194pub const PADS_BANK0_GPIO0_IE_LSB: u32 = 6;
1195pub const PADS_BANK0_GPIO0_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1196pub const PADS_BANK0_GPIO0_DRIVE_RESET: u32 = 1;
1197pub const PADS_BANK0_GPIO0_DRIVE_BITS: u32 = 48;
1198pub const PADS_BANK0_GPIO0_DRIVE_MSB: u32 = 5;
1199pub const PADS_BANK0_GPIO0_DRIVE_LSB: u32 = 4;
1200pub const PADS_BANK0_GPIO0_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1201pub const PADS_BANK0_GPIO0_DRIVE_VALUE_2MA: u32 = 0;
1202pub const PADS_BANK0_GPIO0_DRIVE_VALUE_4MA: u32 = 1;
1203pub const PADS_BANK0_GPIO0_DRIVE_VALUE_8MA: u32 = 2;
1204pub const PADS_BANK0_GPIO0_DRIVE_VALUE_12MA: u32 = 3;
1205pub const PADS_BANK0_GPIO0_PUE_RESET: u32 = 0;
1206pub const PADS_BANK0_GPIO0_PUE_BITS: u32 = 8;
1207pub const PADS_BANK0_GPIO0_PUE_MSB: u32 = 3;
1208pub const PADS_BANK0_GPIO0_PUE_LSB: u32 = 3;
1209pub const PADS_BANK0_GPIO0_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1210pub const PADS_BANK0_GPIO0_PDE_RESET: u32 = 1;
1211pub const PADS_BANK0_GPIO0_PDE_BITS: u32 = 4;
1212pub const PADS_BANK0_GPIO0_PDE_MSB: u32 = 2;
1213pub const PADS_BANK0_GPIO0_PDE_LSB: u32 = 2;
1214pub const PADS_BANK0_GPIO0_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1215pub const PADS_BANK0_GPIO0_SCHMITT_RESET: u32 = 1;
1216pub const PADS_BANK0_GPIO0_SCHMITT_BITS: u32 = 2;
1217pub const PADS_BANK0_GPIO0_SCHMITT_MSB: u32 = 1;
1218pub const PADS_BANK0_GPIO0_SCHMITT_LSB: u32 = 1;
1219pub const PADS_BANK0_GPIO0_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1220pub const PADS_BANK0_GPIO0_SLEWFAST_RESET: u32 = 0;
1221pub const PADS_BANK0_GPIO0_SLEWFAST_BITS: u32 = 1;
1222pub const PADS_BANK0_GPIO0_SLEWFAST_MSB: u32 = 0;
1223pub const PADS_BANK0_GPIO0_SLEWFAST_LSB: u32 = 0;
1224pub const PADS_BANK0_GPIO0_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1225pub const PADS_BANK0_GPIO1_OFFSET: u32 = 8;
1226pub const PADS_BANK0_GPIO1_BITS: u32 = 255;
1227pub const PADS_BANK0_GPIO1_RESET: u32 = 86;
1228pub const PADS_BANK0_GPIO1_OD_RESET: u32 = 0;
1229pub const PADS_BANK0_GPIO1_OD_BITS: u32 = 128;
1230pub const PADS_BANK0_GPIO1_OD_MSB: u32 = 7;
1231pub const PADS_BANK0_GPIO1_OD_LSB: u32 = 7;
1232pub const PADS_BANK0_GPIO1_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1233pub const PADS_BANK0_GPIO1_IE_RESET: u32 = 1;
1234pub const PADS_BANK0_GPIO1_IE_BITS: u32 = 64;
1235pub const PADS_BANK0_GPIO1_IE_MSB: u32 = 6;
1236pub const PADS_BANK0_GPIO1_IE_LSB: u32 = 6;
1237pub const PADS_BANK0_GPIO1_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1238pub const PADS_BANK0_GPIO1_DRIVE_RESET: u32 = 1;
1239pub const PADS_BANK0_GPIO1_DRIVE_BITS: u32 = 48;
1240pub const PADS_BANK0_GPIO1_DRIVE_MSB: u32 = 5;
1241pub const PADS_BANK0_GPIO1_DRIVE_LSB: u32 = 4;
1242pub const PADS_BANK0_GPIO1_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1243pub const PADS_BANK0_GPIO1_DRIVE_VALUE_2MA: u32 = 0;
1244pub const PADS_BANK0_GPIO1_DRIVE_VALUE_4MA: u32 = 1;
1245pub const PADS_BANK0_GPIO1_DRIVE_VALUE_8MA: u32 = 2;
1246pub const PADS_BANK0_GPIO1_DRIVE_VALUE_12MA: u32 = 3;
1247pub const PADS_BANK0_GPIO1_PUE_RESET: u32 = 0;
1248pub const PADS_BANK0_GPIO1_PUE_BITS: u32 = 8;
1249pub const PADS_BANK0_GPIO1_PUE_MSB: u32 = 3;
1250pub const PADS_BANK0_GPIO1_PUE_LSB: u32 = 3;
1251pub const PADS_BANK0_GPIO1_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1252pub const PADS_BANK0_GPIO1_PDE_RESET: u32 = 1;
1253pub const PADS_BANK0_GPIO1_PDE_BITS: u32 = 4;
1254pub const PADS_BANK0_GPIO1_PDE_MSB: u32 = 2;
1255pub const PADS_BANK0_GPIO1_PDE_LSB: u32 = 2;
1256pub const PADS_BANK0_GPIO1_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1257pub const PADS_BANK0_GPIO1_SCHMITT_RESET: u32 = 1;
1258pub const PADS_BANK0_GPIO1_SCHMITT_BITS: u32 = 2;
1259pub const PADS_BANK0_GPIO1_SCHMITT_MSB: u32 = 1;
1260pub const PADS_BANK0_GPIO1_SCHMITT_LSB: u32 = 1;
1261pub const PADS_BANK0_GPIO1_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1262pub const PADS_BANK0_GPIO1_SLEWFAST_RESET: u32 = 0;
1263pub const PADS_BANK0_GPIO1_SLEWFAST_BITS: u32 = 1;
1264pub const PADS_BANK0_GPIO1_SLEWFAST_MSB: u32 = 0;
1265pub const PADS_BANK0_GPIO1_SLEWFAST_LSB: u32 = 0;
1266pub const PADS_BANK0_GPIO1_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1267pub const PADS_BANK0_GPIO2_OFFSET: u32 = 12;
1268pub const PADS_BANK0_GPIO2_BITS: u32 = 255;
1269pub const PADS_BANK0_GPIO2_RESET: u32 = 86;
1270pub const PADS_BANK0_GPIO2_OD_RESET: u32 = 0;
1271pub const PADS_BANK0_GPIO2_OD_BITS: u32 = 128;
1272pub const PADS_BANK0_GPIO2_OD_MSB: u32 = 7;
1273pub const PADS_BANK0_GPIO2_OD_LSB: u32 = 7;
1274pub const PADS_BANK0_GPIO2_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1275pub const PADS_BANK0_GPIO2_IE_RESET: u32 = 1;
1276pub const PADS_BANK0_GPIO2_IE_BITS: u32 = 64;
1277pub const PADS_BANK0_GPIO2_IE_MSB: u32 = 6;
1278pub const PADS_BANK0_GPIO2_IE_LSB: u32 = 6;
1279pub const PADS_BANK0_GPIO2_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1280pub const PADS_BANK0_GPIO2_DRIVE_RESET: u32 = 1;
1281pub const PADS_BANK0_GPIO2_DRIVE_BITS: u32 = 48;
1282pub const PADS_BANK0_GPIO2_DRIVE_MSB: u32 = 5;
1283pub const PADS_BANK0_GPIO2_DRIVE_LSB: u32 = 4;
1284pub const PADS_BANK0_GPIO2_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1285pub const PADS_BANK0_GPIO2_DRIVE_VALUE_2MA: u32 = 0;
1286pub const PADS_BANK0_GPIO2_DRIVE_VALUE_4MA: u32 = 1;
1287pub const PADS_BANK0_GPIO2_DRIVE_VALUE_8MA: u32 = 2;
1288pub const PADS_BANK0_GPIO2_DRIVE_VALUE_12MA: u32 = 3;
1289pub const PADS_BANK0_GPIO2_PUE_RESET: u32 = 0;
1290pub const PADS_BANK0_GPIO2_PUE_BITS: u32 = 8;
1291pub const PADS_BANK0_GPIO2_PUE_MSB: u32 = 3;
1292pub const PADS_BANK0_GPIO2_PUE_LSB: u32 = 3;
1293pub const PADS_BANK0_GPIO2_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1294pub const PADS_BANK0_GPIO2_PDE_RESET: u32 = 1;
1295pub const PADS_BANK0_GPIO2_PDE_BITS: u32 = 4;
1296pub const PADS_BANK0_GPIO2_PDE_MSB: u32 = 2;
1297pub const PADS_BANK0_GPIO2_PDE_LSB: u32 = 2;
1298pub const PADS_BANK0_GPIO2_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1299pub const PADS_BANK0_GPIO2_SCHMITT_RESET: u32 = 1;
1300pub const PADS_BANK0_GPIO2_SCHMITT_BITS: u32 = 2;
1301pub const PADS_BANK0_GPIO2_SCHMITT_MSB: u32 = 1;
1302pub const PADS_BANK0_GPIO2_SCHMITT_LSB: u32 = 1;
1303pub const PADS_BANK0_GPIO2_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1304pub const PADS_BANK0_GPIO2_SLEWFAST_RESET: u32 = 0;
1305pub const PADS_BANK0_GPIO2_SLEWFAST_BITS: u32 = 1;
1306pub const PADS_BANK0_GPIO2_SLEWFAST_MSB: u32 = 0;
1307pub const PADS_BANK0_GPIO2_SLEWFAST_LSB: u32 = 0;
1308pub const PADS_BANK0_GPIO2_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1309pub const PADS_BANK0_GPIO3_OFFSET: u32 = 16;
1310pub const PADS_BANK0_GPIO3_BITS: u32 = 255;
1311pub const PADS_BANK0_GPIO3_RESET: u32 = 86;
1312pub const PADS_BANK0_GPIO3_OD_RESET: u32 = 0;
1313pub const PADS_BANK0_GPIO3_OD_BITS: u32 = 128;
1314pub const PADS_BANK0_GPIO3_OD_MSB: u32 = 7;
1315pub const PADS_BANK0_GPIO3_OD_LSB: u32 = 7;
1316pub const PADS_BANK0_GPIO3_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1317pub const PADS_BANK0_GPIO3_IE_RESET: u32 = 1;
1318pub const PADS_BANK0_GPIO3_IE_BITS: u32 = 64;
1319pub const PADS_BANK0_GPIO3_IE_MSB: u32 = 6;
1320pub const PADS_BANK0_GPIO3_IE_LSB: u32 = 6;
1321pub const PADS_BANK0_GPIO3_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1322pub const PADS_BANK0_GPIO3_DRIVE_RESET: u32 = 1;
1323pub const PADS_BANK0_GPIO3_DRIVE_BITS: u32 = 48;
1324pub const PADS_BANK0_GPIO3_DRIVE_MSB: u32 = 5;
1325pub const PADS_BANK0_GPIO3_DRIVE_LSB: u32 = 4;
1326pub const PADS_BANK0_GPIO3_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1327pub const PADS_BANK0_GPIO3_DRIVE_VALUE_2MA: u32 = 0;
1328pub const PADS_BANK0_GPIO3_DRIVE_VALUE_4MA: u32 = 1;
1329pub const PADS_BANK0_GPIO3_DRIVE_VALUE_8MA: u32 = 2;
1330pub const PADS_BANK0_GPIO3_DRIVE_VALUE_12MA: u32 = 3;
1331pub const PADS_BANK0_GPIO3_PUE_RESET: u32 = 0;
1332pub const PADS_BANK0_GPIO3_PUE_BITS: u32 = 8;
1333pub const PADS_BANK0_GPIO3_PUE_MSB: u32 = 3;
1334pub const PADS_BANK0_GPIO3_PUE_LSB: u32 = 3;
1335pub const PADS_BANK0_GPIO3_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1336pub const PADS_BANK0_GPIO3_PDE_RESET: u32 = 1;
1337pub const PADS_BANK0_GPIO3_PDE_BITS: u32 = 4;
1338pub const PADS_BANK0_GPIO3_PDE_MSB: u32 = 2;
1339pub const PADS_BANK0_GPIO3_PDE_LSB: u32 = 2;
1340pub const PADS_BANK0_GPIO3_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1341pub const PADS_BANK0_GPIO3_SCHMITT_RESET: u32 = 1;
1342pub const PADS_BANK0_GPIO3_SCHMITT_BITS: u32 = 2;
1343pub const PADS_BANK0_GPIO3_SCHMITT_MSB: u32 = 1;
1344pub const PADS_BANK0_GPIO3_SCHMITT_LSB: u32 = 1;
1345pub const PADS_BANK0_GPIO3_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1346pub const PADS_BANK0_GPIO3_SLEWFAST_RESET: u32 = 0;
1347pub const PADS_BANK0_GPIO3_SLEWFAST_BITS: u32 = 1;
1348pub const PADS_BANK0_GPIO3_SLEWFAST_MSB: u32 = 0;
1349pub const PADS_BANK0_GPIO3_SLEWFAST_LSB: u32 = 0;
1350pub const PADS_BANK0_GPIO3_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1351pub const PADS_BANK0_GPIO4_OFFSET: u32 = 20;
1352pub const PADS_BANK0_GPIO4_BITS: u32 = 255;
1353pub const PADS_BANK0_GPIO4_RESET: u32 = 86;
1354pub const PADS_BANK0_GPIO4_OD_RESET: u32 = 0;
1355pub const PADS_BANK0_GPIO4_OD_BITS: u32 = 128;
1356pub const PADS_BANK0_GPIO4_OD_MSB: u32 = 7;
1357pub const PADS_BANK0_GPIO4_OD_LSB: u32 = 7;
1358pub const PADS_BANK0_GPIO4_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1359pub const PADS_BANK0_GPIO4_IE_RESET: u32 = 1;
1360pub const PADS_BANK0_GPIO4_IE_BITS: u32 = 64;
1361pub const PADS_BANK0_GPIO4_IE_MSB: u32 = 6;
1362pub const PADS_BANK0_GPIO4_IE_LSB: u32 = 6;
1363pub const PADS_BANK0_GPIO4_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1364pub const PADS_BANK0_GPIO4_DRIVE_RESET: u32 = 1;
1365pub const PADS_BANK0_GPIO4_DRIVE_BITS: u32 = 48;
1366pub const PADS_BANK0_GPIO4_DRIVE_MSB: u32 = 5;
1367pub const PADS_BANK0_GPIO4_DRIVE_LSB: u32 = 4;
1368pub const PADS_BANK0_GPIO4_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1369pub const PADS_BANK0_GPIO4_DRIVE_VALUE_2MA: u32 = 0;
1370pub const PADS_BANK0_GPIO4_DRIVE_VALUE_4MA: u32 = 1;
1371pub const PADS_BANK0_GPIO4_DRIVE_VALUE_8MA: u32 = 2;
1372pub const PADS_BANK0_GPIO4_DRIVE_VALUE_12MA: u32 = 3;
1373pub const PADS_BANK0_GPIO4_PUE_RESET: u32 = 0;
1374pub const PADS_BANK0_GPIO4_PUE_BITS: u32 = 8;
1375pub const PADS_BANK0_GPIO4_PUE_MSB: u32 = 3;
1376pub const PADS_BANK0_GPIO4_PUE_LSB: u32 = 3;
1377pub const PADS_BANK0_GPIO4_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1378pub const PADS_BANK0_GPIO4_PDE_RESET: u32 = 1;
1379pub const PADS_BANK0_GPIO4_PDE_BITS: u32 = 4;
1380pub const PADS_BANK0_GPIO4_PDE_MSB: u32 = 2;
1381pub const PADS_BANK0_GPIO4_PDE_LSB: u32 = 2;
1382pub const PADS_BANK0_GPIO4_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1383pub const PADS_BANK0_GPIO4_SCHMITT_RESET: u32 = 1;
1384pub const PADS_BANK0_GPIO4_SCHMITT_BITS: u32 = 2;
1385pub const PADS_BANK0_GPIO4_SCHMITT_MSB: u32 = 1;
1386pub const PADS_BANK0_GPIO4_SCHMITT_LSB: u32 = 1;
1387pub const PADS_BANK0_GPIO4_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1388pub const PADS_BANK0_GPIO4_SLEWFAST_RESET: u32 = 0;
1389pub const PADS_BANK0_GPIO4_SLEWFAST_BITS: u32 = 1;
1390pub const PADS_BANK0_GPIO4_SLEWFAST_MSB: u32 = 0;
1391pub const PADS_BANK0_GPIO4_SLEWFAST_LSB: u32 = 0;
1392pub const PADS_BANK0_GPIO4_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1393pub const PADS_BANK0_GPIO5_OFFSET: u32 = 24;
1394pub const PADS_BANK0_GPIO5_BITS: u32 = 255;
1395pub const PADS_BANK0_GPIO5_RESET: u32 = 86;
1396pub const PADS_BANK0_GPIO5_OD_RESET: u32 = 0;
1397pub const PADS_BANK0_GPIO5_OD_BITS: u32 = 128;
1398pub const PADS_BANK0_GPIO5_OD_MSB: u32 = 7;
1399pub const PADS_BANK0_GPIO5_OD_LSB: u32 = 7;
1400pub const PADS_BANK0_GPIO5_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1401pub const PADS_BANK0_GPIO5_IE_RESET: u32 = 1;
1402pub const PADS_BANK0_GPIO5_IE_BITS: u32 = 64;
1403pub const PADS_BANK0_GPIO5_IE_MSB: u32 = 6;
1404pub const PADS_BANK0_GPIO5_IE_LSB: u32 = 6;
1405pub const PADS_BANK0_GPIO5_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1406pub const PADS_BANK0_GPIO5_DRIVE_RESET: u32 = 1;
1407pub const PADS_BANK0_GPIO5_DRIVE_BITS: u32 = 48;
1408pub const PADS_BANK0_GPIO5_DRIVE_MSB: u32 = 5;
1409pub const PADS_BANK0_GPIO5_DRIVE_LSB: u32 = 4;
1410pub const PADS_BANK0_GPIO5_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1411pub const PADS_BANK0_GPIO5_DRIVE_VALUE_2MA: u32 = 0;
1412pub const PADS_BANK0_GPIO5_DRIVE_VALUE_4MA: u32 = 1;
1413pub const PADS_BANK0_GPIO5_DRIVE_VALUE_8MA: u32 = 2;
1414pub const PADS_BANK0_GPIO5_DRIVE_VALUE_12MA: u32 = 3;
1415pub const PADS_BANK0_GPIO5_PUE_RESET: u32 = 0;
1416pub const PADS_BANK0_GPIO5_PUE_BITS: u32 = 8;
1417pub const PADS_BANK0_GPIO5_PUE_MSB: u32 = 3;
1418pub const PADS_BANK0_GPIO5_PUE_LSB: u32 = 3;
1419pub const PADS_BANK0_GPIO5_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1420pub const PADS_BANK0_GPIO5_PDE_RESET: u32 = 1;
1421pub const PADS_BANK0_GPIO5_PDE_BITS: u32 = 4;
1422pub const PADS_BANK0_GPIO5_PDE_MSB: u32 = 2;
1423pub const PADS_BANK0_GPIO5_PDE_LSB: u32 = 2;
1424pub const PADS_BANK0_GPIO5_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1425pub const PADS_BANK0_GPIO5_SCHMITT_RESET: u32 = 1;
1426pub const PADS_BANK0_GPIO5_SCHMITT_BITS: u32 = 2;
1427pub const PADS_BANK0_GPIO5_SCHMITT_MSB: u32 = 1;
1428pub const PADS_BANK0_GPIO5_SCHMITT_LSB: u32 = 1;
1429pub const PADS_BANK0_GPIO5_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1430pub const PADS_BANK0_GPIO5_SLEWFAST_RESET: u32 = 0;
1431pub const PADS_BANK0_GPIO5_SLEWFAST_BITS: u32 = 1;
1432pub const PADS_BANK0_GPIO5_SLEWFAST_MSB: u32 = 0;
1433pub const PADS_BANK0_GPIO5_SLEWFAST_LSB: u32 = 0;
1434pub const PADS_BANK0_GPIO5_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1435pub const PADS_BANK0_GPIO6_OFFSET: u32 = 28;
1436pub const PADS_BANK0_GPIO6_BITS: u32 = 255;
1437pub const PADS_BANK0_GPIO6_RESET: u32 = 86;
1438pub const PADS_BANK0_GPIO6_OD_RESET: u32 = 0;
1439pub const PADS_BANK0_GPIO6_OD_BITS: u32 = 128;
1440pub const PADS_BANK0_GPIO6_OD_MSB: u32 = 7;
1441pub const PADS_BANK0_GPIO6_OD_LSB: u32 = 7;
1442pub const PADS_BANK0_GPIO6_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1443pub const PADS_BANK0_GPIO6_IE_RESET: u32 = 1;
1444pub const PADS_BANK0_GPIO6_IE_BITS: u32 = 64;
1445pub const PADS_BANK0_GPIO6_IE_MSB: u32 = 6;
1446pub const PADS_BANK0_GPIO6_IE_LSB: u32 = 6;
1447pub const PADS_BANK0_GPIO6_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1448pub const PADS_BANK0_GPIO6_DRIVE_RESET: u32 = 1;
1449pub const PADS_BANK0_GPIO6_DRIVE_BITS: u32 = 48;
1450pub const PADS_BANK0_GPIO6_DRIVE_MSB: u32 = 5;
1451pub const PADS_BANK0_GPIO6_DRIVE_LSB: u32 = 4;
1452pub const PADS_BANK0_GPIO6_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1453pub const PADS_BANK0_GPIO6_DRIVE_VALUE_2MA: u32 = 0;
1454pub const PADS_BANK0_GPIO6_DRIVE_VALUE_4MA: u32 = 1;
1455pub const PADS_BANK0_GPIO6_DRIVE_VALUE_8MA: u32 = 2;
1456pub const PADS_BANK0_GPIO6_DRIVE_VALUE_12MA: u32 = 3;
1457pub const PADS_BANK0_GPIO6_PUE_RESET: u32 = 0;
1458pub const PADS_BANK0_GPIO6_PUE_BITS: u32 = 8;
1459pub const PADS_BANK0_GPIO6_PUE_MSB: u32 = 3;
1460pub const PADS_BANK0_GPIO6_PUE_LSB: u32 = 3;
1461pub const PADS_BANK0_GPIO6_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1462pub const PADS_BANK0_GPIO6_PDE_RESET: u32 = 1;
1463pub const PADS_BANK0_GPIO6_PDE_BITS: u32 = 4;
1464pub const PADS_BANK0_GPIO6_PDE_MSB: u32 = 2;
1465pub const PADS_BANK0_GPIO6_PDE_LSB: u32 = 2;
1466pub const PADS_BANK0_GPIO6_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1467pub const PADS_BANK0_GPIO6_SCHMITT_RESET: u32 = 1;
1468pub const PADS_BANK0_GPIO6_SCHMITT_BITS: u32 = 2;
1469pub const PADS_BANK0_GPIO6_SCHMITT_MSB: u32 = 1;
1470pub const PADS_BANK0_GPIO6_SCHMITT_LSB: u32 = 1;
1471pub const PADS_BANK0_GPIO6_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1472pub const PADS_BANK0_GPIO6_SLEWFAST_RESET: u32 = 0;
1473pub const PADS_BANK0_GPIO6_SLEWFAST_BITS: u32 = 1;
1474pub const PADS_BANK0_GPIO6_SLEWFAST_MSB: u32 = 0;
1475pub const PADS_BANK0_GPIO6_SLEWFAST_LSB: u32 = 0;
1476pub const PADS_BANK0_GPIO6_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1477pub const PADS_BANK0_GPIO7_OFFSET: u32 = 32;
1478pub const PADS_BANK0_GPIO7_BITS: u32 = 255;
1479pub const PADS_BANK0_GPIO7_RESET: u32 = 86;
1480pub const PADS_BANK0_GPIO7_OD_RESET: u32 = 0;
1481pub const PADS_BANK0_GPIO7_OD_BITS: u32 = 128;
1482pub const PADS_BANK0_GPIO7_OD_MSB: u32 = 7;
1483pub const PADS_BANK0_GPIO7_OD_LSB: u32 = 7;
1484pub const PADS_BANK0_GPIO7_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1485pub const PADS_BANK0_GPIO7_IE_RESET: u32 = 1;
1486pub const PADS_BANK0_GPIO7_IE_BITS: u32 = 64;
1487pub const PADS_BANK0_GPIO7_IE_MSB: u32 = 6;
1488pub const PADS_BANK0_GPIO7_IE_LSB: u32 = 6;
1489pub const PADS_BANK0_GPIO7_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1490pub const PADS_BANK0_GPIO7_DRIVE_RESET: u32 = 1;
1491pub const PADS_BANK0_GPIO7_DRIVE_BITS: u32 = 48;
1492pub const PADS_BANK0_GPIO7_DRIVE_MSB: u32 = 5;
1493pub const PADS_BANK0_GPIO7_DRIVE_LSB: u32 = 4;
1494pub const PADS_BANK0_GPIO7_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1495pub const PADS_BANK0_GPIO7_DRIVE_VALUE_2MA: u32 = 0;
1496pub const PADS_BANK0_GPIO7_DRIVE_VALUE_4MA: u32 = 1;
1497pub const PADS_BANK0_GPIO7_DRIVE_VALUE_8MA: u32 = 2;
1498pub const PADS_BANK0_GPIO7_DRIVE_VALUE_12MA: u32 = 3;
1499pub const PADS_BANK0_GPIO7_PUE_RESET: u32 = 0;
1500pub const PADS_BANK0_GPIO7_PUE_BITS: u32 = 8;
1501pub const PADS_BANK0_GPIO7_PUE_MSB: u32 = 3;
1502pub const PADS_BANK0_GPIO7_PUE_LSB: u32 = 3;
1503pub const PADS_BANK0_GPIO7_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1504pub const PADS_BANK0_GPIO7_PDE_RESET: u32 = 1;
1505pub const PADS_BANK0_GPIO7_PDE_BITS: u32 = 4;
1506pub const PADS_BANK0_GPIO7_PDE_MSB: u32 = 2;
1507pub const PADS_BANK0_GPIO7_PDE_LSB: u32 = 2;
1508pub const PADS_BANK0_GPIO7_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1509pub const PADS_BANK0_GPIO7_SCHMITT_RESET: u32 = 1;
1510pub const PADS_BANK0_GPIO7_SCHMITT_BITS: u32 = 2;
1511pub const PADS_BANK0_GPIO7_SCHMITT_MSB: u32 = 1;
1512pub const PADS_BANK0_GPIO7_SCHMITT_LSB: u32 = 1;
1513pub const PADS_BANK0_GPIO7_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1514pub const PADS_BANK0_GPIO7_SLEWFAST_RESET: u32 = 0;
1515pub const PADS_BANK0_GPIO7_SLEWFAST_BITS: u32 = 1;
1516pub const PADS_BANK0_GPIO7_SLEWFAST_MSB: u32 = 0;
1517pub const PADS_BANK0_GPIO7_SLEWFAST_LSB: u32 = 0;
1518pub const PADS_BANK0_GPIO7_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1519pub const PADS_BANK0_GPIO8_OFFSET: u32 = 36;
1520pub const PADS_BANK0_GPIO8_BITS: u32 = 255;
1521pub const PADS_BANK0_GPIO8_RESET: u32 = 86;
1522pub const PADS_BANK0_GPIO8_OD_RESET: u32 = 0;
1523pub const PADS_BANK0_GPIO8_OD_BITS: u32 = 128;
1524pub const PADS_BANK0_GPIO8_OD_MSB: u32 = 7;
1525pub const PADS_BANK0_GPIO8_OD_LSB: u32 = 7;
1526pub const PADS_BANK0_GPIO8_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1527pub const PADS_BANK0_GPIO8_IE_RESET: u32 = 1;
1528pub const PADS_BANK0_GPIO8_IE_BITS: u32 = 64;
1529pub const PADS_BANK0_GPIO8_IE_MSB: u32 = 6;
1530pub const PADS_BANK0_GPIO8_IE_LSB: u32 = 6;
1531pub const PADS_BANK0_GPIO8_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1532pub const PADS_BANK0_GPIO8_DRIVE_RESET: u32 = 1;
1533pub const PADS_BANK0_GPIO8_DRIVE_BITS: u32 = 48;
1534pub const PADS_BANK0_GPIO8_DRIVE_MSB: u32 = 5;
1535pub const PADS_BANK0_GPIO8_DRIVE_LSB: u32 = 4;
1536pub const PADS_BANK0_GPIO8_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1537pub const PADS_BANK0_GPIO8_DRIVE_VALUE_2MA: u32 = 0;
1538pub const PADS_BANK0_GPIO8_DRIVE_VALUE_4MA: u32 = 1;
1539pub const PADS_BANK0_GPIO8_DRIVE_VALUE_8MA: u32 = 2;
1540pub const PADS_BANK0_GPIO8_DRIVE_VALUE_12MA: u32 = 3;
1541pub const PADS_BANK0_GPIO8_PUE_RESET: u32 = 0;
1542pub const PADS_BANK0_GPIO8_PUE_BITS: u32 = 8;
1543pub const PADS_BANK0_GPIO8_PUE_MSB: u32 = 3;
1544pub const PADS_BANK0_GPIO8_PUE_LSB: u32 = 3;
1545pub const PADS_BANK0_GPIO8_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1546pub const PADS_BANK0_GPIO8_PDE_RESET: u32 = 1;
1547pub const PADS_BANK0_GPIO8_PDE_BITS: u32 = 4;
1548pub const PADS_BANK0_GPIO8_PDE_MSB: u32 = 2;
1549pub const PADS_BANK0_GPIO8_PDE_LSB: u32 = 2;
1550pub const PADS_BANK0_GPIO8_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1551pub const PADS_BANK0_GPIO8_SCHMITT_RESET: u32 = 1;
1552pub const PADS_BANK0_GPIO8_SCHMITT_BITS: u32 = 2;
1553pub const PADS_BANK0_GPIO8_SCHMITT_MSB: u32 = 1;
1554pub const PADS_BANK0_GPIO8_SCHMITT_LSB: u32 = 1;
1555pub const PADS_BANK0_GPIO8_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1556pub const PADS_BANK0_GPIO8_SLEWFAST_RESET: u32 = 0;
1557pub const PADS_BANK0_GPIO8_SLEWFAST_BITS: u32 = 1;
1558pub const PADS_BANK0_GPIO8_SLEWFAST_MSB: u32 = 0;
1559pub const PADS_BANK0_GPIO8_SLEWFAST_LSB: u32 = 0;
1560pub const PADS_BANK0_GPIO8_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1561pub const PADS_BANK0_GPIO9_OFFSET: u32 = 40;
1562pub const PADS_BANK0_GPIO9_BITS: u32 = 255;
1563pub const PADS_BANK0_GPIO9_RESET: u32 = 86;
1564pub const PADS_BANK0_GPIO9_OD_RESET: u32 = 0;
1565pub const PADS_BANK0_GPIO9_OD_BITS: u32 = 128;
1566pub const PADS_BANK0_GPIO9_OD_MSB: u32 = 7;
1567pub const PADS_BANK0_GPIO9_OD_LSB: u32 = 7;
1568pub const PADS_BANK0_GPIO9_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1569pub const PADS_BANK0_GPIO9_IE_RESET: u32 = 1;
1570pub const PADS_BANK0_GPIO9_IE_BITS: u32 = 64;
1571pub const PADS_BANK0_GPIO9_IE_MSB: u32 = 6;
1572pub const PADS_BANK0_GPIO9_IE_LSB: u32 = 6;
1573pub const PADS_BANK0_GPIO9_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1574pub const PADS_BANK0_GPIO9_DRIVE_RESET: u32 = 1;
1575pub const PADS_BANK0_GPIO9_DRIVE_BITS: u32 = 48;
1576pub const PADS_BANK0_GPIO9_DRIVE_MSB: u32 = 5;
1577pub const PADS_BANK0_GPIO9_DRIVE_LSB: u32 = 4;
1578pub const PADS_BANK0_GPIO9_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1579pub const PADS_BANK0_GPIO9_DRIVE_VALUE_2MA: u32 = 0;
1580pub const PADS_BANK0_GPIO9_DRIVE_VALUE_4MA: u32 = 1;
1581pub const PADS_BANK0_GPIO9_DRIVE_VALUE_8MA: u32 = 2;
1582pub const PADS_BANK0_GPIO9_DRIVE_VALUE_12MA: u32 = 3;
1583pub const PADS_BANK0_GPIO9_PUE_RESET: u32 = 0;
1584pub const PADS_BANK0_GPIO9_PUE_BITS: u32 = 8;
1585pub const PADS_BANK0_GPIO9_PUE_MSB: u32 = 3;
1586pub const PADS_BANK0_GPIO9_PUE_LSB: u32 = 3;
1587pub const PADS_BANK0_GPIO9_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1588pub const PADS_BANK0_GPIO9_PDE_RESET: u32 = 1;
1589pub const PADS_BANK0_GPIO9_PDE_BITS: u32 = 4;
1590pub const PADS_BANK0_GPIO9_PDE_MSB: u32 = 2;
1591pub const PADS_BANK0_GPIO9_PDE_LSB: u32 = 2;
1592pub const PADS_BANK0_GPIO9_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1593pub const PADS_BANK0_GPIO9_SCHMITT_RESET: u32 = 1;
1594pub const PADS_BANK0_GPIO9_SCHMITT_BITS: u32 = 2;
1595pub const PADS_BANK0_GPIO9_SCHMITT_MSB: u32 = 1;
1596pub const PADS_BANK0_GPIO9_SCHMITT_LSB: u32 = 1;
1597pub const PADS_BANK0_GPIO9_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1598pub const PADS_BANK0_GPIO9_SLEWFAST_RESET: u32 = 0;
1599pub const PADS_BANK0_GPIO9_SLEWFAST_BITS: u32 = 1;
1600pub const PADS_BANK0_GPIO9_SLEWFAST_MSB: u32 = 0;
1601pub const PADS_BANK0_GPIO9_SLEWFAST_LSB: u32 = 0;
1602pub const PADS_BANK0_GPIO9_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1603pub const PADS_BANK0_GPIO10_OFFSET: u32 = 44;
1604pub const PADS_BANK0_GPIO10_BITS: u32 = 255;
1605pub const PADS_BANK0_GPIO10_RESET: u32 = 86;
1606pub const PADS_BANK0_GPIO10_OD_RESET: u32 = 0;
1607pub const PADS_BANK0_GPIO10_OD_BITS: u32 = 128;
1608pub const PADS_BANK0_GPIO10_OD_MSB: u32 = 7;
1609pub const PADS_BANK0_GPIO10_OD_LSB: u32 = 7;
1610pub const PADS_BANK0_GPIO10_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1611pub const PADS_BANK0_GPIO10_IE_RESET: u32 = 1;
1612pub const PADS_BANK0_GPIO10_IE_BITS: u32 = 64;
1613pub const PADS_BANK0_GPIO10_IE_MSB: u32 = 6;
1614pub const PADS_BANK0_GPIO10_IE_LSB: u32 = 6;
1615pub const PADS_BANK0_GPIO10_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1616pub const PADS_BANK0_GPIO10_DRIVE_RESET: u32 = 1;
1617pub const PADS_BANK0_GPIO10_DRIVE_BITS: u32 = 48;
1618pub const PADS_BANK0_GPIO10_DRIVE_MSB: u32 = 5;
1619pub const PADS_BANK0_GPIO10_DRIVE_LSB: u32 = 4;
1620pub const PADS_BANK0_GPIO10_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1621pub const PADS_BANK0_GPIO10_DRIVE_VALUE_2MA: u32 = 0;
1622pub const PADS_BANK0_GPIO10_DRIVE_VALUE_4MA: u32 = 1;
1623pub const PADS_BANK0_GPIO10_DRIVE_VALUE_8MA: u32 = 2;
1624pub const PADS_BANK0_GPIO10_DRIVE_VALUE_12MA: u32 = 3;
1625pub const PADS_BANK0_GPIO10_PUE_RESET: u32 = 0;
1626pub const PADS_BANK0_GPIO10_PUE_BITS: u32 = 8;
1627pub const PADS_BANK0_GPIO10_PUE_MSB: u32 = 3;
1628pub const PADS_BANK0_GPIO10_PUE_LSB: u32 = 3;
1629pub const PADS_BANK0_GPIO10_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1630pub const PADS_BANK0_GPIO10_PDE_RESET: u32 = 1;
1631pub const PADS_BANK0_GPIO10_PDE_BITS: u32 = 4;
1632pub const PADS_BANK0_GPIO10_PDE_MSB: u32 = 2;
1633pub const PADS_BANK0_GPIO10_PDE_LSB: u32 = 2;
1634pub const PADS_BANK0_GPIO10_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1635pub const PADS_BANK0_GPIO10_SCHMITT_RESET: u32 = 1;
1636pub const PADS_BANK0_GPIO10_SCHMITT_BITS: u32 = 2;
1637pub const PADS_BANK0_GPIO10_SCHMITT_MSB: u32 = 1;
1638pub const PADS_BANK0_GPIO10_SCHMITT_LSB: u32 = 1;
1639pub const PADS_BANK0_GPIO10_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1640pub const PADS_BANK0_GPIO10_SLEWFAST_RESET: u32 = 0;
1641pub const PADS_BANK0_GPIO10_SLEWFAST_BITS: u32 = 1;
1642pub const PADS_BANK0_GPIO10_SLEWFAST_MSB: u32 = 0;
1643pub const PADS_BANK0_GPIO10_SLEWFAST_LSB: u32 = 0;
1644pub const PADS_BANK0_GPIO10_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1645pub const PADS_BANK0_GPIO11_OFFSET: u32 = 48;
1646pub const PADS_BANK0_GPIO11_BITS: u32 = 255;
1647pub const PADS_BANK0_GPIO11_RESET: u32 = 86;
1648pub const PADS_BANK0_GPIO11_OD_RESET: u32 = 0;
1649pub const PADS_BANK0_GPIO11_OD_BITS: u32 = 128;
1650pub const PADS_BANK0_GPIO11_OD_MSB: u32 = 7;
1651pub const PADS_BANK0_GPIO11_OD_LSB: u32 = 7;
1652pub const PADS_BANK0_GPIO11_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1653pub const PADS_BANK0_GPIO11_IE_RESET: u32 = 1;
1654pub const PADS_BANK0_GPIO11_IE_BITS: u32 = 64;
1655pub const PADS_BANK0_GPIO11_IE_MSB: u32 = 6;
1656pub const PADS_BANK0_GPIO11_IE_LSB: u32 = 6;
1657pub const PADS_BANK0_GPIO11_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1658pub const PADS_BANK0_GPIO11_DRIVE_RESET: u32 = 1;
1659pub const PADS_BANK0_GPIO11_DRIVE_BITS: u32 = 48;
1660pub const PADS_BANK0_GPIO11_DRIVE_MSB: u32 = 5;
1661pub const PADS_BANK0_GPIO11_DRIVE_LSB: u32 = 4;
1662pub const PADS_BANK0_GPIO11_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1663pub const PADS_BANK0_GPIO11_DRIVE_VALUE_2MA: u32 = 0;
1664pub const PADS_BANK0_GPIO11_DRIVE_VALUE_4MA: u32 = 1;
1665pub const PADS_BANK0_GPIO11_DRIVE_VALUE_8MA: u32 = 2;
1666pub const PADS_BANK0_GPIO11_DRIVE_VALUE_12MA: u32 = 3;
1667pub const PADS_BANK0_GPIO11_PUE_RESET: u32 = 0;
1668pub const PADS_BANK0_GPIO11_PUE_BITS: u32 = 8;
1669pub const PADS_BANK0_GPIO11_PUE_MSB: u32 = 3;
1670pub const PADS_BANK0_GPIO11_PUE_LSB: u32 = 3;
1671pub const PADS_BANK0_GPIO11_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1672pub const PADS_BANK0_GPIO11_PDE_RESET: u32 = 1;
1673pub const PADS_BANK0_GPIO11_PDE_BITS: u32 = 4;
1674pub const PADS_BANK0_GPIO11_PDE_MSB: u32 = 2;
1675pub const PADS_BANK0_GPIO11_PDE_LSB: u32 = 2;
1676pub const PADS_BANK0_GPIO11_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1677pub const PADS_BANK0_GPIO11_SCHMITT_RESET: u32 = 1;
1678pub const PADS_BANK0_GPIO11_SCHMITT_BITS: u32 = 2;
1679pub const PADS_BANK0_GPIO11_SCHMITT_MSB: u32 = 1;
1680pub const PADS_BANK0_GPIO11_SCHMITT_LSB: u32 = 1;
1681pub const PADS_BANK0_GPIO11_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1682pub const PADS_BANK0_GPIO11_SLEWFAST_RESET: u32 = 0;
1683pub const PADS_BANK0_GPIO11_SLEWFAST_BITS: u32 = 1;
1684pub const PADS_BANK0_GPIO11_SLEWFAST_MSB: u32 = 0;
1685pub const PADS_BANK0_GPIO11_SLEWFAST_LSB: u32 = 0;
1686pub const PADS_BANK0_GPIO11_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1687pub const PADS_BANK0_GPIO12_OFFSET: u32 = 52;
1688pub const PADS_BANK0_GPIO12_BITS: u32 = 255;
1689pub const PADS_BANK0_GPIO12_RESET: u32 = 86;
1690pub const PADS_BANK0_GPIO12_OD_RESET: u32 = 0;
1691pub const PADS_BANK0_GPIO12_OD_BITS: u32 = 128;
1692pub const PADS_BANK0_GPIO12_OD_MSB: u32 = 7;
1693pub const PADS_BANK0_GPIO12_OD_LSB: u32 = 7;
1694pub const PADS_BANK0_GPIO12_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1695pub const PADS_BANK0_GPIO12_IE_RESET: u32 = 1;
1696pub const PADS_BANK0_GPIO12_IE_BITS: u32 = 64;
1697pub const PADS_BANK0_GPIO12_IE_MSB: u32 = 6;
1698pub const PADS_BANK0_GPIO12_IE_LSB: u32 = 6;
1699pub const PADS_BANK0_GPIO12_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1700pub const PADS_BANK0_GPIO12_DRIVE_RESET: u32 = 1;
1701pub const PADS_BANK0_GPIO12_DRIVE_BITS: u32 = 48;
1702pub const PADS_BANK0_GPIO12_DRIVE_MSB: u32 = 5;
1703pub const PADS_BANK0_GPIO12_DRIVE_LSB: u32 = 4;
1704pub const PADS_BANK0_GPIO12_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1705pub const PADS_BANK0_GPIO12_DRIVE_VALUE_2MA: u32 = 0;
1706pub const PADS_BANK0_GPIO12_DRIVE_VALUE_4MA: u32 = 1;
1707pub const PADS_BANK0_GPIO12_DRIVE_VALUE_8MA: u32 = 2;
1708pub const PADS_BANK0_GPIO12_DRIVE_VALUE_12MA: u32 = 3;
1709pub const PADS_BANK0_GPIO12_PUE_RESET: u32 = 0;
1710pub const PADS_BANK0_GPIO12_PUE_BITS: u32 = 8;
1711pub const PADS_BANK0_GPIO12_PUE_MSB: u32 = 3;
1712pub const PADS_BANK0_GPIO12_PUE_LSB: u32 = 3;
1713pub const PADS_BANK0_GPIO12_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1714pub const PADS_BANK0_GPIO12_PDE_RESET: u32 = 1;
1715pub const PADS_BANK0_GPIO12_PDE_BITS: u32 = 4;
1716pub const PADS_BANK0_GPIO12_PDE_MSB: u32 = 2;
1717pub const PADS_BANK0_GPIO12_PDE_LSB: u32 = 2;
1718pub const PADS_BANK0_GPIO12_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1719pub const PADS_BANK0_GPIO12_SCHMITT_RESET: u32 = 1;
1720pub const PADS_BANK0_GPIO12_SCHMITT_BITS: u32 = 2;
1721pub const PADS_BANK0_GPIO12_SCHMITT_MSB: u32 = 1;
1722pub const PADS_BANK0_GPIO12_SCHMITT_LSB: u32 = 1;
1723pub const PADS_BANK0_GPIO12_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1724pub const PADS_BANK0_GPIO12_SLEWFAST_RESET: u32 = 0;
1725pub const PADS_BANK0_GPIO12_SLEWFAST_BITS: u32 = 1;
1726pub const PADS_BANK0_GPIO12_SLEWFAST_MSB: u32 = 0;
1727pub const PADS_BANK0_GPIO12_SLEWFAST_LSB: u32 = 0;
1728pub const PADS_BANK0_GPIO12_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1729pub const PADS_BANK0_GPIO13_OFFSET: u32 = 56;
1730pub const PADS_BANK0_GPIO13_BITS: u32 = 255;
1731pub const PADS_BANK0_GPIO13_RESET: u32 = 86;
1732pub const PADS_BANK0_GPIO13_OD_RESET: u32 = 0;
1733pub const PADS_BANK0_GPIO13_OD_BITS: u32 = 128;
1734pub const PADS_BANK0_GPIO13_OD_MSB: u32 = 7;
1735pub const PADS_BANK0_GPIO13_OD_LSB: u32 = 7;
1736pub const PADS_BANK0_GPIO13_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1737pub const PADS_BANK0_GPIO13_IE_RESET: u32 = 1;
1738pub const PADS_BANK0_GPIO13_IE_BITS: u32 = 64;
1739pub const PADS_BANK0_GPIO13_IE_MSB: u32 = 6;
1740pub const PADS_BANK0_GPIO13_IE_LSB: u32 = 6;
1741pub const PADS_BANK0_GPIO13_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1742pub const PADS_BANK0_GPIO13_DRIVE_RESET: u32 = 1;
1743pub const PADS_BANK0_GPIO13_DRIVE_BITS: u32 = 48;
1744pub const PADS_BANK0_GPIO13_DRIVE_MSB: u32 = 5;
1745pub const PADS_BANK0_GPIO13_DRIVE_LSB: u32 = 4;
1746pub const PADS_BANK0_GPIO13_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1747pub const PADS_BANK0_GPIO13_DRIVE_VALUE_2MA: u32 = 0;
1748pub const PADS_BANK0_GPIO13_DRIVE_VALUE_4MA: u32 = 1;
1749pub const PADS_BANK0_GPIO13_DRIVE_VALUE_8MA: u32 = 2;
1750pub const PADS_BANK0_GPIO13_DRIVE_VALUE_12MA: u32 = 3;
1751pub const PADS_BANK0_GPIO13_PUE_RESET: u32 = 0;
1752pub const PADS_BANK0_GPIO13_PUE_BITS: u32 = 8;
1753pub const PADS_BANK0_GPIO13_PUE_MSB: u32 = 3;
1754pub const PADS_BANK0_GPIO13_PUE_LSB: u32 = 3;
1755pub const PADS_BANK0_GPIO13_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1756pub const PADS_BANK0_GPIO13_PDE_RESET: u32 = 1;
1757pub const PADS_BANK0_GPIO13_PDE_BITS: u32 = 4;
1758pub const PADS_BANK0_GPIO13_PDE_MSB: u32 = 2;
1759pub const PADS_BANK0_GPIO13_PDE_LSB: u32 = 2;
1760pub const PADS_BANK0_GPIO13_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1761pub const PADS_BANK0_GPIO13_SCHMITT_RESET: u32 = 1;
1762pub const PADS_BANK0_GPIO13_SCHMITT_BITS: u32 = 2;
1763pub const PADS_BANK0_GPIO13_SCHMITT_MSB: u32 = 1;
1764pub const PADS_BANK0_GPIO13_SCHMITT_LSB: u32 = 1;
1765pub const PADS_BANK0_GPIO13_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1766pub const PADS_BANK0_GPIO13_SLEWFAST_RESET: u32 = 0;
1767pub const PADS_BANK0_GPIO13_SLEWFAST_BITS: u32 = 1;
1768pub const PADS_BANK0_GPIO13_SLEWFAST_MSB: u32 = 0;
1769pub const PADS_BANK0_GPIO13_SLEWFAST_LSB: u32 = 0;
1770pub const PADS_BANK0_GPIO13_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1771pub const PADS_BANK0_GPIO14_OFFSET: u32 = 60;
1772pub const PADS_BANK0_GPIO14_BITS: u32 = 255;
1773pub const PADS_BANK0_GPIO14_RESET: u32 = 86;
1774pub const PADS_BANK0_GPIO14_OD_RESET: u32 = 0;
1775pub const PADS_BANK0_GPIO14_OD_BITS: u32 = 128;
1776pub const PADS_BANK0_GPIO14_OD_MSB: u32 = 7;
1777pub const PADS_BANK0_GPIO14_OD_LSB: u32 = 7;
1778pub const PADS_BANK0_GPIO14_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1779pub const PADS_BANK0_GPIO14_IE_RESET: u32 = 1;
1780pub const PADS_BANK0_GPIO14_IE_BITS: u32 = 64;
1781pub const PADS_BANK0_GPIO14_IE_MSB: u32 = 6;
1782pub const PADS_BANK0_GPIO14_IE_LSB: u32 = 6;
1783pub const PADS_BANK0_GPIO14_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1784pub const PADS_BANK0_GPIO14_DRIVE_RESET: u32 = 1;
1785pub const PADS_BANK0_GPIO14_DRIVE_BITS: u32 = 48;
1786pub const PADS_BANK0_GPIO14_DRIVE_MSB: u32 = 5;
1787pub const PADS_BANK0_GPIO14_DRIVE_LSB: u32 = 4;
1788pub const PADS_BANK0_GPIO14_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1789pub const PADS_BANK0_GPIO14_DRIVE_VALUE_2MA: u32 = 0;
1790pub const PADS_BANK0_GPIO14_DRIVE_VALUE_4MA: u32 = 1;
1791pub const PADS_BANK0_GPIO14_DRIVE_VALUE_8MA: u32 = 2;
1792pub const PADS_BANK0_GPIO14_DRIVE_VALUE_12MA: u32 = 3;
1793pub const PADS_BANK0_GPIO14_PUE_RESET: u32 = 0;
1794pub const PADS_BANK0_GPIO14_PUE_BITS: u32 = 8;
1795pub const PADS_BANK0_GPIO14_PUE_MSB: u32 = 3;
1796pub const PADS_BANK0_GPIO14_PUE_LSB: u32 = 3;
1797pub const PADS_BANK0_GPIO14_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1798pub const PADS_BANK0_GPIO14_PDE_RESET: u32 = 1;
1799pub const PADS_BANK0_GPIO14_PDE_BITS: u32 = 4;
1800pub const PADS_BANK0_GPIO14_PDE_MSB: u32 = 2;
1801pub const PADS_BANK0_GPIO14_PDE_LSB: u32 = 2;
1802pub const PADS_BANK0_GPIO14_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1803pub const PADS_BANK0_GPIO14_SCHMITT_RESET: u32 = 1;
1804pub const PADS_BANK0_GPIO14_SCHMITT_BITS: u32 = 2;
1805pub const PADS_BANK0_GPIO14_SCHMITT_MSB: u32 = 1;
1806pub const PADS_BANK0_GPIO14_SCHMITT_LSB: u32 = 1;
1807pub const PADS_BANK0_GPIO14_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1808pub const PADS_BANK0_GPIO14_SLEWFAST_RESET: u32 = 0;
1809pub const PADS_BANK0_GPIO14_SLEWFAST_BITS: u32 = 1;
1810pub const PADS_BANK0_GPIO14_SLEWFAST_MSB: u32 = 0;
1811pub const PADS_BANK0_GPIO14_SLEWFAST_LSB: u32 = 0;
1812pub const PADS_BANK0_GPIO14_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1813pub const PADS_BANK0_GPIO15_OFFSET: u32 = 64;
1814pub const PADS_BANK0_GPIO15_BITS: u32 = 255;
1815pub const PADS_BANK0_GPIO15_RESET: u32 = 86;
1816pub const PADS_BANK0_GPIO15_OD_RESET: u32 = 0;
1817pub const PADS_BANK0_GPIO15_OD_BITS: u32 = 128;
1818pub const PADS_BANK0_GPIO15_OD_MSB: u32 = 7;
1819pub const PADS_BANK0_GPIO15_OD_LSB: u32 = 7;
1820pub const PADS_BANK0_GPIO15_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1821pub const PADS_BANK0_GPIO15_IE_RESET: u32 = 1;
1822pub const PADS_BANK0_GPIO15_IE_BITS: u32 = 64;
1823pub const PADS_BANK0_GPIO15_IE_MSB: u32 = 6;
1824pub const PADS_BANK0_GPIO15_IE_LSB: u32 = 6;
1825pub const PADS_BANK0_GPIO15_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1826pub const PADS_BANK0_GPIO15_DRIVE_RESET: u32 = 1;
1827pub const PADS_BANK0_GPIO15_DRIVE_BITS: u32 = 48;
1828pub const PADS_BANK0_GPIO15_DRIVE_MSB: u32 = 5;
1829pub const PADS_BANK0_GPIO15_DRIVE_LSB: u32 = 4;
1830pub const PADS_BANK0_GPIO15_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1831pub const PADS_BANK0_GPIO15_DRIVE_VALUE_2MA: u32 = 0;
1832pub const PADS_BANK0_GPIO15_DRIVE_VALUE_4MA: u32 = 1;
1833pub const PADS_BANK0_GPIO15_DRIVE_VALUE_8MA: u32 = 2;
1834pub const PADS_BANK0_GPIO15_DRIVE_VALUE_12MA: u32 = 3;
1835pub const PADS_BANK0_GPIO15_PUE_RESET: u32 = 0;
1836pub const PADS_BANK0_GPIO15_PUE_BITS: u32 = 8;
1837pub const PADS_BANK0_GPIO15_PUE_MSB: u32 = 3;
1838pub const PADS_BANK0_GPIO15_PUE_LSB: u32 = 3;
1839pub const PADS_BANK0_GPIO15_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1840pub const PADS_BANK0_GPIO15_PDE_RESET: u32 = 1;
1841pub const PADS_BANK0_GPIO15_PDE_BITS: u32 = 4;
1842pub const PADS_BANK0_GPIO15_PDE_MSB: u32 = 2;
1843pub const PADS_BANK0_GPIO15_PDE_LSB: u32 = 2;
1844pub const PADS_BANK0_GPIO15_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1845pub const PADS_BANK0_GPIO15_SCHMITT_RESET: u32 = 1;
1846pub const PADS_BANK0_GPIO15_SCHMITT_BITS: u32 = 2;
1847pub const PADS_BANK0_GPIO15_SCHMITT_MSB: u32 = 1;
1848pub const PADS_BANK0_GPIO15_SCHMITT_LSB: u32 = 1;
1849pub const PADS_BANK0_GPIO15_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1850pub const PADS_BANK0_GPIO15_SLEWFAST_RESET: u32 = 0;
1851pub const PADS_BANK0_GPIO15_SLEWFAST_BITS: u32 = 1;
1852pub const PADS_BANK0_GPIO15_SLEWFAST_MSB: u32 = 0;
1853pub const PADS_BANK0_GPIO15_SLEWFAST_LSB: u32 = 0;
1854pub const PADS_BANK0_GPIO15_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1855pub const PADS_BANK0_GPIO16_OFFSET: u32 = 68;
1856pub const PADS_BANK0_GPIO16_BITS: u32 = 255;
1857pub const PADS_BANK0_GPIO16_RESET: u32 = 86;
1858pub const PADS_BANK0_GPIO16_OD_RESET: u32 = 0;
1859pub const PADS_BANK0_GPIO16_OD_BITS: u32 = 128;
1860pub const PADS_BANK0_GPIO16_OD_MSB: u32 = 7;
1861pub const PADS_BANK0_GPIO16_OD_LSB: u32 = 7;
1862pub const PADS_BANK0_GPIO16_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1863pub const PADS_BANK0_GPIO16_IE_RESET: u32 = 1;
1864pub const PADS_BANK0_GPIO16_IE_BITS: u32 = 64;
1865pub const PADS_BANK0_GPIO16_IE_MSB: u32 = 6;
1866pub const PADS_BANK0_GPIO16_IE_LSB: u32 = 6;
1867pub const PADS_BANK0_GPIO16_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1868pub const PADS_BANK0_GPIO16_DRIVE_RESET: u32 = 1;
1869pub const PADS_BANK0_GPIO16_DRIVE_BITS: u32 = 48;
1870pub const PADS_BANK0_GPIO16_DRIVE_MSB: u32 = 5;
1871pub const PADS_BANK0_GPIO16_DRIVE_LSB: u32 = 4;
1872pub const PADS_BANK0_GPIO16_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1873pub const PADS_BANK0_GPIO16_DRIVE_VALUE_2MA: u32 = 0;
1874pub const PADS_BANK0_GPIO16_DRIVE_VALUE_4MA: u32 = 1;
1875pub const PADS_BANK0_GPIO16_DRIVE_VALUE_8MA: u32 = 2;
1876pub const PADS_BANK0_GPIO16_DRIVE_VALUE_12MA: u32 = 3;
1877pub const PADS_BANK0_GPIO16_PUE_RESET: u32 = 0;
1878pub const PADS_BANK0_GPIO16_PUE_BITS: u32 = 8;
1879pub const PADS_BANK0_GPIO16_PUE_MSB: u32 = 3;
1880pub const PADS_BANK0_GPIO16_PUE_LSB: u32 = 3;
1881pub const PADS_BANK0_GPIO16_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1882pub const PADS_BANK0_GPIO16_PDE_RESET: u32 = 1;
1883pub const PADS_BANK0_GPIO16_PDE_BITS: u32 = 4;
1884pub const PADS_BANK0_GPIO16_PDE_MSB: u32 = 2;
1885pub const PADS_BANK0_GPIO16_PDE_LSB: u32 = 2;
1886pub const PADS_BANK0_GPIO16_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1887pub const PADS_BANK0_GPIO16_SCHMITT_RESET: u32 = 1;
1888pub const PADS_BANK0_GPIO16_SCHMITT_BITS: u32 = 2;
1889pub const PADS_BANK0_GPIO16_SCHMITT_MSB: u32 = 1;
1890pub const PADS_BANK0_GPIO16_SCHMITT_LSB: u32 = 1;
1891pub const PADS_BANK0_GPIO16_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1892pub const PADS_BANK0_GPIO16_SLEWFAST_RESET: u32 = 0;
1893pub const PADS_BANK0_GPIO16_SLEWFAST_BITS: u32 = 1;
1894pub const PADS_BANK0_GPIO16_SLEWFAST_MSB: u32 = 0;
1895pub const PADS_BANK0_GPIO16_SLEWFAST_LSB: u32 = 0;
1896pub const PADS_BANK0_GPIO16_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1897pub const PADS_BANK0_GPIO17_OFFSET: u32 = 72;
1898pub const PADS_BANK0_GPIO17_BITS: u32 = 255;
1899pub const PADS_BANK0_GPIO17_RESET: u32 = 86;
1900pub const PADS_BANK0_GPIO17_OD_RESET: u32 = 0;
1901pub const PADS_BANK0_GPIO17_OD_BITS: u32 = 128;
1902pub const PADS_BANK0_GPIO17_OD_MSB: u32 = 7;
1903pub const PADS_BANK0_GPIO17_OD_LSB: u32 = 7;
1904pub const PADS_BANK0_GPIO17_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1905pub const PADS_BANK0_GPIO17_IE_RESET: u32 = 1;
1906pub const PADS_BANK0_GPIO17_IE_BITS: u32 = 64;
1907pub const PADS_BANK0_GPIO17_IE_MSB: u32 = 6;
1908pub const PADS_BANK0_GPIO17_IE_LSB: u32 = 6;
1909pub const PADS_BANK0_GPIO17_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1910pub const PADS_BANK0_GPIO17_DRIVE_RESET: u32 = 1;
1911pub const PADS_BANK0_GPIO17_DRIVE_BITS: u32 = 48;
1912pub const PADS_BANK0_GPIO17_DRIVE_MSB: u32 = 5;
1913pub const PADS_BANK0_GPIO17_DRIVE_LSB: u32 = 4;
1914pub const PADS_BANK0_GPIO17_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1915pub const PADS_BANK0_GPIO17_DRIVE_VALUE_2MA: u32 = 0;
1916pub const PADS_BANK0_GPIO17_DRIVE_VALUE_4MA: u32 = 1;
1917pub const PADS_BANK0_GPIO17_DRIVE_VALUE_8MA: u32 = 2;
1918pub const PADS_BANK0_GPIO17_DRIVE_VALUE_12MA: u32 = 3;
1919pub const PADS_BANK0_GPIO17_PUE_RESET: u32 = 0;
1920pub const PADS_BANK0_GPIO17_PUE_BITS: u32 = 8;
1921pub const PADS_BANK0_GPIO17_PUE_MSB: u32 = 3;
1922pub const PADS_BANK0_GPIO17_PUE_LSB: u32 = 3;
1923pub const PADS_BANK0_GPIO17_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1924pub const PADS_BANK0_GPIO17_PDE_RESET: u32 = 1;
1925pub const PADS_BANK0_GPIO17_PDE_BITS: u32 = 4;
1926pub const PADS_BANK0_GPIO17_PDE_MSB: u32 = 2;
1927pub const PADS_BANK0_GPIO17_PDE_LSB: u32 = 2;
1928pub const PADS_BANK0_GPIO17_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1929pub const PADS_BANK0_GPIO17_SCHMITT_RESET: u32 = 1;
1930pub const PADS_BANK0_GPIO17_SCHMITT_BITS: u32 = 2;
1931pub const PADS_BANK0_GPIO17_SCHMITT_MSB: u32 = 1;
1932pub const PADS_BANK0_GPIO17_SCHMITT_LSB: u32 = 1;
1933pub const PADS_BANK0_GPIO17_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1934pub const PADS_BANK0_GPIO17_SLEWFAST_RESET: u32 = 0;
1935pub const PADS_BANK0_GPIO17_SLEWFAST_BITS: u32 = 1;
1936pub const PADS_BANK0_GPIO17_SLEWFAST_MSB: u32 = 0;
1937pub const PADS_BANK0_GPIO17_SLEWFAST_LSB: u32 = 0;
1938pub const PADS_BANK0_GPIO17_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1939pub const PADS_BANK0_GPIO18_OFFSET: u32 = 76;
1940pub const PADS_BANK0_GPIO18_BITS: u32 = 255;
1941pub const PADS_BANK0_GPIO18_RESET: u32 = 86;
1942pub const PADS_BANK0_GPIO18_OD_RESET: u32 = 0;
1943pub const PADS_BANK0_GPIO18_OD_BITS: u32 = 128;
1944pub const PADS_BANK0_GPIO18_OD_MSB: u32 = 7;
1945pub const PADS_BANK0_GPIO18_OD_LSB: u32 = 7;
1946pub const PADS_BANK0_GPIO18_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1947pub const PADS_BANK0_GPIO18_IE_RESET: u32 = 1;
1948pub const PADS_BANK0_GPIO18_IE_BITS: u32 = 64;
1949pub const PADS_BANK0_GPIO18_IE_MSB: u32 = 6;
1950pub const PADS_BANK0_GPIO18_IE_LSB: u32 = 6;
1951pub const PADS_BANK0_GPIO18_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1952pub const PADS_BANK0_GPIO18_DRIVE_RESET: u32 = 1;
1953pub const PADS_BANK0_GPIO18_DRIVE_BITS: u32 = 48;
1954pub const PADS_BANK0_GPIO18_DRIVE_MSB: u32 = 5;
1955pub const PADS_BANK0_GPIO18_DRIVE_LSB: u32 = 4;
1956pub const PADS_BANK0_GPIO18_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1957pub const PADS_BANK0_GPIO18_DRIVE_VALUE_2MA: u32 = 0;
1958pub const PADS_BANK0_GPIO18_DRIVE_VALUE_4MA: u32 = 1;
1959pub const PADS_BANK0_GPIO18_DRIVE_VALUE_8MA: u32 = 2;
1960pub const PADS_BANK0_GPIO18_DRIVE_VALUE_12MA: u32 = 3;
1961pub const PADS_BANK0_GPIO18_PUE_RESET: u32 = 0;
1962pub const PADS_BANK0_GPIO18_PUE_BITS: u32 = 8;
1963pub const PADS_BANK0_GPIO18_PUE_MSB: u32 = 3;
1964pub const PADS_BANK0_GPIO18_PUE_LSB: u32 = 3;
1965pub const PADS_BANK0_GPIO18_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1966pub const PADS_BANK0_GPIO18_PDE_RESET: u32 = 1;
1967pub const PADS_BANK0_GPIO18_PDE_BITS: u32 = 4;
1968pub const PADS_BANK0_GPIO18_PDE_MSB: u32 = 2;
1969pub const PADS_BANK0_GPIO18_PDE_LSB: u32 = 2;
1970pub const PADS_BANK0_GPIO18_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1971pub const PADS_BANK0_GPIO18_SCHMITT_RESET: u32 = 1;
1972pub const PADS_BANK0_GPIO18_SCHMITT_BITS: u32 = 2;
1973pub const PADS_BANK0_GPIO18_SCHMITT_MSB: u32 = 1;
1974pub const PADS_BANK0_GPIO18_SCHMITT_LSB: u32 = 1;
1975pub const PADS_BANK0_GPIO18_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
1976pub const PADS_BANK0_GPIO18_SLEWFAST_RESET: u32 = 0;
1977pub const PADS_BANK0_GPIO18_SLEWFAST_BITS: u32 = 1;
1978pub const PADS_BANK0_GPIO18_SLEWFAST_MSB: u32 = 0;
1979pub const PADS_BANK0_GPIO18_SLEWFAST_LSB: u32 = 0;
1980pub const PADS_BANK0_GPIO18_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
1981pub const PADS_BANK0_GPIO19_OFFSET: u32 = 80;
1982pub const PADS_BANK0_GPIO19_BITS: u32 = 255;
1983pub const PADS_BANK0_GPIO19_RESET: u32 = 86;
1984pub const PADS_BANK0_GPIO19_OD_RESET: u32 = 0;
1985pub const PADS_BANK0_GPIO19_OD_BITS: u32 = 128;
1986pub const PADS_BANK0_GPIO19_OD_MSB: u32 = 7;
1987pub const PADS_BANK0_GPIO19_OD_LSB: u32 = 7;
1988pub const PADS_BANK0_GPIO19_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
1989pub const PADS_BANK0_GPIO19_IE_RESET: u32 = 1;
1990pub const PADS_BANK0_GPIO19_IE_BITS: u32 = 64;
1991pub const PADS_BANK0_GPIO19_IE_MSB: u32 = 6;
1992pub const PADS_BANK0_GPIO19_IE_LSB: u32 = 6;
1993pub const PADS_BANK0_GPIO19_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1994pub const PADS_BANK0_GPIO19_DRIVE_RESET: u32 = 1;
1995pub const PADS_BANK0_GPIO19_DRIVE_BITS: u32 = 48;
1996pub const PADS_BANK0_GPIO19_DRIVE_MSB: u32 = 5;
1997pub const PADS_BANK0_GPIO19_DRIVE_LSB: u32 = 4;
1998pub const PADS_BANK0_GPIO19_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
1999pub const PADS_BANK0_GPIO19_DRIVE_VALUE_2MA: u32 = 0;
2000pub const PADS_BANK0_GPIO19_DRIVE_VALUE_4MA: u32 = 1;
2001pub const PADS_BANK0_GPIO19_DRIVE_VALUE_8MA: u32 = 2;
2002pub const PADS_BANK0_GPIO19_DRIVE_VALUE_12MA: u32 = 3;
2003pub const PADS_BANK0_GPIO19_PUE_RESET: u32 = 0;
2004pub const PADS_BANK0_GPIO19_PUE_BITS: u32 = 8;
2005pub const PADS_BANK0_GPIO19_PUE_MSB: u32 = 3;
2006pub const PADS_BANK0_GPIO19_PUE_LSB: u32 = 3;
2007pub const PADS_BANK0_GPIO19_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2008pub const PADS_BANK0_GPIO19_PDE_RESET: u32 = 1;
2009pub const PADS_BANK0_GPIO19_PDE_BITS: u32 = 4;
2010pub const PADS_BANK0_GPIO19_PDE_MSB: u32 = 2;
2011pub const PADS_BANK0_GPIO19_PDE_LSB: u32 = 2;
2012pub const PADS_BANK0_GPIO19_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2013pub const PADS_BANK0_GPIO19_SCHMITT_RESET: u32 = 1;
2014pub const PADS_BANK0_GPIO19_SCHMITT_BITS: u32 = 2;
2015pub const PADS_BANK0_GPIO19_SCHMITT_MSB: u32 = 1;
2016pub const PADS_BANK0_GPIO19_SCHMITT_LSB: u32 = 1;
2017pub const PADS_BANK0_GPIO19_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2018pub const PADS_BANK0_GPIO19_SLEWFAST_RESET: u32 = 0;
2019pub const PADS_BANK0_GPIO19_SLEWFAST_BITS: u32 = 1;
2020pub const PADS_BANK0_GPIO19_SLEWFAST_MSB: u32 = 0;
2021pub const PADS_BANK0_GPIO19_SLEWFAST_LSB: u32 = 0;
2022pub const PADS_BANK0_GPIO19_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2023pub const PADS_BANK0_GPIO20_OFFSET: u32 = 84;
2024pub const PADS_BANK0_GPIO20_BITS: u32 = 255;
2025pub const PADS_BANK0_GPIO20_RESET: u32 = 86;
2026pub const PADS_BANK0_GPIO20_OD_RESET: u32 = 0;
2027pub const PADS_BANK0_GPIO20_OD_BITS: u32 = 128;
2028pub const PADS_BANK0_GPIO20_OD_MSB: u32 = 7;
2029pub const PADS_BANK0_GPIO20_OD_LSB: u32 = 7;
2030pub const PADS_BANK0_GPIO20_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2031pub const PADS_BANK0_GPIO20_IE_RESET: u32 = 1;
2032pub const PADS_BANK0_GPIO20_IE_BITS: u32 = 64;
2033pub const PADS_BANK0_GPIO20_IE_MSB: u32 = 6;
2034pub const PADS_BANK0_GPIO20_IE_LSB: u32 = 6;
2035pub const PADS_BANK0_GPIO20_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2036pub const PADS_BANK0_GPIO20_DRIVE_RESET: u32 = 1;
2037pub const PADS_BANK0_GPIO20_DRIVE_BITS: u32 = 48;
2038pub const PADS_BANK0_GPIO20_DRIVE_MSB: u32 = 5;
2039pub const PADS_BANK0_GPIO20_DRIVE_LSB: u32 = 4;
2040pub const PADS_BANK0_GPIO20_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2041pub const PADS_BANK0_GPIO20_DRIVE_VALUE_2MA: u32 = 0;
2042pub const PADS_BANK0_GPIO20_DRIVE_VALUE_4MA: u32 = 1;
2043pub const PADS_BANK0_GPIO20_DRIVE_VALUE_8MA: u32 = 2;
2044pub const PADS_BANK0_GPIO20_DRIVE_VALUE_12MA: u32 = 3;
2045pub const PADS_BANK0_GPIO20_PUE_RESET: u32 = 0;
2046pub const PADS_BANK0_GPIO20_PUE_BITS: u32 = 8;
2047pub const PADS_BANK0_GPIO20_PUE_MSB: u32 = 3;
2048pub const PADS_BANK0_GPIO20_PUE_LSB: u32 = 3;
2049pub const PADS_BANK0_GPIO20_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2050pub const PADS_BANK0_GPIO20_PDE_RESET: u32 = 1;
2051pub const PADS_BANK0_GPIO20_PDE_BITS: u32 = 4;
2052pub const PADS_BANK0_GPIO20_PDE_MSB: u32 = 2;
2053pub const PADS_BANK0_GPIO20_PDE_LSB: u32 = 2;
2054pub const PADS_BANK0_GPIO20_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2055pub const PADS_BANK0_GPIO20_SCHMITT_RESET: u32 = 1;
2056pub const PADS_BANK0_GPIO20_SCHMITT_BITS: u32 = 2;
2057pub const PADS_BANK0_GPIO20_SCHMITT_MSB: u32 = 1;
2058pub const PADS_BANK0_GPIO20_SCHMITT_LSB: u32 = 1;
2059pub const PADS_BANK0_GPIO20_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2060pub const PADS_BANK0_GPIO20_SLEWFAST_RESET: u32 = 0;
2061pub const PADS_BANK0_GPIO20_SLEWFAST_BITS: u32 = 1;
2062pub const PADS_BANK0_GPIO20_SLEWFAST_MSB: u32 = 0;
2063pub const PADS_BANK0_GPIO20_SLEWFAST_LSB: u32 = 0;
2064pub const PADS_BANK0_GPIO20_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2065pub const PADS_BANK0_GPIO21_OFFSET: u32 = 88;
2066pub const PADS_BANK0_GPIO21_BITS: u32 = 255;
2067pub const PADS_BANK0_GPIO21_RESET: u32 = 86;
2068pub const PADS_BANK0_GPIO21_OD_RESET: u32 = 0;
2069pub const PADS_BANK0_GPIO21_OD_BITS: u32 = 128;
2070pub const PADS_BANK0_GPIO21_OD_MSB: u32 = 7;
2071pub const PADS_BANK0_GPIO21_OD_LSB: u32 = 7;
2072pub const PADS_BANK0_GPIO21_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2073pub const PADS_BANK0_GPIO21_IE_RESET: u32 = 1;
2074pub const PADS_BANK0_GPIO21_IE_BITS: u32 = 64;
2075pub const PADS_BANK0_GPIO21_IE_MSB: u32 = 6;
2076pub const PADS_BANK0_GPIO21_IE_LSB: u32 = 6;
2077pub const PADS_BANK0_GPIO21_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2078pub const PADS_BANK0_GPIO21_DRIVE_RESET: u32 = 1;
2079pub const PADS_BANK0_GPIO21_DRIVE_BITS: u32 = 48;
2080pub const PADS_BANK0_GPIO21_DRIVE_MSB: u32 = 5;
2081pub const PADS_BANK0_GPIO21_DRIVE_LSB: u32 = 4;
2082pub const PADS_BANK0_GPIO21_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2083pub const PADS_BANK0_GPIO21_DRIVE_VALUE_2MA: u32 = 0;
2084pub const PADS_BANK0_GPIO21_DRIVE_VALUE_4MA: u32 = 1;
2085pub const PADS_BANK0_GPIO21_DRIVE_VALUE_8MA: u32 = 2;
2086pub const PADS_BANK0_GPIO21_DRIVE_VALUE_12MA: u32 = 3;
2087pub const PADS_BANK0_GPIO21_PUE_RESET: u32 = 0;
2088pub const PADS_BANK0_GPIO21_PUE_BITS: u32 = 8;
2089pub const PADS_BANK0_GPIO21_PUE_MSB: u32 = 3;
2090pub const PADS_BANK0_GPIO21_PUE_LSB: u32 = 3;
2091pub const PADS_BANK0_GPIO21_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2092pub const PADS_BANK0_GPIO21_PDE_RESET: u32 = 1;
2093pub const PADS_BANK0_GPIO21_PDE_BITS: u32 = 4;
2094pub const PADS_BANK0_GPIO21_PDE_MSB: u32 = 2;
2095pub const PADS_BANK0_GPIO21_PDE_LSB: u32 = 2;
2096pub const PADS_BANK0_GPIO21_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2097pub const PADS_BANK0_GPIO21_SCHMITT_RESET: u32 = 1;
2098pub const PADS_BANK0_GPIO21_SCHMITT_BITS: u32 = 2;
2099pub const PADS_BANK0_GPIO21_SCHMITT_MSB: u32 = 1;
2100pub const PADS_BANK0_GPIO21_SCHMITT_LSB: u32 = 1;
2101pub const PADS_BANK0_GPIO21_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2102pub const PADS_BANK0_GPIO21_SLEWFAST_RESET: u32 = 0;
2103pub const PADS_BANK0_GPIO21_SLEWFAST_BITS: u32 = 1;
2104pub const PADS_BANK0_GPIO21_SLEWFAST_MSB: u32 = 0;
2105pub const PADS_BANK0_GPIO21_SLEWFAST_LSB: u32 = 0;
2106pub const PADS_BANK0_GPIO21_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2107pub const PADS_BANK0_GPIO22_OFFSET: u32 = 92;
2108pub const PADS_BANK0_GPIO22_BITS: u32 = 255;
2109pub const PADS_BANK0_GPIO22_RESET: u32 = 86;
2110pub const PADS_BANK0_GPIO22_OD_RESET: u32 = 0;
2111pub const PADS_BANK0_GPIO22_OD_BITS: u32 = 128;
2112pub const PADS_BANK0_GPIO22_OD_MSB: u32 = 7;
2113pub const PADS_BANK0_GPIO22_OD_LSB: u32 = 7;
2114pub const PADS_BANK0_GPIO22_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2115pub const PADS_BANK0_GPIO22_IE_RESET: u32 = 1;
2116pub const PADS_BANK0_GPIO22_IE_BITS: u32 = 64;
2117pub const PADS_BANK0_GPIO22_IE_MSB: u32 = 6;
2118pub const PADS_BANK0_GPIO22_IE_LSB: u32 = 6;
2119pub const PADS_BANK0_GPIO22_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2120pub const PADS_BANK0_GPIO22_DRIVE_RESET: u32 = 1;
2121pub const PADS_BANK0_GPIO22_DRIVE_BITS: u32 = 48;
2122pub const PADS_BANK0_GPIO22_DRIVE_MSB: u32 = 5;
2123pub const PADS_BANK0_GPIO22_DRIVE_LSB: u32 = 4;
2124pub const PADS_BANK0_GPIO22_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2125pub const PADS_BANK0_GPIO22_DRIVE_VALUE_2MA: u32 = 0;
2126pub const PADS_BANK0_GPIO22_DRIVE_VALUE_4MA: u32 = 1;
2127pub const PADS_BANK0_GPIO22_DRIVE_VALUE_8MA: u32 = 2;
2128pub const PADS_BANK0_GPIO22_DRIVE_VALUE_12MA: u32 = 3;
2129pub const PADS_BANK0_GPIO22_PUE_RESET: u32 = 0;
2130pub const PADS_BANK0_GPIO22_PUE_BITS: u32 = 8;
2131pub const PADS_BANK0_GPIO22_PUE_MSB: u32 = 3;
2132pub const PADS_BANK0_GPIO22_PUE_LSB: u32 = 3;
2133pub const PADS_BANK0_GPIO22_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2134pub const PADS_BANK0_GPIO22_PDE_RESET: u32 = 1;
2135pub const PADS_BANK0_GPIO22_PDE_BITS: u32 = 4;
2136pub const PADS_BANK0_GPIO22_PDE_MSB: u32 = 2;
2137pub const PADS_BANK0_GPIO22_PDE_LSB: u32 = 2;
2138pub const PADS_BANK0_GPIO22_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2139pub const PADS_BANK0_GPIO22_SCHMITT_RESET: u32 = 1;
2140pub const PADS_BANK0_GPIO22_SCHMITT_BITS: u32 = 2;
2141pub const PADS_BANK0_GPIO22_SCHMITT_MSB: u32 = 1;
2142pub const PADS_BANK0_GPIO22_SCHMITT_LSB: u32 = 1;
2143pub const PADS_BANK0_GPIO22_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2144pub const PADS_BANK0_GPIO22_SLEWFAST_RESET: u32 = 0;
2145pub const PADS_BANK0_GPIO22_SLEWFAST_BITS: u32 = 1;
2146pub const PADS_BANK0_GPIO22_SLEWFAST_MSB: u32 = 0;
2147pub const PADS_BANK0_GPIO22_SLEWFAST_LSB: u32 = 0;
2148pub const PADS_BANK0_GPIO22_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2149pub const PADS_BANK0_GPIO23_OFFSET: u32 = 96;
2150pub const PADS_BANK0_GPIO23_BITS: u32 = 255;
2151pub const PADS_BANK0_GPIO23_RESET: u32 = 86;
2152pub const PADS_BANK0_GPIO23_OD_RESET: u32 = 0;
2153pub const PADS_BANK0_GPIO23_OD_BITS: u32 = 128;
2154pub const PADS_BANK0_GPIO23_OD_MSB: u32 = 7;
2155pub const PADS_BANK0_GPIO23_OD_LSB: u32 = 7;
2156pub const PADS_BANK0_GPIO23_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2157pub const PADS_BANK0_GPIO23_IE_RESET: u32 = 1;
2158pub const PADS_BANK0_GPIO23_IE_BITS: u32 = 64;
2159pub const PADS_BANK0_GPIO23_IE_MSB: u32 = 6;
2160pub const PADS_BANK0_GPIO23_IE_LSB: u32 = 6;
2161pub const PADS_BANK0_GPIO23_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2162pub const PADS_BANK0_GPIO23_DRIVE_RESET: u32 = 1;
2163pub const PADS_BANK0_GPIO23_DRIVE_BITS: u32 = 48;
2164pub const PADS_BANK0_GPIO23_DRIVE_MSB: u32 = 5;
2165pub const PADS_BANK0_GPIO23_DRIVE_LSB: u32 = 4;
2166pub const PADS_BANK0_GPIO23_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2167pub const PADS_BANK0_GPIO23_DRIVE_VALUE_2MA: u32 = 0;
2168pub const PADS_BANK0_GPIO23_DRIVE_VALUE_4MA: u32 = 1;
2169pub const PADS_BANK0_GPIO23_DRIVE_VALUE_8MA: u32 = 2;
2170pub const PADS_BANK0_GPIO23_DRIVE_VALUE_12MA: u32 = 3;
2171pub const PADS_BANK0_GPIO23_PUE_RESET: u32 = 0;
2172pub const PADS_BANK0_GPIO23_PUE_BITS: u32 = 8;
2173pub const PADS_BANK0_GPIO23_PUE_MSB: u32 = 3;
2174pub const PADS_BANK0_GPIO23_PUE_LSB: u32 = 3;
2175pub const PADS_BANK0_GPIO23_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2176pub const PADS_BANK0_GPIO23_PDE_RESET: u32 = 1;
2177pub const PADS_BANK0_GPIO23_PDE_BITS: u32 = 4;
2178pub const PADS_BANK0_GPIO23_PDE_MSB: u32 = 2;
2179pub const PADS_BANK0_GPIO23_PDE_LSB: u32 = 2;
2180pub const PADS_BANK0_GPIO23_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2181pub const PADS_BANK0_GPIO23_SCHMITT_RESET: u32 = 1;
2182pub const PADS_BANK0_GPIO23_SCHMITT_BITS: u32 = 2;
2183pub const PADS_BANK0_GPIO23_SCHMITT_MSB: u32 = 1;
2184pub const PADS_BANK0_GPIO23_SCHMITT_LSB: u32 = 1;
2185pub const PADS_BANK0_GPIO23_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2186pub const PADS_BANK0_GPIO23_SLEWFAST_RESET: u32 = 0;
2187pub const PADS_BANK0_GPIO23_SLEWFAST_BITS: u32 = 1;
2188pub const PADS_BANK0_GPIO23_SLEWFAST_MSB: u32 = 0;
2189pub const PADS_BANK0_GPIO23_SLEWFAST_LSB: u32 = 0;
2190pub const PADS_BANK0_GPIO23_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2191pub const PADS_BANK0_GPIO24_OFFSET: u32 = 100;
2192pub const PADS_BANK0_GPIO24_BITS: u32 = 255;
2193pub const PADS_BANK0_GPIO24_RESET: u32 = 86;
2194pub const PADS_BANK0_GPIO24_OD_RESET: u32 = 0;
2195pub const PADS_BANK0_GPIO24_OD_BITS: u32 = 128;
2196pub const PADS_BANK0_GPIO24_OD_MSB: u32 = 7;
2197pub const PADS_BANK0_GPIO24_OD_LSB: u32 = 7;
2198pub const PADS_BANK0_GPIO24_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2199pub const PADS_BANK0_GPIO24_IE_RESET: u32 = 1;
2200pub const PADS_BANK0_GPIO24_IE_BITS: u32 = 64;
2201pub const PADS_BANK0_GPIO24_IE_MSB: u32 = 6;
2202pub const PADS_BANK0_GPIO24_IE_LSB: u32 = 6;
2203pub const PADS_BANK0_GPIO24_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2204pub const PADS_BANK0_GPIO24_DRIVE_RESET: u32 = 1;
2205pub const PADS_BANK0_GPIO24_DRIVE_BITS: u32 = 48;
2206pub const PADS_BANK0_GPIO24_DRIVE_MSB: u32 = 5;
2207pub const PADS_BANK0_GPIO24_DRIVE_LSB: u32 = 4;
2208pub const PADS_BANK0_GPIO24_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2209pub const PADS_BANK0_GPIO24_DRIVE_VALUE_2MA: u32 = 0;
2210pub const PADS_BANK0_GPIO24_DRIVE_VALUE_4MA: u32 = 1;
2211pub const PADS_BANK0_GPIO24_DRIVE_VALUE_8MA: u32 = 2;
2212pub const PADS_BANK0_GPIO24_DRIVE_VALUE_12MA: u32 = 3;
2213pub const PADS_BANK0_GPIO24_PUE_RESET: u32 = 0;
2214pub const PADS_BANK0_GPIO24_PUE_BITS: u32 = 8;
2215pub const PADS_BANK0_GPIO24_PUE_MSB: u32 = 3;
2216pub const PADS_BANK0_GPIO24_PUE_LSB: u32 = 3;
2217pub const PADS_BANK0_GPIO24_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2218pub const PADS_BANK0_GPIO24_PDE_RESET: u32 = 1;
2219pub const PADS_BANK0_GPIO24_PDE_BITS: u32 = 4;
2220pub const PADS_BANK0_GPIO24_PDE_MSB: u32 = 2;
2221pub const PADS_BANK0_GPIO24_PDE_LSB: u32 = 2;
2222pub const PADS_BANK0_GPIO24_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2223pub const PADS_BANK0_GPIO24_SCHMITT_RESET: u32 = 1;
2224pub const PADS_BANK0_GPIO24_SCHMITT_BITS: u32 = 2;
2225pub const PADS_BANK0_GPIO24_SCHMITT_MSB: u32 = 1;
2226pub const PADS_BANK0_GPIO24_SCHMITT_LSB: u32 = 1;
2227pub const PADS_BANK0_GPIO24_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2228pub const PADS_BANK0_GPIO24_SLEWFAST_RESET: u32 = 0;
2229pub const PADS_BANK0_GPIO24_SLEWFAST_BITS: u32 = 1;
2230pub const PADS_BANK0_GPIO24_SLEWFAST_MSB: u32 = 0;
2231pub const PADS_BANK0_GPIO24_SLEWFAST_LSB: u32 = 0;
2232pub const PADS_BANK0_GPIO24_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2233pub const PADS_BANK0_GPIO25_OFFSET: u32 = 104;
2234pub const PADS_BANK0_GPIO25_BITS: u32 = 255;
2235pub const PADS_BANK0_GPIO25_RESET: u32 = 86;
2236pub const PADS_BANK0_GPIO25_OD_RESET: u32 = 0;
2237pub const PADS_BANK0_GPIO25_OD_BITS: u32 = 128;
2238pub const PADS_BANK0_GPIO25_OD_MSB: u32 = 7;
2239pub const PADS_BANK0_GPIO25_OD_LSB: u32 = 7;
2240pub const PADS_BANK0_GPIO25_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2241pub const PADS_BANK0_GPIO25_IE_RESET: u32 = 1;
2242pub const PADS_BANK0_GPIO25_IE_BITS: u32 = 64;
2243pub const PADS_BANK0_GPIO25_IE_MSB: u32 = 6;
2244pub const PADS_BANK0_GPIO25_IE_LSB: u32 = 6;
2245pub const PADS_BANK0_GPIO25_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2246pub const PADS_BANK0_GPIO25_DRIVE_RESET: u32 = 1;
2247pub const PADS_BANK0_GPIO25_DRIVE_BITS: u32 = 48;
2248pub const PADS_BANK0_GPIO25_DRIVE_MSB: u32 = 5;
2249pub const PADS_BANK0_GPIO25_DRIVE_LSB: u32 = 4;
2250pub const PADS_BANK0_GPIO25_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2251pub const PADS_BANK0_GPIO25_DRIVE_VALUE_2MA: u32 = 0;
2252pub const PADS_BANK0_GPIO25_DRIVE_VALUE_4MA: u32 = 1;
2253pub const PADS_BANK0_GPIO25_DRIVE_VALUE_8MA: u32 = 2;
2254pub const PADS_BANK0_GPIO25_DRIVE_VALUE_12MA: u32 = 3;
2255pub const PADS_BANK0_GPIO25_PUE_RESET: u32 = 0;
2256pub const PADS_BANK0_GPIO25_PUE_BITS: u32 = 8;
2257pub const PADS_BANK0_GPIO25_PUE_MSB: u32 = 3;
2258pub const PADS_BANK0_GPIO25_PUE_LSB: u32 = 3;
2259pub const PADS_BANK0_GPIO25_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2260pub const PADS_BANK0_GPIO25_PDE_RESET: u32 = 1;
2261pub const PADS_BANK0_GPIO25_PDE_BITS: u32 = 4;
2262pub const PADS_BANK0_GPIO25_PDE_MSB: u32 = 2;
2263pub const PADS_BANK0_GPIO25_PDE_LSB: u32 = 2;
2264pub const PADS_BANK0_GPIO25_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2265pub const PADS_BANK0_GPIO25_SCHMITT_RESET: u32 = 1;
2266pub const PADS_BANK0_GPIO25_SCHMITT_BITS: u32 = 2;
2267pub const PADS_BANK0_GPIO25_SCHMITT_MSB: u32 = 1;
2268pub const PADS_BANK0_GPIO25_SCHMITT_LSB: u32 = 1;
2269pub const PADS_BANK0_GPIO25_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2270pub const PADS_BANK0_GPIO25_SLEWFAST_RESET: u32 = 0;
2271pub const PADS_BANK0_GPIO25_SLEWFAST_BITS: u32 = 1;
2272pub const PADS_BANK0_GPIO25_SLEWFAST_MSB: u32 = 0;
2273pub const PADS_BANK0_GPIO25_SLEWFAST_LSB: u32 = 0;
2274pub const PADS_BANK0_GPIO25_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2275pub const PADS_BANK0_GPIO26_OFFSET: u32 = 108;
2276pub const PADS_BANK0_GPIO26_BITS: u32 = 255;
2277pub const PADS_BANK0_GPIO26_RESET: u32 = 86;
2278pub const PADS_BANK0_GPIO26_OD_RESET: u32 = 0;
2279pub const PADS_BANK0_GPIO26_OD_BITS: u32 = 128;
2280pub const PADS_BANK0_GPIO26_OD_MSB: u32 = 7;
2281pub const PADS_BANK0_GPIO26_OD_LSB: u32 = 7;
2282pub const PADS_BANK0_GPIO26_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2283pub const PADS_BANK0_GPIO26_IE_RESET: u32 = 1;
2284pub const PADS_BANK0_GPIO26_IE_BITS: u32 = 64;
2285pub const PADS_BANK0_GPIO26_IE_MSB: u32 = 6;
2286pub const PADS_BANK0_GPIO26_IE_LSB: u32 = 6;
2287pub const PADS_BANK0_GPIO26_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2288pub const PADS_BANK0_GPIO26_DRIVE_RESET: u32 = 1;
2289pub const PADS_BANK0_GPIO26_DRIVE_BITS: u32 = 48;
2290pub const PADS_BANK0_GPIO26_DRIVE_MSB: u32 = 5;
2291pub const PADS_BANK0_GPIO26_DRIVE_LSB: u32 = 4;
2292pub const PADS_BANK0_GPIO26_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2293pub const PADS_BANK0_GPIO26_DRIVE_VALUE_2MA: u32 = 0;
2294pub const PADS_BANK0_GPIO26_DRIVE_VALUE_4MA: u32 = 1;
2295pub const PADS_BANK0_GPIO26_DRIVE_VALUE_8MA: u32 = 2;
2296pub const PADS_BANK0_GPIO26_DRIVE_VALUE_12MA: u32 = 3;
2297pub const PADS_BANK0_GPIO26_PUE_RESET: u32 = 0;
2298pub const PADS_BANK0_GPIO26_PUE_BITS: u32 = 8;
2299pub const PADS_BANK0_GPIO26_PUE_MSB: u32 = 3;
2300pub const PADS_BANK0_GPIO26_PUE_LSB: u32 = 3;
2301pub const PADS_BANK0_GPIO26_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2302pub const PADS_BANK0_GPIO26_PDE_RESET: u32 = 1;
2303pub const PADS_BANK0_GPIO26_PDE_BITS: u32 = 4;
2304pub const PADS_BANK0_GPIO26_PDE_MSB: u32 = 2;
2305pub const PADS_BANK0_GPIO26_PDE_LSB: u32 = 2;
2306pub const PADS_BANK0_GPIO26_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2307pub const PADS_BANK0_GPIO26_SCHMITT_RESET: u32 = 1;
2308pub const PADS_BANK0_GPIO26_SCHMITT_BITS: u32 = 2;
2309pub const PADS_BANK0_GPIO26_SCHMITT_MSB: u32 = 1;
2310pub const PADS_BANK0_GPIO26_SCHMITT_LSB: u32 = 1;
2311pub const PADS_BANK0_GPIO26_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2312pub const PADS_BANK0_GPIO26_SLEWFAST_RESET: u32 = 0;
2313pub const PADS_BANK0_GPIO26_SLEWFAST_BITS: u32 = 1;
2314pub const PADS_BANK0_GPIO26_SLEWFAST_MSB: u32 = 0;
2315pub const PADS_BANK0_GPIO26_SLEWFAST_LSB: u32 = 0;
2316pub const PADS_BANK0_GPIO26_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2317pub const PADS_BANK0_GPIO27_OFFSET: u32 = 112;
2318pub const PADS_BANK0_GPIO27_BITS: u32 = 255;
2319pub const PADS_BANK0_GPIO27_RESET: u32 = 86;
2320pub const PADS_BANK0_GPIO27_OD_RESET: u32 = 0;
2321pub const PADS_BANK0_GPIO27_OD_BITS: u32 = 128;
2322pub const PADS_BANK0_GPIO27_OD_MSB: u32 = 7;
2323pub const PADS_BANK0_GPIO27_OD_LSB: u32 = 7;
2324pub const PADS_BANK0_GPIO27_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2325pub const PADS_BANK0_GPIO27_IE_RESET: u32 = 1;
2326pub const PADS_BANK0_GPIO27_IE_BITS: u32 = 64;
2327pub const PADS_BANK0_GPIO27_IE_MSB: u32 = 6;
2328pub const PADS_BANK0_GPIO27_IE_LSB: u32 = 6;
2329pub const PADS_BANK0_GPIO27_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2330pub const PADS_BANK0_GPIO27_DRIVE_RESET: u32 = 1;
2331pub const PADS_BANK0_GPIO27_DRIVE_BITS: u32 = 48;
2332pub const PADS_BANK0_GPIO27_DRIVE_MSB: u32 = 5;
2333pub const PADS_BANK0_GPIO27_DRIVE_LSB: u32 = 4;
2334pub const PADS_BANK0_GPIO27_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2335pub const PADS_BANK0_GPIO27_DRIVE_VALUE_2MA: u32 = 0;
2336pub const PADS_BANK0_GPIO27_DRIVE_VALUE_4MA: u32 = 1;
2337pub const PADS_BANK0_GPIO27_DRIVE_VALUE_8MA: u32 = 2;
2338pub const PADS_BANK0_GPIO27_DRIVE_VALUE_12MA: u32 = 3;
2339pub const PADS_BANK0_GPIO27_PUE_RESET: u32 = 0;
2340pub const PADS_BANK0_GPIO27_PUE_BITS: u32 = 8;
2341pub const PADS_BANK0_GPIO27_PUE_MSB: u32 = 3;
2342pub const PADS_BANK0_GPIO27_PUE_LSB: u32 = 3;
2343pub const PADS_BANK0_GPIO27_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2344pub const PADS_BANK0_GPIO27_PDE_RESET: u32 = 1;
2345pub const PADS_BANK0_GPIO27_PDE_BITS: u32 = 4;
2346pub const PADS_BANK0_GPIO27_PDE_MSB: u32 = 2;
2347pub const PADS_BANK0_GPIO27_PDE_LSB: u32 = 2;
2348pub const PADS_BANK0_GPIO27_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2349pub const PADS_BANK0_GPIO27_SCHMITT_RESET: u32 = 1;
2350pub const PADS_BANK0_GPIO27_SCHMITT_BITS: u32 = 2;
2351pub const PADS_BANK0_GPIO27_SCHMITT_MSB: u32 = 1;
2352pub const PADS_BANK0_GPIO27_SCHMITT_LSB: u32 = 1;
2353pub const PADS_BANK0_GPIO27_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2354pub const PADS_BANK0_GPIO27_SLEWFAST_RESET: u32 = 0;
2355pub const PADS_BANK0_GPIO27_SLEWFAST_BITS: u32 = 1;
2356pub const PADS_BANK0_GPIO27_SLEWFAST_MSB: u32 = 0;
2357pub const PADS_BANK0_GPIO27_SLEWFAST_LSB: u32 = 0;
2358pub const PADS_BANK0_GPIO27_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2359pub const PADS_BANK0_GPIO28_OFFSET: u32 = 116;
2360pub const PADS_BANK0_GPIO28_BITS: u32 = 255;
2361pub const PADS_BANK0_GPIO28_RESET: u32 = 86;
2362pub const PADS_BANK0_GPIO28_OD_RESET: u32 = 0;
2363pub const PADS_BANK0_GPIO28_OD_BITS: u32 = 128;
2364pub const PADS_BANK0_GPIO28_OD_MSB: u32 = 7;
2365pub const PADS_BANK0_GPIO28_OD_LSB: u32 = 7;
2366pub const PADS_BANK0_GPIO28_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2367pub const PADS_BANK0_GPIO28_IE_RESET: u32 = 1;
2368pub const PADS_BANK0_GPIO28_IE_BITS: u32 = 64;
2369pub const PADS_BANK0_GPIO28_IE_MSB: u32 = 6;
2370pub const PADS_BANK0_GPIO28_IE_LSB: u32 = 6;
2371pub const PADS_BANK0_GPIO28_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2372pub const PADS_BANK0_GPIO28_DRIVE_RESET: u32 = 1;
2373pub const PADS_BANK0_GPIO28_DRIVE_BITS: u32 = 48;
2374pub const PADS_BANK0_GPIO28_DRIVE_MSB: u32 = 5;
2375pub const PADS_BANK0_GPIO28_DRIVE_LSB: u32 = 4;
2376pub const PADS_BANK0_GPIO28_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2377pub const PADS_BANK0_GPIO28_DRIVE_VALUE_2MA: u32 = 0;
2378pub const PADS_BANK0_GPIO28_DRIVE_VALUE_4MA: u32 = 1;
2379pub const PADS_BANK0_GPIO28_DRIVE_VALUE_8MA: u32 = 2;
2380pub const PADS_BANK0_GPIO28_DRIVE_VALUE_12MA: u32 = 3;
2381pub const PADS_BANK0_GPIO28_PUE_RESET: u32 = 0;
2382pub const PADS_BANK0_GPIO28_PUE_BITS: u32 = 8;
2383pub const PADS_BANK0_GPIO28_PUE_MSB: u32 = 3;
2384pub const PADS_BANK0_GPIO28_PUE_LSB: u32 = 3;
2385pub const PADS_BANK0_GPIO28_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2386pub const PADS_BANK0_GPIO28_PDE_RESET: u32 = 1;
2387pub const PADS_BANK0_GPIO28_PDE_BITS: u32 = 4;
2388pub const PADS_BANK0_GPIO28_PDE_MSB: u32 = 2;
2389pub const PADS_BANK0_GPIO28_PDE_LSB: u32 = 2;
2390pub const PADS_BANK0_GPIO28_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2391pub const PADS_BANK0_GPIO28_SCHMITT_RESET: u32 = 1;
2392pub const PADS_BANK0_GPIO28_SCHMITT_BITS: u32 = 2;
2393pub const PADS_BANK0_GPIO28_SCHMITT_MSB: u32 = 1;
2394pub const PADS_BANK0_GPIO28_SCHMITT_LSB: u32 = 1;
2395pub const PADS_BANK0_GPIO28_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2396pub const PADS_BANK0_GPIO28_SLEWFAST_RESET: u32 = 0;
2397pub const PADS_BANK0_GPIO28_SLEWFAST_BITS: u32 = 1;
2398pub const PADS_BANK0_GPIO28_SLEWFAST_MSB: u32 = 0;
2399pub const PADS_BANK0_GPIO28_SLEWFAST_LSB: u32 = 0;
2400pub const PADS_BANK0_GPIO28_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2401pub const PADS_BANK0_GPIO29_OFFSET: u32 = 120;
2402pub const PADS_BANK0_GPIO29_BITS: u32 = 255;
2403pub const PADS_BANK0_GPIO29_RESET: u32 = 86;
2404pub const PADS_BANK0_GPIO29_OD_RESET: u32 = 0;
2405pub const PADS_BANK0_GPIO29_OD_BITS: u32 = 128;
2406pub const PADS_BANK0_GPIO29_OD_MSB: u32 = 7;
2407pub const PADS_BANK0_GPIO29_OD_LSB: u32 = 7;
2408pub const PADS_BANK0_GPIO29_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2409pub const PADS_BANK0_GPIO29_IE_RESET: u32 = 1;
2410pub const PADS_BANK0_GPIO29_IE_BITS: u32 = 64;
2411pub const PADS_BANK0_GPIO29_IE_MSB: u32 = 6;
2412pub const PADS_BANK0_GPIO29_IE_LSB: u32 = 6;
2413pub const PADS_BANK0_GPIO29_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2414pub const PADS_BANK0_GPIO29_DRIVE_RESET: u32 = 1;
2415pub const PADS_BANK0_GPIO29_DRIVE_BITS: u32 = 48;
2416pub const PADS_BANK0_GPIO29_DRIVE_MSB: u32 = 5;
2417pub const PADS_BANK0_GPIO29_DRIVE_LSB: u32 = 4;
2418pub const PADS_BANK0_GPIO29_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2419pub const PADS_BANK0_GPIO29_DRIVE_VALUE_2MA: u32 = 0;
2420pub const PADS_BANK0_GPIO29_DRIVE_VALUE_4MA: u32 = 1;
2421pub const PADS_BANK0_GPIO29_DRIVE_VALUE_8MA: u32 = 2;
2422pub const PADS_BANK0_GPIO29_DRIVE_VALUE_12MA: u32 = 3;
2423pub const PADS_BANK0_GPIO29_PUE_RESET: u32 = 0;
2424pub const PADS_BANK0_GPIO29_PUE_BITS: u32 = 8;
2425pub const PADS_BANK0_GPIO29_PUE_MSB: u32 = 3;
2426pub const PADS_BANK0_GPIO29_PUE_LSB: u32 = 3;
2427pub const PADS_BANK0_GPIO29_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2428pub const PADS_BANK0_GPIO29_PDE_RESET: u32 = 1;
2429pub const PADS_BANK0_GPIO29_PDE_BITS: u32 = 4;
2430pub const PADS_BANK0_GPIO29_PDE_MSB: u32 = 2;
2431pub const PADS_BANK0_GPIO29_PDE_LSB: u32 = 2;
2432pub const PADS_BANK0_GPIO29_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2433pub const PADS_BANK0_GPIO29_SCHMITT_RESET: u32 = 1;
2434pub const PADS_BANK0_GPIO29_SCHMITT_BITS: u32 = 2;
2435pub const PADS_BANK0_GPIO29_SCHMITT_MSB: u32 = 1;
2436pub const PADS_BANK0_GPIO29_SCHMITT_LSB: u32 = 1;
2437pub const PADS_BANK0_GPIO29_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2438pub const PADS_BANK0_GPIO29_SLEWFAST_RESET: u32 = 0;
2439pub const PADS_BANK0_GPIO29_SLEWFAST_BITS: u32 = 1;
2440pub const PADS_BANK0_GPIO29_SLEWFAST_MSB: u32 = 0;
2441pub const PADS_BANK0_GPIO29_SLEWFAST_LSB: u32 = 0;
2442pub const PADS_BANK0_GPIO29_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2443pub const PADS_BANK0_SWCLK_OFFSET: u32 = 124;
2444pub const PADS_BANK0_SWCLK_BITS: u32 = 255;
2445pub const PADS_BANK0_SWCLK_RESET: u32 = 218;
2446pub const PADS_BANK0_SWCLK_OD_RESET: u32 = 1;
2447pub const PADS_BANK0_SWCLK_OD_BITS: u32 = 128;
2448pub const PADS_BANK0_SWCLK_OD_MSB: u32 = 7;
2449pub const PADS_BANK0_SWCLK_OD_LSB: u32 = 7;
2450pub const PADS_BANK0_SWCLK_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2451pub const PADS_BANK0_SWCLK_IE_RESET: u32 = 1;
2452pub const PADS_BANK0_SWCLK_IE_BITS: u32 = 64;
2453pub const PADS_BANK0_SWCLK_IE_MSB: u32 = 6;
2454pub const PADS_BANK0_SWCLK_IE_LSB: u32 = 6;
2455pub const PADS_BANK0_SWCLK_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2456pub const PADS_BANK0_SWCLK_DRIVE_RESET: u32 = 1;
2457pub const PADS_BANK0_SWCLK_DRIVE_BITS: u32 = 48;
2458pub const PADS_BANK0_SWCLK_DRIVE_MSB: u32 = 5;
2459pub const PADS_BANK0_SWCLK_DRIVE_LSB: u32 = 4;
2460pub const PADS_BANK0_SWCLK_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2461pub const PADS_BANK0_SWCLK_DRIVE_VALUE_2MA: u32 = 0;
2462pub const PADS_BANK0_SWCLK_DRIVE_VALUE_4MA: u32 = 1;
2463pub const PADS_BANK0_SWCLK_DRIVE_VALUE_8MA: u32 = 2;
2464pub const PADS_BANK0_SWCLK_DRIVE_VALUE_12MA: u32 = 3;
2465pub const PADS_BANK0_SWCLK_PUE_RESET: u32 = 1;
2466pub const PADS_BANK0_SWCLK_PUE_BITS: u32 = 8;
2467pub const PADS_BANK0_SWCLK_PUE_MSB: u32 = 3;
2468pub const PADS_BANK0_SWCLK_PUE_LSB: u32 = 3;
2469pub const PADS_BANK0_SWCLK_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2470pub const PADS_BANK0_SWCLK_PDE_RESET: u32 = 0;
2471pub const PADS_BANK0_SWCLK_PDE_BITS: u32 = 4;
2472pub const PADS_BANK0_SWCLK_PDE_MSB: u32 = 2;
2473pub const PADS_BANK0_SWCLK_PDE_LSB: u32 = 2;
2474pub const PADS_BANK0_SWCLK_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2475pub const PADS_BANK0_SWCLK_SCHMITT_RESET: u32 = 1;
2476pub const PADS_BANK0_SWCLK_SCHMITT_BITS: u32 = 2;
2477pub const PADS_BANK0_SWCLK_SCHMITT_MSB: u32 = 1;
2478pub const PADS_BANK0_SWCLK_SCHMITT_LSB: u32 = 1;
2479pub const PADS_BANK0_SWCLK_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2480pub const PADS_BANK0_SWCLK_SLEWFAST_RESET: u32 = 0;
2481pub const PADS_BANK0_SWCLK_SLEWFAST_BITS: u32 = 1;
2482pub const PADS_BANK0_SWCLK_SLEWFAST_MSB: u32 = 0;
2483pub const PADS_BANK0_SWCLK_SLEWFAST_LSB: u32 = 0;
2484pub const PADS_BANK0_SWCLK_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2485pub const PADS_BANK0_SWD_OFFSET: u32 = 128;
2486pub const PADS_BANK0_SWD_BITS: u32 = 255;
2487pub const PADS_BANK0_SWD_RESET: u32 = 90;
2488pub const PADS_BANK0_SWD_OD_RESET: u32 = 0;
2489pub const PADS_BANK0_SWD_OD_BITS: u32 = 128;
2490pub const PADS_BANK0_SWD_OD_MSB: u32 = 7;
2491pub const PADS_BANK0_SWD_OD_LSB: u32 = 7;
2492pub const PADS_BANK0_SWD_OD_ACCESS: &'static [u8; 3usize] = b"RW\0";
2493pub const PADS_BANK0_SWD_IE_RESET: u32 = 1;
2494pub const PADS_BANK0_SWD_IE_BITS: u32 = 64;
2495pub const PADS_BANK0_SWD_IE_MSB: u32 = 6;
2496pub const PADS_BANK0_SWD_IE_LSB: u32 = 6;
2497pub const PADS_BANK0_SWD_IE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2498pub const PADS_BANK0_SWD_DRIVE_RESET: u32 = 1;
2499pub const PADS_BANK0_SWD_DRIVE_BITS: u32 = 48;
2500pub const PADS_BANK0_SWD_DRIVE_MSB: u32 = 5;
2501pub const PADS_BANK0_SWD_DRIVE_LSB: u32 = 4;
2502pub const PADS_BANK0_SWD_DRIVE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2503pub const PADS_BANK0_SWD_DRIVE_VALUE_2MA: u32 = 0;
2504pub const PADS_BANK0_SWD_DRIVE_VALUE_4MA: u32 = 1;
2505pub const PADS_BANK0_SWD_DRIVE_VALUE_8MA: u32 = 2;
2506pub const PADS_BANK0_SWD_DRIVE_VALUE_12MA: u32 = 3;
2507pub const PADS_BANK0_SWD_PUE_RESET: u32 = 1;
2508pub const PADS_BANK0_SWD_PUE_BITS: u32 = 8;
2509pub const PADS_BANK0_SWD_PUE_MSB: u32 = 3;
2510pub const PADS_BANK0_SWD_PUE_LSB: u32 = 3;
2511pub const PADS_BANK0_SWD_PUE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2512pub const PADS_BANK0_SWD_PDE_RESET: u32 = 0;
2513pub const PADS_BANK0_SWD_PDE_BITS: u32 = 4;
2514pub const PADS_BANK0_SWD_PDE_MSB: u32 = 2;
2515pub const PADS_BANK0_SWD_PDE_LSB: u32 = 2;
2516pub const PADS_BANK0_SWD_PDE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2517pub const PADS_BANK0_SWD_SCHMITT_RESET: u32 = 1;
2518pub const PADS_BANK0_SWD_SCHMITT_BITS: u32 = 2;
2519pub const PADS_BANK0_SWD_SCHMITT_MSB: u32 = 1;
2520pub const PADS_BANK0_SWD_SCHMITT_LSB: u32 = 1;
2521pub const PADS_BANK0_SWD_SCHMITT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2522pub const PADS_BANK0_SWD_SLEWFAST_RESET: u32 = 0;
2523pub const PADS_BANK0_SWD_SLEWFAST_BITS: u32 = 1;
2524pub const PADS_BANK0_SWD_SLEWFAST_MSB: u32 = 0;
2525pub const PADS_BANK0_SWD_SLEWFAST_LSB: u32 = 0;
2526pub const PADS_BANK0_SWD_SLEWFAST_ACCESS: &'static [u8; 3usize] = b"RW\0";
2527pub const PARAM_ASSERTIONS_ENABLED_GPIO: u32 = 0;
2528pub const GPIO_OUT: u32 = 1;
2529pub const GPIO_IN: u32 = 0;
2530pub const N_GPIOS: u32 = 30;
2531pub const PICO_DEBUG_PIN_BASE: u32 = 19;
2532pub const PICO_DEBUG_PIN_COUNT: u32 = 3;
2533pub const UART_UARTDR_OFFSET: u32 = 0;
2534pub const UART_UARTDR_BITS: u32 = 4095;
2535pub const UART_UARTDR_RESET: u32 = 0;
2536pub const UART_UARTDR_OE_RESET: &'static [u8; 2usize] = b"-\0";
2537pub const UART_UARTDR_OE_BITS: u32 = 2048;
2538pub const UART_UARTDR_OE_MSB: u32 = 11;
2539pub const UART_UARTDR_OE_LSB: u32 = 11;
2540pub const UART_UARTDR_OE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2541pub const UART_UARTDR_BE_RESET: &'static [u8; 2usize] = b"-\0";
2542pub const UART_UARTDR_BE_BITS: u32 = 1024;
2543pub const UART_UARTDR_BE_MSB: u32 = 10;
2544pub const UART_UARTDR_BE_LSB: u32 = 10;
2545pub const UART_UARTDR_BE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2546pub const UART_UARTDR_PE_RESET: &'static [u8; 2usize] = b"-\0";
2547pub const UART_UARTDR_PE_BITS: u32 = 512;
2548pub const UART_UARTDR_PE_MSB: u32 = 9;
2549pub const UART_UARTDR_PE_LSB: u32 = 9;
2550pub const UART_UARTDR_PE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2551pub const UART_UARTDR_FE_RESET: &'static [u8; 2usize] = b"-\0";
2552pub const UART_UARTDR_FE_BITS: u32 = 256;
2553pub const UART_UARTDR_FE_MSB: u32 = 8;
2554pub const UART_UARTDR_FE_LSB: u32 = 8;
2555pub const UART_UARTDR_FE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2556pub const UART_UARTDR_DATA_RESET: &'static [u8; 2usize] = b"-\0";
2557pub const UART_UARTDR_DATA_BITS: u32 = 255;
2558pub const UART_UARTDR_DATA_MSB: u32 = 7;
2559pub const UART_UARTDR_DATA_LSB: u32 = 0;
2560pub const UART_UARTDR_DATA_ACCESS: &'static [u8; 4usize] = b"RWF\0";
2561pub const UART_UARTRSR_OFFSET: u32 = 4;
2562pub const UART_UARTRSR_BITS: u32 = 15;
2563pub const UART_UARTRSR_RESET: u32 = 0;
2564pub const UART_UARTRSR_OE_RESET: u32 = 0;
2565pub const UART_UARTRSR_OE_BITS: u32 = 8;
2566pub const UART_UARTRSR_OE_MSB: u32 = 3;
2567pub const UART_UARTRSR_OE_LSB: u32 = 3;
2568pub const UART_UARTRSR_OE_ACCESS: &'static [u8; 3usize] = b"WC\0";
2569pub const UART_UARTRSR_BE_RESET: u32 = 0;
2570pub const UART_UARTRSR_BE_BITS: u32 = 4;
2571pub const UART_UARTRSR_BE_MSB: u32 = 2;
2572pub const UART_UARTRSR_BE_LSB: u32 = 2;
2573pub const UART_UARTRSR_BE_ACCESS: &'static [u8; 3usize] = b"WC\0";
2574pub const UART_UARTRSR_PE_RESET: u32 = 0;
2575pub const UART_UARTRSR_PE_BITS: u32 = 2;
2576pub const UART_UARTRSR_PE_MSB: u32 = 1;
2577pub const UART_UARTRSR_PE_LSB: u32 = 1;
2578pub const UART_UARTRSR_PE_ACCESS: &'static [u8; 3usize] = b"WC\0";
2579pub const UART_UARTRSR_FE_RESET: u32 = 0;
2580pub const UART_UARTRSR_FE_BITS: u32 = 1;
2581pub const UART_UARTRSR_FE_MSB: u32 = 0;
2582pub const UART_UARTRSR_FE_LSB: u32 = 0;
2583pub const UART_UARTRSR_FE_ACCESS: &'static [u8; 3usize] = b"WC\0";
2584pub const UART_UARTFR_OFFSET: u32 = 24;
2585pub const UART_UARTFR_BITS: u32 = 511;
2586pub const UART_UARTFR_RESET: u32 = 144;
2587pub const UART_UARTFR_RI_RESET: &'static [u8; 2usize] = b"-\0";
2588pub const UART_UARTFR_RI_BITS: u32 = 256;
2589pub const UART_UARTFR_RI_MSB: u32 = 8;
2590pub const UART_UARTFR_RI_LSB: u32 = 8;
2591pub const UART_UARTFR_RI_ACCESS: &'static [u8; 3usize] = b"RO\0";
2592pub const UART_UARTFR_TXFE_RESET: u32 = 1;
2593pub const UART_UARTFR_TXFE_BITS: u32 = 128;
2594pub const UART_UARTFR_TXFE_MSB: u32 = 7;
2595pub const UART_UARTFR_TXFE_LSB: u32 = 7;
2596pub const UART_UARTFR_TXFE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2597pub const UART_UARTFR_RXFF_RESET: u32 = 0;
2598pub const UART_UARTFR_RXFF_BITS: u32 = 64;
2599pub const UART_UARTFR_RXFF_MSB: u32 = 6;
2600pub const UART_UARTFR_RXFF_LSB: u32 = 6;
2601pub const UART_UARTFR_RXFF_ACCESS: &'static [u8; 3usize] = b"RO\0";
2602pub const UART_UARTFR_TXFF_RESET: u32 = 0;
2603pub const UART_UARTFR_TXFF_BITS: u32 = 32;
2604pub const UART_UARTFR_TXFF_MSB: u32 = 5;
2605pub const UART_UARTFR_TXFF_LSB: u32 = 5;
2606pub const UART_UARTFR_TXFF_ACCESS: &'static [u8; 3usize] = b"RO\0";
2607pub const UART_UARTFR_RXFE_RESET: u32 = 1;
2608pub const UART_UARTFR_RXFE_BITS: u32 = 16;
2609pub const UART_UARTFR_RXFE_MSB: u32 = 4;
2610pub const UART_UARTFR_RXFE_LSB: u32 = 4;
2611pub const UART_UARTFR_RXFE_ACCESS: &'static [u8; 3usize] = b"RO\0";
2612pub const UART_UARTFR_BUSY_RESET: u32 = 0;
2613pub const UART_UARTFR_BUSY_BITS: u32 = 8;
2614pub const UART_UARTFR_BUSY_MSB: u32 = 3;
2615pub const UART_UARTFR_BUSY_LSB: u32 = 3;
2616pub const UART_UARTFR_BUSY_ACCESS: &'static [u8; 3usize] = b"RO\0";
2617pub const UART_UARTFR_DCD_RESET: &'static [u8; 2usize] = b"-\0";
2618pub const UART_UARTFR_DCD_BITS: u32 = 4;
2619pub const UART_UARTFR_DCD_MSB: u32 = 2;
2620pub const UART_UARTFR_DCD_LSB: u32 = 2;
2621pub const UART_UARTFR_DCD_ACCESS: &'static [u8; 3usize] = b"RO\0";
2622pub const UART_UARTFR_DSR_RESET: &'static [u8; 2usize] = b"-\0";
2623pub const UART_UARTFR_DSR_BITS: u32 = 2;
2624pub const UART_UARTFR_DSR_MSB: u32 = 1;
2625pub const UART_UARTFR_DSR_LSB: u32 = 1;
2626pub const UART_UARTFR_DSR_ACCESS: &'static [u8; 3usize] = b"RO\0";
2627pub const UART_UARTFR_CTS_RESET: &'static [u8; 2usize] = b"-\0";
2628pub const UART_UARTFR_CTS_BITS: u32 = 1;
2629pub const UART_UARTFR_CTS_MSB: u32 = 0;
2630pub const UART_UARTFR_CTS_LSB: u32 = 0;
2631pub const UART_UARTFR_CTS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2632pub const UART_UARTILPR_OFFSET: u32 = 32;
2633pub const UART_UARTILPR_BITS: u32 = 255;
2634pub const UART_UARTILPR_RESET: u32 = 0;
2635pub const UART_UARTILPR_ILPDVSR_RESET: u32 = 0;
2636pub const UART_UARTILPR_ILPDVSR_BITS: u32 = 255;
2637pub const UART_UARTILPR_ILPDVSR_MSB: u32 = 7;
2638pub const UART_UARTILPR_ILPDVSR_LSB: u32 = 0;
2639pub const UART_UARTILPR_ILPDVSR_ACCESS: &'static [u8; 3usize] = b"RW\0";
2640pub const UART_UARTIBRD_OFFSET: u32 = 36;
2641pub const UART_UARTIBRD_BITS: u32 = 65535;
2642pub const UART_UARTIBRD_RESET: u32 = 0;
2643pub const UART_UARTIBRD_BAUD_DIVINT_RESET: u32 = 0;
2644pub const UART_UARTIBRD_BAUD_DIVINT_BITS: u32 = 65535;
2645pub const UART_UARTIBRD_BAUD_DIVINT_MSB: u32 = 15;
2646pub const UART_UARTIBRD_BAUD_DIVINT_LSB: u32 = 0;
2647pub const UART_UARTIBRD_BAUD_DIVINT_ACCESS: &'static [u8; 3usize] = b"RW\0";
2648pub const UART_UARTFBRD_OFFSET: u32 = 40;
2649pub const UART_UARTFBRD_BITS: u32 = 63;
2650pub const UART_UARTFBRD_RESET: u32 = 0;
2651pub const UART_UARTFBRD_BAUD_DIVFRAC_RESET: u32 = 0;
2652pub const UART_UARTFBRD_BAUD_DIVFRAC_BITS: u32 = 63;
2653pub const UART_UARTFBRD_BAUD_DIVFRAC_MSB: u32 = 5;
2654pub const UART_UARTFBRD_BAUD_DIVFRAC_LSB: u32 = 0;
2655pub const UART_UARTFBRD_BAUD_DIVFRAC_ACCESS: &'static [u8; 3usize] = b"RW\0";
2656pub const UART_UARTLCR_H_OFFSET: u32 = 44;
2657pub const UART_UARTLCR_H_BITS: u32 = 255;
2658pub const UART_UARTLCR_H_RESET: u32 = 0;
2659pub const UART_UARTLCR_H_SPS_RESET: u32 = 0;
2660pub const UART_UARTLCR_H_SPS_BITS: u32 = 128;
2661pub const UART_UARTLCR_H_SPS_MSB: u32 = 7;
2662pub const UART_UARTLCR_H_SPS_LSB: u32 = 7;
2663pub const UART_UARTLCR_H_SPS_ACCESS: &'static [u8; 3usize] = b"RW\0";
2664pub const UART_UARTLCR_H_WLEN_RESET: u32 = 0;
2665pub const UART_UARTLCR_H_WLEN_BITS: u32 = 96;
2666pub const UART_UARTLCR_H_WLEN_MSB: u32 = 6;
2667pub const UART_UARTLCR_H_WLEN_LSB: u32 = 5;
2668pub const UART_UARTLCR_H_WLEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2669pub const UART_UARTLCR_H_FEN_RESET: u32 = 0;
2670pub const UART_UARTLCR_H_FEN_BITS: u32 = 16;
2671pub const UART_UARTLCR_H_FEN_MSB: u32 = 4;
2672pub const UART_UARTLCR_H_FEN_LSB: u32 = 4;
2673pub const UART_UARTLCR_H_FEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2674pub const UART_UARTLCR_H_STP2_RESET: u32 = 0;
2675pub const UART_UARTLCR_H_STP2_BITS: u32 = 8;
2676pub const UART_UARTLCR_H_STP2_MSB: u32 = 3;
2677pub const UART_UARTLCR_H_STP2_LSB: u32 = 3;
2678pub const UART_UARTLCR_H_STP2_ACCESS: &'static [u8; 3usize] = b"RW\0";
2679pub const UART_UARTLCR_H_EPS_RESET: u32 = 0;
2680pub const UART_UARTLCR_H_EPS_BITS: u32 = 4;
2681pub const UART_UARTLCR_H_EPS_MSB: u32 = 2;
2682pub const UART_UARTLCR_H_EPS_LSB: u32 = 2;
2683pub const UART_UARTLCR_H_EPS_ACCESS: &'static [u8; 3usize] = b"RW\0";
2684pub const UART_UARTLCR_H_PEN_RESET: u32 = 0;
2685pub const UART_UARTLCR_H_PEN_BITS: u32 = 2;
2686pub const UART_UARTLCR_H_PEN_MSB: u32 = 1;
2687pub const UART_UARTLCR_H_PEN_LSB: u32 = 1;
2688pub const UART_UARTLCR_H_PEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2689pub const UART_UARTLCR_H_BRK_RESET: u32 = 0;
2690pub const UART_UARTLCR_H_BRK_BITS: u32 = 1;
2691pub const UART_UARTLCR_H_BRK_MSB: u32 = 0;
2692pub const UART_UARTLCR_H_BRK_LSB: u32 = 0;
2693pub const UART_UARTLCR_H_BRK_ACCESS: &'static [u8; 3usize] = b"RW\0";
2694pub const UART_UARTCR_OFFSET: u32 = 48;
2695pub const UART_UARTCR_BITS: u32 = 65415;
2696pub const UART_UARTCR_RESET: u32 = 768;
2697pub const UART_UARTCR_CTSEN_RESET: u32 = 0;
2698pub const UART_UARTCR_CTSEN_BITS: u32 = 32768;
2699pub const UART_UARTCR_CTSEN_MSB: u32 = 15;
2700pub const UART_UARTCR_CTSEN_LSB: u32 = 15;
2701pub const UART_UARTCR_CTSEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2702pub const UART_UARTCR_RTSEN_RESET: u32 = 0;
2703pub const UART_UARTCR_RTSEN_BITS: u32 = 16384;
2704pub const UART_UARTCR_RTSEN_MSB: u32 = 14;
2705pub const UART_UARTCR_RTSEN_LSB: u32 = 14;
2706pub const UART_UARTCR_RTSEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2707pub const UART_UARTCR_OUT2_RESET: u32 = 0;
2708pub const UART_UARTCR_OUT2_BITS: u32 = 8192;
2709pub const UART_UARTCR_OUT2_MSB: u32 = 13;
2710pub const UART_UARTCR_OUT2_LSB: u32 = 13;
2711pub const UART_UARTCR_OUT2_ACCESS: &'static [u8; 3usize] = b"RW\0";
2712pub const UART_UARTCR_OUT1_RESET: u32 = 0;
2713pub const UART_UARTCR_OUT1_BITS: u32 = 4096;
2714pub const UART_UARTCR_OUT1_MSB: u32 = 12;
2715pub const UART_UARTCR_OUT1_LSB: u32 = 12;
2716pub const UART_UARTCR_OUT1_ACCESS: &'static [u8; 3usize] = b"RW\0";
2717pub const UART_UARTCR_RTS_RESET: u32 = 0;
2718pub const UART_UARTCR_RTS_BITS: u32 = 2048;
2719pub const UART_UARTCR_RTS_MSB: u32 = 11;
2720pub const UART_UARTCR_RTS_LSB: u32 = 11;
2721pub const UART_UARTCR_RTS_ACCESS: &'static [u8; 3usize] = b"RW\0";
2722pub const UART_UARTCR_DTR_RESET: u32 = 0;
2723pub const UART_UARTCR_DTR_BITS: u32 = 1024;
2724pub const UART_UARTCR_DTR_MSB: u32 = 10;
2725pub const UART_UARTCR_DTR_LSB: u32 = 10;
2726pub const UART_UARTCR_DTR_ACCESS: &'static [u8; 3usize] = b"RW\0";
2727pub const UART_UARTCR_RXE_RESET: u32 = 1;
2728pub const UART_UARTCR_RXE_BITS: u32 = 512;
2729pub const UART_UARTCR_RXE_MSB: u32 = 9;
2730pub const UART_UARTCR_RXE_LSB: u32 = 9;
2731pub const UART_UARTCR_RXE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2732pub const UART_UARTCR_TXE_RESET: u32 = 1;
2733pub const UART_UARTCR_TXE_BITS: u32 = 256;
2734pub const UART_UARTCR_TXE_MSB: u32 = 8;
2735pub const UART_UARTCR_TXE_LSB: u32 = 8;
2736pub const UART_UARTCR_TXE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2737pub const UART_UARTCR_LBE_RESET: u32 = 0;
2738pub const UART_UARTCR_LBE_BITS: u32 = 128;
2739pub const UART_UARTCR_LBE_MSB: u32 = 7;
2740pub const UART_UARTCR_LBE_LSB: u32 = 7;
2741pub const UART_UARTCR_LBE_ACCESS: &'static [u8; 3usize] = b"RW\0";
2742pub const UART_UARTCR_SIRLP_RESET: u32 = 0;
2743pub const UART_UARTCR_SIRLP_BITS: u32 = 4;
2744pub const UART_UARTCR_SIRLP_MSB: u32 = 2;
2745pub const UART_UARTCR_SIRLP_LSB: u32 = 2;
2746pub const UART_UARTCR_SIRLP_ACCESS: &'static [u8; 3usize] = b"RW\0";
2747pub const UART_UARTCR_SIREN_RESET: u32 = 0;
2748pub const UART_UARTCR_SIREN_BITS: u32 = 2;
2749pub const UART_UARTCR_SIREN_MSB: u32 = 1;
2750pub const UART_UARTCR_SIREN_LSB: u32 = 1;
2751pub const UART_UARTCR_SIREN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2752pub const UART_UARTCR_UARTEN_RESET: u32 = 0;
2753pub const UART_UARTCR_UARTEN_BITS: u32 = 1;
2754pub const UART_UARTCR_UARTEN_MSB: u32 = 0;
2755pub const UART_UARTCR_UARTEN_LSB: u32 = 0;
2756pub const UART_UARTCR_UARTEN_ACCESS: &'static [u8; 3usize] = b"RW\0";
2757pub const UART_UARTIFLS_OFFSET: u32 = 52;
2758pub const UART_UARTIFLS_BITS: u32 = 63;
2759pub const UART_UARTIFLS_RESET: u32 = 18;
2760pub const UART_UARTIFLS_RXIFLSEL_RESET: u32 = 2;
2761pub const UART_UARTIFLS_RXIFLSEL_BITS: u32 = 56;
2762pub const UART_UARTIFLS_RXIFLSEL_MSB: u32 = 5;
2763pub const UART_UARTIFLS_RXIFLSEL_LSB: u32 = 3;
2764pub const UART_UARTIFLS_RXIFLSEL_ACCESS: &'static [u8; 3usize] = b"RW\0";
2765pub const UART_UARTIFLS_TXIFLSEL_RESET: u32 = 2;
2766pub const UART_UARTIFLS_TXIFLSEL_BITS: u32 = 7;
2767pub const UART_UARTIFLS_TXIFLSEL_MSB: u32 = 2;
2768pub const UART_UARTIFLS_TXIFLSEL_LSB: u32 = 0;
2769pub const UART_UARTIFLS_TXIFLSEL_ACCESS: &'static [u8; 3usize] = b"RW\0";
2770pub const UART_UARTIMSC_OFFSET: u32 = 56;
2771pub const UART_UARTIMSC_BITS: u32 = 2047;
2772pub const UART_UARTIMSC_RESET: u32 = 0;
2773pub const UART_UARTIMSC_OEIM_RESET: u32 = 0;
2774pub const UART_UARTIMSC_OEIM_BITS: u32 = 1024;
2775pub const UART_UARTIMSC_OEIM_MSB: u32 = 10;
2776pub const UART_UARTIMSC_OEIM_LSB: u32 = 10;
2777pub const UART_UARTIMSC_OEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2778pub const UART_UARTIMSC_BEIM_RESET: u32 = 0;
2779pub const UART_UARTIMSC_BEIM_BITS: u32 = 512;
2780pub const UART_UARTIMSC_BEIM_MSB: u32 = 9;
2781pub const UART_UARTIMSC_BEIM_LSB: u32 = 9;
2782pub const UART_UARTIMSC_BEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2783pub const UART_UARTIMSC_PEIM_RESET: u32 = 0;
2784pub const UART_UARTIMSC_PEIM_BITS: u32 = 256;
2785pub const UART_UARTIMSC_PEIM_MSB: u32 = 8;
2786pub const UART_UARTIMSC_PEIM_LSB: u32 = 8;
2787pub const UART_UARTIMSC_PEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2788pub const UART_UARTIMSC_FEIM_RESET: u32 = 0;
2789pub const UART_UARTIMSC_FEIM_BITS: u32 = 128;
2790pub const UART_UARTIMSC_FEIM_MSB: u32 = 7;
2791pub const UART_UARTIMSC_FEIM_LSB: u32 = 7;
2792pub const UART_UARTIMSC_FEIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2793pub const UART_UARTIMSC_RTIM_RESET: u32 = 0;
2794pub const UART_UARTIMSC_RTIM_BITS: u32 = 64;
2795pub const UART_UARTIMSC_RTIM_MSB: u32 = 6;
2796pub const UART_UARTIMSC_RTIM_LSB: u32 = 6;
2797pub const UART_UARTIMSC_RTIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2798pub const UART_UARTIMSC_TXIM_RESET: u32 = 0;
2799pub const UART_UARTIMSC_TXIM_BITS: u32 = 32;
2800pub const UART_UARTIMSC_TXIM_MSB: u32 = 5;
2801pub const UART_UARTIMSC_TXIM_LSB: u32 = 5;
2802pub const UART_UARTIMSC_TXIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2803pub const UART_UARTIMSC_RXIM_RESET: u32 = 0;
2804pub const UART_UARTIMSC_RXIM_BITS: u32 = 16;
2805pub const UART_UARTIMSC_RXIM_MSB: u32 = 4;
2806pub const UART_UARTIMSC_RXIM_LSB: u32 = 4;
2807pub const UART_UARTIMSC_RXIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2808pub const UART_UARTIMSC_DSRMIM_RESET: u32 = 0;
2809pub const UART_UARTIMSC_DSRMIM_BITS: u32 = 8;
2810pub const UART_UARTIMSC_DSRMIM_MSB: u32 = 3;
2811pub const UART_UARTIMSC_DSRMIM_LSB: u32 = 3;
2812pub const UART_UARTIMSC_DSRMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2813pub const UART_UARTIMSC_DCDMIM_RESET: u32 = 0;
2814pub const UART_UARTIMSC_DCDMIM_BITS: u32 = 4;
2815pub const UART_UARTIMSC_DCDMIM_MSB: u32 = 2;
2816pub const UART_UARTIMSC_DCDMIM_LSB: u32 = 2;
2817pub const UART_UARTIMSC_DCDMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2818pub const UART_UARTIMSC_CTSMIM_RESET: u32 = 0;
2819pub const UART_UARTIMSC_CTSMIM_BITS: u32 = 2;
2820pub const UART_UARTIMSC_CTSMIM_MSB: u32 = 1;
2821pub const UART_UARTIMSC_CTSMIM_LSB: u32 = 1;
2822pub const UART_UARTIMSC_CTSMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2823pub const UART_UARTIMSC_RIMIM_RESET: u32 = 0;
2824pub const UART_UARTIMSC_RIMIM_BITS: u32 = 1;
2825pub const UART_UARTIMSC_RIMIM_MSB: u32 = 0;
2826pub const UART_UARTIMSC_RIMIM_LSB: u32 = 0;
2827pub const UART_UARTIMSC_RIMIM_ACCESS: &'static [u8; 3usize] = b"RW\0";
2828pub const UART_UARTRIS_OFFSET: u32 = 60;
2829pub const UART_UARTRIS_BITS: u32 = 2047;
2830pub const UART_UARTRIS_RESET: u32 = 0;
2831pub const UART_UARTRIS_OERIS_RESET: u32 = 0;
2832pub const UART_UARTRIS_OERIS_BITS: u32 = 1024;
2833pub const UART_UARTRIS_OERIS_MSB: u32 = 10;
2834pub const UART_UARTRIS_OERIS_LSB: u32 = 10;
2835pub const UART_UARTRIS_OERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2836pub const UART_UARTRIS_BERIS_RESET: u32 = 0;
2837pub const UART_UARTRIS_BERIS_BITS: u32 = 512;
2838pub const UART_UARTRIS_BERIS_MSB: u32 = 9;
2839pub const UART_UARTRIS_BERIS_LSB: u32 = 9;
2840pub const UART_UARTRIS_BERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2841pub const UART_UARTRIS_PERIS_RESET: u32 = 0;
2842pub const UART_UARTRIS_PERIS_BITS: u32 = 256;
2843pub const UART_UARTRIS_PERIS_MSB: u32 = 8;
2844pub const UART_UARTRIS_PERIS_LSB: u32 = 8;
2845pub const UART_UARTRIS_PERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2846pub const UART_UARTRIS_FERIS_RESET: u32 = 0;
2847pub const UART_UARTRIS_FERIS_BITS: u32 = 128;
2848pub const UART_UARTRIS_FERIS_MSB: u32 = 7;
2849pub const UART_UARTRIS_FERIS_LSB: u32 = 7;
2850pub const UART_UARTRIS_FERIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2851pub const UART_UARTRIS_RTRIS_RESET: u32 = 0;
2852pub const UART_UARTRIS_RTRIS_BITS: u32 = 64;
2853pub const UART_UARTRIS_RTRIS_MSB: u32 = 6;
2854pub const UART_UARTRIS_RTRIS_LSB: u32 = 6;
2855pub const UART_UARTRIS_RTRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2856pub const UART_UARTRIS_TXRIS_RESET: u32 = 0;
2857pub const UART_UARTRIS_TXRIS_BITS: u32 = 32;
2858pub const UART_UARTRIS_TXRIS_MSB: u32 = 5;
2859pub const UART_UARTRIS_TXRIS_LSB: u32 = 5;
2860pub const UART_UARTRIS_TXRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2861pub const UART_UARTRIS_RXRIS_RESET: u32 = 0;
2862pub const UART_UARTRIS_RXRIS_BITS: u32 = 16;
2863pub const UART_UARTRIS_RXRIS_MSB: u32 = 4;
2864pub const UART_UARTRIS_RXRIS_LSB: u32 = 4;
2865pub const UART_UARTRIS_RXRIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2866pub const UART_UARTRIS_DSRRMIS_RESET: &'static [u8; 2usize] = b"-\0";
2867pub const UART_UARTRIS_DSRRMIS_BITS: u32 = 8;
2868pub const UART_UARTRIS_DSRRMIS_MSB: u32 = 3;
2869pub const UART_UARTRIS_DSRRMIS_LSB: u32 = 3;
2870pub const UART_UARTRIS_DSRRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2871pub const UART_UARTRIS_DCDRMIS_RESET: &'static [u8; 2usize] = b"-\0";
2872pub const UART_UARTRIS_DCDRMIS_BITS: u32 = 4;
2873pub const UART_UARTRIS_DCDRMIS_MSB: u32 = 2;
2874pub const UART_UARTRIS_DCDRMIS_LSB: u32 = 2;
2875pub const UART_UARTRIS_DCDRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2876pub const UART_UARTRIS_CTSRMIS_RESET: &'static [u8; 2usize] = b"-\0";
2877pub const UART_UARTRIS_CTSRMIS_BITS: u32 = 2;
2878pub const UART_UARTRIS_CTSRMIS_MSB: u32 = 1;
2879pub const UART_UARTRIS_CTSRMIS_LSB: u32 = 1;
2880pub const UART_UARTRIS_CTSRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2881pub const UART_UARTRIS_RIRMIS_RESET: &'static [u8; 2usize] = b"-\0";
2882pub const UART_UARTRIS_RIRMIS_BITS: u32 = 1;
2883pub const UART_UARTRIS_RIRMIS_MSB: u32 = 0;
2884pub const UART_UARTRIS_RIRMIS_LSB: u32 = 0;
2885pub const UART_UARTRIS_RIRMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2886pub const UART_UARTMIS_OFFSET: u32 = 64;
2887pub const UART_UARTMIS_BITS: u32 = 2047;
2888pub const UART_UARTMIS_RESET: u32 = 0;
2889pub const UART_UARTMIS_OEMIS_RESET: u32 = 0;
2890pub const UART_UARTMIS_OEMIS_BITS: u32 = 1024;
2891pub const UART_UARTMIS_OEMIS_MSB: u32 = 10;
2892pub const UART_UARTMIS_OEMIS_LSB: u32 = 10;
2893pub const UART_UARTMIS_OEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2894pub const UART_UARTMIS_BEMIS_RESET: u32 = 0;
2895pub const UART_UARTMIS_BEMIS_BITS: u32 = 512;
2896pub const UART_UARTMIS_BEMIS_MSB: u32 = 9;
2897pub const UART_UARTMIS_BEMIS_LSB: u32 = 9;
2898pub const UART_UARTMIS_BEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2899pub const UART_UARTMIS_PEMIS_RESET: u32 = 0;
2900pub const UART_UARTMIS_PEMIS_BITS: u32 = 256;
2901pub const UART_UARTMIS_PEMIS_MSB: u32 = 8;
2902pub const UART_UARTMIS_PEMIS_LSB: u32 = 8;
2903pub const UART_UARTMIS_PEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2904pub const UART_UARTMIS_FEMIS_RESET: u32 = 0;
2905pub const UART_UARTMIS_FEMIS_BITS: u32 = 128;
2906pub const UART_UARTMIS_FEMIS_MSB: u32 = 7;
2907pub const UART_UARTMIS_FEMIS_LSB: u32 = 7;
2908pub const UART_UARTMIS_FEMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2909pub const UART_UARTMIS_RTMIS_RESET: u32 = 0;
2910pub const UART_UARTMIS_RTMIS_BITS: u32 = 64;
2911pub const UART_UARTMIS_RTMIS_MSB: u32 = 6;
2912pub const UART_UARTMIS_RTMIS_LSB: u32 = 6;
2913pub const UART_UARTMIS_RTMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2914pub const UART_UARTMIS_TXMIS_RESET: u32 = 0;
2915pub const UART_UARTMIS_TXMIS_BITS: u32 = 32;
2916pub const UART_UARTMIS_TXMIS_MSB: u32 = 5;
2917pub const UART_UARTMIS_TXMIS_LSB: u32 = 5;
2918pub const UART_UARTMIS_TXMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2919pub const UART_UARTMIS_RXMIS_RESET: u32 = 0;
2920pub const UART_UARTMIS_RXMIS_BITS: u32 = 16;
2921pub const UART_UARTMIS_RXMIS_MSB: u32 = 4;
2922pub const UART_UARTMIS_RXMIS_LSB: u32 = 4;
2923pub const UART_UARTMIS_RXMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2924pub const UART_UARTMIS_DSRMMIS_RESET: &'static [u8; 2usize] = b"-\0";
2925pub const UART_UARTMIS_DSRMMIS_BITS: u32 = 8;
2926pub const UART_UARTMIS_DSRMMIS_MSB: u32 = 3;
2927pub const UART_UARTMIS_DSRMMIS_LSB: u32 = 3;
2928pub const UART_UARTMIS_DSRMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2929pub const UART_UARTMIS_DCDMMIS_RESET: &'static [u8; 2usize] = b"-\0";
2930pub const UART_UARTMIS_DCDMMIS_BITS: u32 = 4;
2931pub const UART_UARTMIS_DCDMMIS_MSB: u32 = 2;
2932pub const UART_UARTMIS_DCDMMIS_LSB: u32 = 2;
2933pub const UART_UARTMIS_DCDMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2934pub const UART_UARTMIS_CTSMMIS_RESET: &'static [u8; 2usize] = b"-\0";
2935pub const UART_UARTMIS_CTSMMIS_BITS: u32 = 2;
2936pub const UART_UARTMIS_CTSMMIS_MSB: u32 = 1;
2937pub const UART_UARTMIS_CTSMMIS_LSB: u32 = 1;
2938pub const UART_UARTMIS_CTSMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2939pub const UART_UARTMIS_RIMMIS_RESET: &'static [u8; 2usize] = b"-\0";
2940pub const UART_UARTMIS_RIMMIS_BITS: u32 = 1;
2941pub const UART_UARTMIS_RIMMIS_MSB: u32 = 0;
2942pub const UART_UARTMIS_RIMMIS_LSB: u32 = 0;
2943pub const UART_UARTMIS_RIMMIS_ACCESS: &'static [u8; 3usize] = b"RO\0";
2944pub const UART_UARTICR_OFFSET: u32 = 68;
2945pub const UART_UARTICR_BITS: u32 = 2047;
2946pub const UART_UARTICR_RESET: u32 = 0;
2947pub const UART_UARTICR_OEIC_RESET: &'static [u8; 2usize] = b"-\0";
2948pub const UART_UARTICR_OEIC_BITS: u32 = 1024;
2949pub const UART_UARTICR_OEIC_MSB: u32 = 10;
2950pub const UART_UARTICR_OEIC_LSB: u32 = 10;
2951pub const UART_UARTICR_OEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2952pub const UART_UARTICR_BEIC_RESET: &'static [u8; 2usize] = b"-\0";
2953pub const UART_UARTICR_BEIC_BITS: u32 = 512;
2954pub const UART_UARTICR_BEIC_MSB: u32 = 9;
2955pub const UART_UARTICR_BEIC_LSB: u32 = 9;
2956pub const UART_UARTICR_BEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2957pub const UART_UARTICR_PEIC_RESET: &'static [u8; 2usize] = b"-\0";
2958pub const UART_UARTICR_PEIC_BITS: u32 = 256;
2959pub const UART_UARTICR_PEIC_MSB: u32 = 8;
2960pub const UART_UARTICR_PEIC_LSB: u32 = 8;
2961pub const UART_UARTICR_PEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2962pub const UART_UARTICR_FEIC_RESET: &'static [u8; 2usize] = b"-\0";
2963pub const UART_UARTICR_FEIC_BITS: u32 = 128;
2964pub const UART_UARTICR_FEIC_MSB: u32 = 7;
2965pub const UART_UARTICR_FEIC_LSB: u32 = 7;
2966pub const UART_UARTICR_FEIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2967pub const UART_UARTICR_RTIC_RESET: &'static [u8; 2usize] = b"-\0";
2968pub const UART_UARTICR_RTIC_BITS: u32 = 64;
2969pub const UART_UARTICR_RTIC_MSB: u32 = 6;
2970pub const UART_UARTICR_RTIC_LSB: u32 = 6;
2971pub const UART_UARTICR_RTIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2972pub const UART_UARTICR_TXIC_RESET: &'static [u8; 2usize] = b"-\0";
2973pub const UART_UARTICR_TXIC_BITS: u32 = 32;
2974pub const UART_UARTICR_TXIC_MSB: u32 = 5;
2975pub const UART_UARTICR_TXIC_LSB: u32 = 5;
2976pub const UART_UARTICR_TXIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2977pub const UART_UARTICR_RXIC_RESET: &'static [u8; 2usize] = b"-\0";
2978pub const UART_UARTICR_RXIC_BITS: u32 = 16;
2979pub const UART_UARTICR_RXIC_MSB: u32 = 4;
2980pub const UART_UARTICR_RXIC_LSB: u32 = 4;
2981pub const UART_UARTICR_RXIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2982pub const UART_UARTICR_DSRMIC_RESET: &'static [u8; 2usize] = b"-\0";
2983pub const UART_UARTICR_DSRMIC_BITS: u32 = 8;
2984pub const UART_UARTICR_DSRMIC_MSB: u32 = 3;
2985pub const UART_UARTICR_DSRMIC_LSB: u32 = 3;
2986pub const UART_UARTICR_DSRMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2987pub const UART_UARTICR_DCDMIC_RESET: &'static [u8; 2usize] = b"-\0";
2988pub const UART_UARTICR_DCDMIC_BITS: u32 = 4;
2989pub const UART_UARTICR_DCDMIC_MSB: u32 = 2;
2990pub const UART_UARTICR_DCDMIC_LSB: u32 = 2;
2991pub const UART_UARTICR_DCDMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2992pub const UART_UARTICR_CTSMIC_RESET: &'static [u8; 2usize] = b"-\0";
2993pub const UART_UARTICR_CTSMIC_BITS: u32 = 2;
2994pub const UART_UARTICR_CTSMIC_MSB: u32 = 1;
2995pub const UART_UARTICR_CTSMIC_LSB: u32 = 1;
2996pub const UART_UARTICR_CTSMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
2997pub const UART_UARTICR_RIMIC_RESET: &'static [u8; 2usize] = b"-\0";
2998pub const UART_UARTICR_RIMIC_BITS: u32 = 1;
2999pub const UART_UARTICR_RIMIC_MSB: u32 = 0;
3000pub const UART_UARTICR_RIMIC_LSB: u32 = 0;
3001pub const UART_UARTICR_RIMIC_ACCESS: &'static [u8; 3usize] = b"WC\0";
3002pub const UART_UARTDMACR_OFFSET: u32 = 72;
3003pub const UART_UARTDMACR_BITS: u32 = 7;
3004pub const UART_UARTDMACR_RESET: u32 = 0;
3005pub const UART_UARTDMACR_DMAONERR_RESET: u32 = 0;
3006pub const UART_UARTDMACR_DMAONERR_BITS: u32 = 4;
3007pub const UART_UARTDMACR_DMAONERR_MSB: u32 = 2;
3008pub const UART_UARTDMACR_DMAONERR_LSB: u32 = 2;
3009pub const UART_UARTDMACR_DMAONERR_ACCESS: &'static [u8; 3usize] = b"RW\0";
3010pub const UART_UARTDMACR_TXDMAE_RESET: u32 = 0;
3011pub const UART_UARTDMACR_TXDMAE_BITS: u32 = 2;
3012pub const UART_UARTDMACR_TXDMAE_MSB: u32 = 1;
3013pub const UART_UARTDMACR_TXDMAE_LSB: u32 = 1;
3014pub const UART_UARTDMACR_TXDMAE_ACCESS: &'static [u8; 3usize] = b"RW\0";
3015pub const UART_UARTDMACR_RXDMAE_RESET: u32 = 0;
3016pub const UART_UARTDMACR_RXDMAE_BITS: u32 = 1;
3017pub const UART_UARTDMACR_RXDMAE_MSB: u32 = 0;
3018pub const UART_UARTDMACR_RXDMAE_LSB: u32 = 0;
3019pub const UART_UARTDMACR_RXDMAE_ACCESS: &'static [u8; 3usize] = b"RW\0";
3020pub const UART_UARTPERIPHID0_OFFSET: u32 = 4064;
3021pub const UART_UARTPERIPHID0_BITS: u32 = 255;
3022pub const UART_UARTPERIPHID0_RESET: u32 = 17;
3023pub const UART_UARTPERIPHID0_PARTNUMBER0_RESET: u32 = 17;
3024pub const UART_UARTPERIPHID0_PARTNUMBER0_BITS: u32 = 255;
3025pub const UART_UARTPERIPHID0_PARTNUMBER0_MSB: u32 = 7;
3026pub const UART_UARTPERIPHID0_PARTNUMBER0_LSB: u32 = 0;
3027pub const UART_UARTPERIPHID0_PARTNUMBER0_ACCESS: &'static [u8; 3usize] = b"RO\0";
3028pub const UART_UARTPERIPHID1_OFFSET: u32 = 4068;
3029pub const UART_UARTPERIPHID1_BITS: u32 = 255;
3030pub const UART_UARTPERIPHID1_RESET: u32 = 16;
3031pub const UART_UARTPERIPHID1_DESIGNER0_RESET: u32 = 1;
3032pub const UART_UARTPERIPHID1_DESIGNER0_BITS: u32 = 240;
3033pub const UART_UARTPERIPHID1_DESIGNER0_MSB: u32 = 7;
3034pub const UART_UARTPERIPHID1_DESIGNER0_LSB: u32 = 4;
3035pub const UART_UARTPERIPHID1_DESIGNER0_ACCESS: &'static [u8; 3usize] = b"RO\0";
3036pub const UART_UARTPERIPHID1_PARTNUMBER1_RESET: u32 = 0;
3037pub const UART_UARTPERIPHID1_PARTNUMBER1_BITS: u32 = 15;
3038pub const UART_UARTPERIPHID1_PARTNUMBER1_MSB: u32 = 3;
3039pub const UART_UARTPERIPHID1_PARTNUMBER1_LSB: u32 = 0;
3040pub const UART_UARTPERIPHID1_PARTNUMBER1_ACCESS: &'static [u8; 3usize] = b"RO\0";
3041pub const UART_UARTPERIPHID2_OFFSET: u32 = 4072;
3042pub const UART_UARTPERIPHID2_BITS: u32 = 255;
3043pub const UART_UARTPERIPHID2_RESET: u32 = 52;
3044pub const UART_UARTPERIPHID2_REVISION_RESET: u32 = 3;
3045pub const UART_UARTPERIPHID2_REVISION_BITS: u32 = 240;
3046pub const UART_UARTPERIPHID2_REVISION_MSB: u32 = 7;
3047pub const UART_UARTPERIPHID2_REVISION_LSB: u32 = 4;
3048pub const UART_UARTPERIPHID2_REVISION_ACCESS: &'static [u8; 3usize] = b"RO\0";
3049pub const UART_UARTPERIPHID2_DESIGNER1_RESET: u32 = 4;
3050pub const UART_UARTPERIPHID2_DESIGNER1_BITS: u32 = 15;
3051pub const UART_UARTPERIPHID2_DESIGNER1_MSB: u32 = 3;
3052pub const UART_UARTPERIPHID2_DESIGNER1_LSB: u32 = 0;
3053pub const UART_UARTPERIPHID2_DESIGNER1_ACCESS: &'static [u8; 3usize] = b"RO\0";
3054pub const UART_UARTPERIPHID3_OFFSET: u32 = 4076;
3055pub const UART_UARTPERIPHID3_BITS: u32 = 255;
3056pub const UART_UARTPERIPHID3_RESET: u32 = 0;
3057pub const UART_UARTPERIPHID3_CONFIGURATION_RESET: u32 = 0;
3058pub const UART_UARTPERIPHID3_CONFIGURATION_BITS: u32 = 255;
3059pub const UART_UARTPERIPHID3_CONFIGURATION_MSB: u32 = 7;
3060pub const UART_UARTPERIPHID3_CONFIGURATION_LSB: u32 = 0;
3061pub const UART_UARTPERIPHID3_CONFIGURATION_ACCESS: &'static [u8; 3usize] = b"RO\0";
3062pub const UART_UARTPCELLID0_OFFSET: u32 = 4080;
3063pub const UART_UARTPCELLID0_BITS: u32 = 255;
3064pub const UART_UARTPCELLID0_RESET: u32 = 13;
3065pub const UART_UARTPCELLID0_UARTPCELLID0_RESET: u32 = 13;
3066pub const UART_UARTPCELLID0_UARTPCELLID0_BITS: u32 = 255;
3067pub const UART_UARTPCELLID0_UARTPCELLID0_MSB: u32 = 7;
3068pub const UART_UARTPCELLID0_UARTPCELLID0_LSB: u32 = 0;
3069pub const UART_UARTPCELLID0_UARTPCELLID0_ACCESS: &'static [u8; 3usize] = b"RO\0";
3070pub const UART_UARTPCELLID1_OFFSET: u32 = 4084;
3071pub const UART_UARTPCELLID1_BITS: u32 = 255;
3072pub const UART_UARTPCELLID1_RESET: u32 = 240;
3073pub const UART_UARTPCELLID1_UARTPCELLID1_RESET: u32 = 240;
3074pub const UART_UARTPCELLID1_UARTPCELLID1_BITS: u32 = 255;
3075pub const UART_UARTPCELLID1_UARTPCELLID1_MSB: u32 = 7;
3076pub const UART_UARTPCELLID1_UARTPCELLID1_LSB: u32 = 0;
3077pub const UART_UARTPCELLID1_UARTPCELLID1_ACCESS: &'static [u8; 3usize] = b"RO\0";
3078pub const UART_UARTPCELLID2_OFFSET: u32 = 4088;
3079pub const UART_UARTPCELLID2_BITS: u32 = 255;
3080pub const UART_UARTPCELLID2_RESET: u32 = 5;
3081pub const UART_UARTPCELLID2_UARTPCELLID2_RESET: u32 = 5;
3082pub const UART_UARTPCELLID2_UARTPCELLID2_BITS: u32 = 255;
3083pub const UART_UARTPCELLID2_UARTPCELLID2_MSB: u32 = 7;
3084pub const UART_UARTPCELLID2_UARTPCELLID2_LSB: u32 = 0;
3085pub const UART_UARTPCELLID2_UARTPCELLID2_ACCESS: &'static [u8; 3usize] = b"RO\0";
3086pub const UART_UARTPCELLID3_OFFSET: u32 = 4092;
3087pub const UART_UARTPCELLID3_BITS: u32 = 255;
3088pub const UART_UARTPCELLID3_RESET: u32 = 177;
3089pub const UART_UARTPCELLID3_UARTPCELLID3_RESET: u32 = 177;
3090pub const UART_UARTPCELLID3_UARTPCELLID3_BITS: u32 = 255;
3091pub const UART_UARTPCELLID3_UARTPCELLID3_MSB: u32 = 7;
3092pub const UART_UARTPCELLID3_UARTPCELLID3_LSB: u32 = 0;
3093pub const UART_UARTPCELLID3_UARTPCELLID3_ACCESS: &'static [u8; 3usize] = b"RO\0";
3094pub const PARAM_ASSERTIONS_ENABLED_UART: u32 = 0;
3095pub const PICO_UART_ENABLE_CRLF_SUPPORT: u32 = 1;
3096pub const PICO_UART_DEFAULT_CRLF: u32 = 0;
3097pub const PICO_DEFAULT_UART_BAUD_RATE: u32 = 115200;
3098pub type int_least8_t = i8;
3099pub type int_least16_t = i16;
3100pub type int_least32_t = i32;
3101pub type int_least64_t = i64;
3102pub type uint_least8_t = u8;
3103pub type uint_least16_t = u16;
3104pub type uint_least32_t = u32;
3105pub type uint_least64_t = u64;
3106pub type int_fast8_t = i8;
3107pub type int_fast16_t = i16;
3108pub type int_fast32_t = i32;
3109pub type int_fast64_t = i64;
3110pub type uint_fast8_t = u8;
3111pub type uint_fast16_t = u16;
3112pub type uint_fast32_t = u32;
3113pub type uint_fast64_t = u64;
3114pub type __int8_t = crate::ctypes::c_schar;
3115pub type __uint8_t = crate::ctypes::c_uchar;
3116pub type __int16_t = crate::ctypes::c_short;
3117pub type __uint16_t = crate::ctypes::c_ushort;
3118pub type __int32_t = crate::ctypes::c_int;
3119pub type __uint32_t = crate::ctypes::c_uint;
3120pub type __int64_t = crate::ctypes::c_longlong;
3121pub type __uint64_t = crate::ctypes::c_ulonglong;
3122pub type __darwin_intptr_t = crate::ctypes::c_long;
3123pub type __darwin_natural_t = crate::ctypes::c_uint;
3124pub type __darwin_ct_rune_t = crate::ctypes::c_int;
3125#[repr(C)]
3126#[derive(Debug, Copy, Clone)]
3127pub struct __mbstate_t {
3128 pub __mbstate8: __BindgenUnionField<[crate::ctypes::c_char; 128usize]>,
3129 pub _mbstateL: __BindgenUnionField<crate::ctypes::c_longlong>,
3130 pub bindgen_union_field: [u64; 16usize],
3131}
3132#[test]
3133fn bindgen_test_layout___mbstate_t() {
3134 assert_eq!(
3135 ::core::mem::size_of::<__mbstate_t>(),
3136 128usize,
3137 concat!("Size of: ", stringify!(__mbstate_t))
3138 );
3139 assert_eq!(
3140 ::core::mem::align_of::<__mbstate_t>(),
3141 8usize,
3142 concat!("Alignment of ", stringify!(__mbstate_t))
3143 );
3144 assert_eq!(
3145 unsafe { &(*(::core::ptr::null::<__mbstate_t>())).__mbstate8 as *const _ as usize },
3146 0usize,
3147 concat!(
3148 "Offset of field: ",
3149 stringify!(__mbstate_t),
3150 "::",
3151 stringify!(__mbstate8)
3152 )
3153 );
3154 assert_eq!(
3155 unsafe { &(*(::core::ptr::null::<__mbstate_t>()))._mbstateL as *const _ as usize },
3156 0usize,
3157 concat!(
3158 "Offset of field: ",
3159 stringify!(__mbstate_t),
3160 "::",
3161 stringify!(_mbstateL)
3162 )
3163 );
3164}
3165pub type __darwin_mbstate_t = __mbstate_t;
3166pub type __darwin_ptrdiff_t = crate::ctypes::c_long;
3167pub type __darwin_size_t = crate::ctypes::c_ulong;
3168pub type __darwin_va_list = __builtin_va_list;
3169pub type __darwin_wchar_t = crate::ctypes::c_int;
3170pub type __darwin_rune_t = __darwin_wchar_t;
3171pub type __darwin_wint_t = crate::ctypes::c_int;
3172pub type __darwin_clock_t = crate::ctypes::c_ulong;
3173pub type __darwin_socklen_t = __uint32_t;
3174pub type __darwin_ssize_t = crate::ctypes::c_long;
3175pub type __darwin_time_t = crate::ctypes::c_long;
3176pub type __darwin_blkcnt_t = __int64_t;
3177pub type __darwin_blksize_t = __int32_t;
3178pub type __darwin_dev_t = __int32_t;
3179pub type __darwin_fsblkcnt_t = crate::ctypes::c_uint;
3180pub type __darwin_fsfilcnt_t = crate::ctypes::c_uint;
3181pub type __darwin_gid_t = __uint32_t;
3182pub type __darwin_id_t = __uint32_t;
3183pub type __darwin_ino64_t = __uint64_t;
3184pub type __darwin_ino_t = __darwin_ino64_t;
3185pub type __darwin_mach_port_name_t = __darwin_natural_t;
3186pub type __darwin_mach_port_t = __darwin_mach_port_name_t;
3187pub type __darwin_mode_t = __uint16_t;
3188pub type __darwin_off_t = __int64_t;
3189pub type __darwin_pid_t = __int32_t;
3190pub type __darwin_sigset_t = __uint32_t;
3191pub type __darwin_suseconds_t = __int32_t;
3192pub type __darwin_uid_t = __uint32_t;
3193pub type __darwin_useconds_t = __uint32_t;
3194pub type __darwin_uuid_t = [crate::ctypes::c_uchar; 16usize];
3195pub type __darwin_uuid_string_t = [crate::ctypes::c_char; 37usize];
3196#[repr(C)]
3197#[derive(Debug, Copy, Clone)]
3198pub struct __darwin_pthread_handler_rec {
3199 pub __routine: ::core::option::Option<unsafe extern "C" fn(arg1: *mut crate::ctypes::c_void)>,
3200 pub __arg: *mut crate::ctypes::c_void,
3201 pub __next: *mut __darwin_pthread_handler_rec,
3202}
3203#[test]
3204fn bindgen_test_layout___darwin_pthread_handler_rec() {
3205 assert_eq!(
3206 ::core::mem::size_of::<__darwin_pthread_handler_rec>(),
3207 24usize,
3208 concat!("Size of: ", stringify!(__darwin_pthread_handler_rec))
3209 );
3210 assert_eq!(
3211 ::core::mem::align_of::<__darwin_pthread_handler_rec>(),
3212 8usize,
3213 concat!("Alignment of ", stringify!(__darwin_pthread_handler_rec))
3214 );
3215 assert_eq!(
3216 unsafe {
3217 &(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__routine as *const _ as usize
3218 },
3219 0usize,
3220 concat!(
3221 "Offset of field: ",
3222 stringify!(__darwin_pthread_handler_rec),
3223 "::",
3224 stringify!(__routine)
3225 )
3226 );
3227 assert_eq!(
3228 unsafe {
3229 &(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__arg as *const _ as usize
3230 },
3231 8usize,
3232 concat!(
3233 "Offset of field: ",
3234 stringify!(__darwin_pthread_handler_rec),
3235 "::",
3236 stringify!(__arg)
3237 )
3238 );
3239 assert_eq!(
3240 unsafe {
3241 &(*(::core::ptr::null::<__darwin_pthread_handler_rec>())).__next as *const _ as usize
3242 },
3243 16usize,
3244 concat!(
3245 "Offset of field: ",
3246 stringify!(__darwin_pthread_handler_rec),
3247 "::",
3248 stringify!(__next)
3249 )
3250 );
3251}
3252#[repr(C)]
3253#[derive(Copy, Clone)]
3254pub struct _opaque_pthread_attr_t {
3255 pub __sig: crate::ctypes::c_long,
3256 pub __opaque: [crate::ctypes::c_char; 56usize],
3257}
3258#[test]
3259fn bindgen_test_layout__opaque_pthread_attr_t() {
3260 assert_eq!(
3261 ::core::mem::size_of::<_opaque_pthread_attr_t>(),
3262 64usize,
3263 concat!("Size of: ", stringify!(_opaque_pthread_attr_t))
3264 );
3265 assert_eq!(
3266 ::core::mem::align_of::<_opaque_pthread_attr_t>(),
3267 8usize,
3268 concat!("Alignment of ", stringify!(_opaque_pthread_attr_t))
3269 );
3270 assert_eq!(
3271 unsafe { &(*(::core::ptr::null::<_opaque_pthread_attr_t>())).__sig as *const _ as usize },
3272 0usize,
3273 concat!(
3274 "Offset of field: ",
3275 stringify!(_opaque_pthread_attr_t),
3276 "::",
3277 stringify!(__sig)
3278 )
3279 );
3280 assert_eq!(
3281 unsafe {
3282 &(*(::core::ptr::null::<_opaque_pthread_attr_t>())).__opaque as *const _ as usize
3283 },
3284 8usize,
3285 concat!(
3286 "Offset of field: ",
3287 stringify!(_opaque_pthread_attr_t),
3288 "::",
3289 stringify!(__opaque)
3290 )
3291 );
3292}
3293#[repr(C)]
3294#[derive(Copy, Clone)]
3295pub struct _opaque_pthread_cond_t {
3296 pub __sig: crate::ctypes::c_long,
3297 pub __opaque: [crate::ctypes::c_char; 40usize],
3298}
3299#[test]
3300fn bindgen_test_layout__opaque_pthread_cond_t() {
3301 assert_eq!(
3302 ::core::mem::size_of::<_opaque_pthread_cond_t>(),
3303 48usize,
3304 concat!("Size of: ", stringify!(_opaque_pthread_cond_t))
3305 );
3306 assert_eq!(
3307 ::core::mem::align_of::<_opaque_pthread_cond_t>(),
3308 8usize,
3309 concat!("Alignment of ", stringify!(_opaque_pthread_cond_t))
3310 );
3311 assert_eq!(
3312 unsafe { &(*(::core::ptr::null::<_opaque_pthread_cond_t>())).__sig as *const _ as usize },
3313 0usize,
3314 concat!(
3315 "Offset of field: ",
3316 stringify!(_opaque_pthread_cond_t),
3317 "::",
3318 stringify!(__sig)
3319 )
3320 );
3321 assert_eq!(
3322 unsafe {
3323 &(*(::core::ptr::null::<_opaque_pthread_cond_t>())).__opaque as *const _ as usize
3324 },
3325 8usize,
3326 concat!(
3327 "Offset of field: ",
3328 stringify!(_opaque_pthread_cond_t),
3329 "::",
3330 stringify!(__opaque)
3331 )
3332 );
3333}
3334#[repr(C)]
3335#[derive(Debug, Copy, Clone)]
3336pub struct _opaque_pthread_condattr_t {
3337 pub __sig: crate::ctypes::c_long,
3338 pub __opaque: [crate::ctypes::c_char; 8usize],
3339}
3340#[test]
3341fn bindgen_test_layout__opaque_pthread_condattr_t() {
3342 assert_eq!(
3343 ::core::mem::size_of::<_opaque_pthread_condattr_t>(),
3344 16usize,
3345 concat!("Size of: ", stringify!(_opaque_pthread_condattr_t))
3346 );
3347 assert_eq!(
3348 ::core::mem::align_of::<_opaque_pthread_condattr_t>(),
3349 8usize,
3350 concat!("Alignment of ", stringify!(_opaque_pthread_condattr_t))
3351 );
3352 assert_eq!(
3353 unsafe {
3354 &(*(::core::ptr::null::<_opaque_pthread_condattr_t>())).__sig as *const _ as usize
3355 },
3356 0usize,
3357 concat!(
3358 "Offset of field: ",
3359 stringify!(_opaque_pthread_condattr_t),
3360 "::",
3361 stringify!(__sig)
3362 )
3363 );
3364 assert_eq!(
3365 unsafe {
3366 &(*(::core::ptr::null::<_opaque_pthread_condattr_t>())).__opaque as *const _ as usize
3367 },
3368 8usize,
3369 concat!(
3370 "Offset of field: ",
3371 stringify!(_opaque_pthread_condattr_t),
3372 "::",
3373 stringify!(__opaque)
3374 )
3375 );
3376}
3377#[repr(C)]
3378#[derive(Copy, Clone)]
3379pub struct _opaque_pthread_mutex_t {
3380 pub __sig: crate::ctypes::c_long,
3381 pub __opaque: [crate::ctypes::c_char; 56usize],
3382}
3383#[test]
3384fn bindgen_test_layout__opaque_pthread_mutex_t() {
3385 assert_eq!(
3386 ::core::mem::size_of::<_opaque_pthread_mutex_t>(),
3387 64usize,
3388 concat!("Size of: ", stringify!(_opaque_pthread_mutex_t))
3389 );
3390 assert_eq!(
3391 ::core::mem::align_of::<_opaque_pthread_mutex_t>(),
3392 8usize,
3393 concat!("Alignment of ", stringify!(_opaque_pthread_mutex_t))
3394 );
3395 assert_eq!(
3396 unsafe { &(*(::core::ptr::null::<_opaque_pthread_mutex_t>())).__sig as *const _ as usize },
3397 0usize,
3398 concat!(
3399 "Offset of field: ",
3400 stringify!(_opaque_pthread_mutex_t),
3401 "::",
3402 stringify!(__sig)
3403 )
3404 );
3405 assert_eq!(
3406 unsafe {
3407 &(*(::core::ptr::null::<_opaque_pthread_mutex_t>())).__opaque as *const _ as usize
3408 },
3409 8usize,
3410 concat!(
3411 "Offset of field: ",
3412 stringify!(_opaque_pthread_mutex_t),
3413 "::",
3414 stringify!(__opaque)
3415 )
3416 );
3417}
3418#[repr(C)]
3419#[derive(Debug, Copy, Clone)]
3420pub struct _opaque_pthread_mutexattr_t {
3421 pub __sig: crate::ctypes::c_long,
3422 pub __opaque: [crate::ctypes::c_char; 8usize],
3423}
3424#[test]
3425fn bindgen_test_layout__opaque_pthread_mutexattr_t() {
3426 assert_eq!(
3427 ::core::mem::size_of::<_opaque_pthread_mutexattr_t>(),
3428 16usize,
3429 concat!("Size of: ", stringify!(_opaque_pthread_mutexattr_t))
3430 );
3431 assert_eq!(
3432 ::core::mem::align_of::<_opaque_pthread_mutexattr_t>(),
3433 8usize,
3434 concat!("Alignment of ", stringify!(_opaque_pthread_mutexattr_t))
3435 );
3436 assert_eq!(
3437 unsafe {
3438 &(*(::core::ptr::null::<_opaque_pthread_mutexattr_t>())).__sig as *const _ as usize
3439 },
3440 0usize,
3441 concat!(
3442 "Offset of field: ",
3443 stringify!(_opaque_pthread_mutexattr_t),
3444 "::",
3445 stringify!(__sig)
3446 )
3447 );
3448 assert_eq!(
3449 unsafe {
3450 &(*(::core::ptr::null::<_opaque_pthread_mutexattr_t>())).__opaque as *const _ as usize
3451 },
3452 8usize,
3453 concat!(
3454 "Offset of field: ",
3455 stringify!(_opaque_pthread_mutexattr_t),
3456 "::",
3457 stringify!(__opaque)
3458 )
3459 );
3460}
3461#[repr(C)]
3462#[derive(Debug, Copy, Clone)]
3463pub struct _opaque_pthread_once_t {
3464 pub __sig: crate::ctypes::c_long,
3465 pub __opaque: [crate::ctypes::c_char; 8usize],
3466}
3467#[test]
3468fn bindgen_test_layout__opaque_pthread_once_t() {
3469 assert_eq!(
3470 ::core::mem::size_of::<_opaque_pthread_once_t>(),
3471 16usize,
3472 concat!("Size of: ", stringify!(_opaque_pthread_once_t))
3473 );
3474 assert_eq!(
3475 ::core::mem::align_of::<_opaque_pthread_once_t>(),
3476 8usize,
3477 concat!("Alignment of ", stringify!(_opaque_pthread_once_t))
3478 );
3479 assert_eq!(
3480 unsafe { &(*(::core::ptr::null::<_opaque_pthread_once_t>())).__sig as *const _ as usize },
3481 0usize,
3482 concat!(
3483 "Offset of field: ",
3484 stringify!(_opaque_pthread_once_t),
3485 "::",
3486 stringify!(__sig)
3487 )
3488 );
3489 assert_eq!(
3490 unsafe {
3491 &(*(::core::ptr::null::<_opaque_pthread_once_t>())).__opaque as *const _ as usize
3492 },
3493 8usize,
3494 concat!(
3495 "Offset of field: ",
3496 stringify!(_opaque_pthread_once_t),
3497 "::",
3498 stringify!(__opaque)
3499 )
3500 );
3501}
3502#[repr(C)]
3503#[derive(Copy, Clone)]
3504pub struct _opaque_pthread_rwlock_t {
3505 pub __sig: crate::ctypes::c_long,
3506 pub __opaque: [crate::ctypes::c_char; 192usize],
3507}
3508#[test]
3509fn bindgen_test_layout__opaque_pthread_rwlock_t() {
3510 assert_eq!(
3511 ::core::mem::size_of::<_opaque_pthread_rwlock_t>(),
3512 200usize,
3513 concat!("Size of: ", stringify!(_opaque_pthread_rwlock_t))
3514 );
3515 assert_eq!(
3516 ::core::mem::align_of::<_opaque_pthread_rwlock_t>(),
3517 8usize,
3518 concat!("Alignment of ", stringify!(_opaque_pthread_rwlock_t))
3519 );
3520 assert_eq!(
3521 unsafe { &(*(::core::ptr::null::<_opaque_pthread_rwlock_t>())).__sig as *const _ as usize },
3522 0usize,
3523 concat!(
3524 "Offset of field: ",
3525 stringify!(_opaque_pthread_rwlock_t),
3526 "::",
3527 stringify!(__sig)
3528 )
3529 );
3530 assert_eq!(
3531 unsafe {
3532 &(*(::core::ptr::null::<_opaque_pthread_rwlock_t>())).__opaque as *const _ as usize
3533 },
3534 8usize,
3535 concat!(
3536 "Offset of field: ",
3537 stringify!(_opaque_pthread_rwlock_t),
3538 "::",
3539 stringify!(__opaque)
3540 )
3541 );
3542}
3543#[repr(C)]
3544#[derive(Debug, Copy, Clone)]
3545pub struct _opaque_pthread_rwlockattr_t {
3546 pub __sig: crate::ctypes::c_long,
3547 pub __opaque: [crate::ctypes::c_char; 16usize],
3548}
3549#[test]
3550fn bindgen_test_layout__opaque_pthread_rwlockattr_t() {
3551 assert_eq!(
3552 ::core::mem::size_of::<_opaque_pthread_rwlockattr_t>(),
3553 24usize,
3554 concat!("Size of: ", stringify!(_opaque_pthread_rwlockattr_t))
3555 );
3556 assert_eq!(
3557 ::core::mem::align_of::<_opaque_pthread_rwlockattr_t>(),
3558 8usize,
3559 concat!("Alignment of ", stringify!(_opaque_pthread_rwlockattr_t))
3560 );
3561 assert_eq!(
3562 unsafe {
3563 &(*(::core::ptr::null::<_opaque_pthread_rwlockattr_t>())).__sig as *const _ as usize
3564 },
3565 0usize,
3566 concat!(
3567 "Offset of field: ",
3568 stringify!(_opaque_pthread_rwlockattr_t),
3569 "::",
3570 stringify!(__sig)
3571 )
3572 );
3573 assert_eq!(
3574 unsafe {
3575 &(*(::core::ptr::null::<_opaque_pthread_rwlockattr_t>())).__opaque as *const _ as usize
3576 },
3577 8usize,
3578 concat!(
3579 "Offset of field: ",
3580 stringify!(_opaque_pthread_rwlockattr_t),
3581 "::",
3582 stringify!(__opaque)
3583 )
3584 );
3585}
3586#[repr(C)]
3587#[derive(Copy, Clone)]
3588pub struct _opaque_pthread_t {
3589 pub __sig: crate::ctypes::c_long,
3590 pub __cleanup_stack: *mut __darwin_pthread_handler_rec,
3591 pub __opaque: [crate::ctypes::c_char; 8176usize],
3592}
3593#[test]
3594fn bindgen_test_layout__opaque_pthread_t() {
3595 assert_eq!(
3596 ::core::mem::size_of::<_opaque_pthread_t>(),
3597 8192usize,
3598 concat!("Size of: ", stringify!(_opaque_pthread_t))
3599 );
3600 assert_eq!(
3601 ::core::mem::align_of::<_opaque_pthread_t>(),
3602 8usize,
3603 concat!("Alignment of ", stringify!(_opaque_pthread_t))
3604 );
3605 assert_eq!(
3606 unsafe { &(*(::core::ptr::null::<_opaque_pthread_t>())).__sig as *const _ as usize },
3607 0usize,
3608 concat!(
3609 "Offset of field: ",
3610 stringify!(_opaque_pthread_t),
3611 "::",
3612 stringify!(__sig)
3613 )
3614 );
3615 assert_eq!(
3616 unsafe {
3617 &(*(::core::ptr::null::<_opaque_pthread_t>())).__cleanup_stack as *const _ as usize
3618 },
3619 8usize,
3620 concat!(
3621 "Offset of field: ",
3622 stringify!(_opaque_pthread_t),
3623 "::",
3624 stringify!(__cleanup_stack)
3625 )
3626 );
3627 assert_eq!(
3628 unsafe { &(*(::core::ptr::null::<_opaque_pthread_t>())).__opaque as *const _ as usize },
3629 16usize,
3630 concat!(
3631 "Offset of field: ",
3632 stringify!(_opaque_pthread_t),
3633 "::",
3634 stringify!(__opaque)
3635 )
3636 );
3637}
3638pub type __darwin_pthread_attr_t = _opaque_pthread_attr_t;
3639pub type __darwin_pthread_cond_t = _opaque_pthread_cond_t;
3640pub type __darwin_pthread_condattr_t = _opaque_pthread_condattr_t;
3641pub type __darwin_pthread_key_t = crate::ctypes::c_ulong;
3642pub type __darwin_pthread_mutex_t = _opaque_pthread_mutex_t;
3643pub type __darwin_pthread_mutexattr_t = _opaque_pthread_mutexattr_t;
3644pub type __darwin_pthread_once_t = _opaque_pthread_once_t;
3645pub type __darwin_pthread_rwlock_t = _opaque_pthread_rwlock_t;
3646pub type __darwin_pthread_rwlockattr_t = _opaque_pthread_rwlockattr_t;
3647pub type __darwin_pthread_t = *mut _opaque_pthread_t;
3648pub type u_int8_t = crate::ctypes::c_uchar;
3649pub type u_int16_t = crate::ctypes::c_ushort;
3650pub type u_int32_t = crate::ctypes::c_uint;
3651pub type u_int64_t = crate::ctypes::c_ulonglong;
3652pub type register_t = i64;
3653pub type user_addr_t = u_int64_t;
3654pub type user_size_t = u_int64_t;
3655pub type user_ssize_t = i64;
3656pub type user_long_t = i64;
3657pub type user_ulong_t = u_int64_t;
3658pub type user_time_t = i64;
3659pub type user_off_t = i64;
3660pub type syscall_arg_t = u_int64_t;
3661pub type intmax_t = crate::ctypes::c_long;
3662pub type uintmax_t = crate::ctypes::c_ulong;
3663pub type size_t = crate::ctypes::c_ulong;
3664pub type rsize_t = crate::ctypes::c_ulong;
3665pub type wchar_t = crate::ctypes::c_int;
3666pub type max_align_t = u128;
3667pub type uint = crate::ctypes::c_uint;
3668#[repr(C)]
3669#[derive(Debug, Copy, Clone)]
3670pub struct absolute_time_t {
3671 pub _private_us_since_boot: u64,
3672}
3673#[test]
3674fn bindgen_test_layout_absolute_time_t() {
3675 assert_eq!(
3676 ::core::mem::size_of::<absolute_time_t>(),
3677 8usize,
3678 concat!("Size of: ", stringify!(absolute_time_t))
3679 );
3680 assert_eq!(
3681 ::core::mem::align_of::<absolute_time_t>(),
3682 8usize,
3683 concat!("Alignment of ", stringify!(absolute_time_t))
3684 );
3685 assert_eq!(
3686 unsafe {
3687 &(*(::core::ptr::null::<absolute_time_t>()))._private_us_since_boot as *const _ as usize
3688 },
3689 0usize,
3690 concat!(
3691 "Offset of field: ",
3692 stringify!(absolute_time_t),
3693 "::",
3694 stringify!(_private_us_since_boot)
3695 )
3696 );
3697}
3698#[doc = " \\struct datetime_t"]
3699#[doc = " \\ingroup util_datetime"]
3700#[doc = " \\brief Structure containing date and time information"]
3701#[doc = ""]
3702#[doc = " When setting an RTC alarm, set a field to -1 tells"]
3703#[doc = " the RTC to not match on this field"]
3704#[repr(C)]
3705#[derive(Debug, Copy, Clone)]
3706pub struct datetime_t {
3707 #[doc = "< 0..4095"]
3708 pub year: i16,
3709 #[doc = "< 1..12, 1 is January"]
3710 pub month: i8,
3711 #[doc = "< 1..28,29,30,31 depending on month"]
3712 pub day: i8,
3713 #[doc = "< 0..6, 0 is Sunday"]
3714 pub dotw: i8,
3715 #[doc = "< 0..23"]
3716 pub hour: i8,
3717 #[doc = "< 0..59"]
3718 pub min: i8,
3719 #[doc = "< 0..59"]
3720 pub sec: i8,
3721}
3722#[test]
3723fn bindgen_test_layout_datetime_t() {
3724 assert_eq!(
3725 ::core::mem::size_of::<datetime_t>(),
3726 8usize,
3727 concat!("Size of: ", stringify!(datetime_t))
3728 );
3729 assert_eq!(
3730 ::core::mem::align_of::<datetime_t>(),
3731 2usize,
3732 concat!("Alignment of ", stringify!(datetime_t))
3733 );
3734 assert_eq!(
3735 unsafe { &(*(::core::ptr::null::<datetime_t>())).year as *const _ as usize },
3736 0usize,
3737 concat!(
3738 "Offset of field: ",
3739 stringify!(datetime_t),
3740 "::",
3741 stringify!(year)
3742 )
3743 );
3744 assert_eq!(
3745 unsafe { &(*(::core::ptr::null::<datetime_t>())).month as *const _ as usize },
3746 2usize,
3747 concat!(
3748 "Offset of field: ",
3749 stringify!(datetime_t),
3750 "::",
3751 stringify!(month)
3752 )
3753 );
3754 assert_eq!(
3755 unsafe { &(*(::core::ptr::null::<datetime_t>())).day as *const _ as usize },
3756 3usize,
3757 concat!(
3758 "Offset of field: ",
3759 stringify!(datetime_t),
3760 "::",
3761 stringify!(day)
3762 )
3763 );
3764 assert_eq!(
3765 unsafe { &(*(::core::ptr::null::<datetime_t>())).dotw as *const _ as usize },
3766 4usize,
3767 concat!(
3768 "Offset of field: ",
3769 stringify!(datetime_t),
3770 "::",
3771 stringify!(dotw)
3772 )
3773 );
3774 assert_eq!(
3775 unsafe { &(*(::core::ptr::null::<datetime_t>())).hour as *const _ as usize },
3776 5usize,
3777 concat!(
3778 "Offset of field: ",
3779 stringify!(datetime_t),
3780 "::",
3781 stringify!(hour)
3782 )
3783 );
3784 assert_eq!(
3785 unsafe { &(*(::core::ptr::null::<datetime_t>())).min as *const _ as usize },
3786 6usize,
3787 concat!(
3788 "Offset of field: ",
3789 stringify!(datetime_t),
3790 "::",
3791 stringify!(min)
3792 )
3793 );
3794 assert_eq!(
3795 unsafe { &(*(::core::ptr::null::<datetime_t>())).sec as *const _ as usize },
3796 7usize,
3797 concat!(
3798 "Offset of field: ",
3799 stringify!(datetime_t),
3800 "::",
3801 stringify!(sec)
3802 )
3803 );
3804}
3805extern "C" {
3806 pub fn panic_unsupported();
3807}
3808extern "C" {
3809 pub fn panic(fmt: *const crate::ctypes::c_char, ...);
3810}
3811extern "C" {
3812 pub fn running_on_fpga() -> bool;
3813}
3814extern "C" {
3815 pub fn rp2040_chip_version() -> u8;
3816}
3817extern "C" {
3818 pub fn __assert_rtn(
3819 arg1: *const crate::ctypes::c_char,
3820 arg2: *const crate::ctypes::c_char,
3821 arg3: crate::ctypes::c_int,
3822 arg4: *const crate::ctypes::c_char,
3823 );
3824}
3825pub const PICO_OK: crate::ctypes::c_int = 0;
3826pub const PICO_ERROR_NONE: crate::ctypes::c_int = 0;
3827pub const PICO_ERROR_TIMEOUT: crate::ctypes::c_int = -1;
3828pub const PICO_ERROR_GENERIC: crate::ctypes::c_int = -2;
3829pub const PICO_ERROR_NO_DATA: crate::ctypes::c_int = -3;
3830#[doc = " Common return codes from pico_sdk methods that return a status"]
3831pub type _bindgen_ty_1 = crate::ctypes::c_int;
3832#[repr(C)]
3833#[derive(Debug, Copy, Clone)]
3834pub struct stdio_driver {
3835 _unused: [u8; 0],
3836}
3837pub type stdio_driver_t = stdio_driver;
3838extern "C" {
3839 #[doc = " \\brief Initialize all of the present standard stdio types that are linked into the binary."]
3840 #[doc = " \\ingroup pico_stdio"]
3841 #[doc = ""]
3842 #[doc = " Call this method once you have set up your clocks to enable the stdio support for UART, USB"]
3843 #[doc = " and semihosting based on the presence of the respective librariess in the binary."]
3844 #[doc = ""]
3845 #[doc = " \\see stdio_uart, stdio_usb, stdio_semihosting"]
3846 pub fn stdio_init_all();
3847}
3848extern "C" {
3849 #[doc = " \\brief Initialize all of the present standard stdio types that are linked into the binary."]
3850 #[doc = " \\ingroup pico_stdio"]
3851 #[doc = ""]
3852 #[doc = " Call this method once you have set up your clocks to enable the stdio support for UART, USB"]
3853 #[doc = " and semihosting based on the presence of the respective librariess in the binary."]
3854 #[doc = ""]
3855 #[doc = " \\see stdio_uart, stdio_usb, stdio_semihosting"]
3856 pub fn stdio_flush();
3857}
3858extern "C" {
3859 #[doc = " \\brief Return a character from stdin if there is one available within a timeout"]
3860 #[doc = " \\ingroup pico_stdio"]
3861 #[doc = ""]
3862 #[doc = " \\param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available."]
3863 #[doc = " \\return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs"]
3864 pub fn getchar_timeout_us(timeout_us: u32) -> crate::ctypes::c_int;
3865}
3866extern "C" {
3867 #[doc = " \\brief Adds or removes a driver from the list of active drivers used for input/output"]
3868 #[doc = " \\ingroup pico_stdio"]
3869 #[doc = ""]
3870 #[doc = " \\note this method should always be called on an initialized driver"]
3871 #[doc = " \\param driver the driver"]
3872 #[doc = " \\param enabled true to add, false to remove"]
3873 pub fn stdio_set_driver_enabled(driver: *mut stdio_driver_t, enabled: bool);
3874}
3875extern "C" {
3876 #[doc = " \\brief Control limiting of output to a single driver"]
3877 #[doc = " \\ingroup pico_stdio"]
3878 #[doc = ""]
3879 #[doc = " \\note this method should always be called on an initialized driver"]
3880 #[doc = ""]
3881 #[doc = " \\param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers)."]
3882 #[doc = " if NULL then all enabled drivers will be used"]
3883 pub fn stdio_filter_driver(driver: *mut stdio_driver_t);
3884}
3885extern "C" {
3886 #[doc = " \\brief control conversion of line feeds to carriage return on transmissions"]
3887 #[doc = " \\ingroup pico_stdio"]
3888 #[doc = ""]
3889 #[doc = " \\note this method should always be called on an initialized driver"]
3890 #[doc = ""]
3891 #[doc = " \\param driver the driver"]
3892 #[doc = " \\param translate If true, convert line feeds to carriage return on transmissions"]
3893 pub fn stdio_set_translate_crlf(driver: *mut stdio_driver_t, translate: bool);
3894}
3895pub type io_rw_32 = u32;
3896pub type io_ro_32 = u32;
3897pub type io_wo_32 = u32;
3898pub type io_rw_16 = u16;
3899pub type io_ro_16 = u16;
3900pub type io_wo_16 = u16;
3901pub type io_rw_8 = u8;
3902pub type io_ro_8 = u8;
3903pub type io_wo_8 = u8;
3904pub type ioptr = *mut u8;
3905pub type const_ioptr = ioptr;
3906#[repr(C)]
3907#[derive(Debug, Copy, Clone)]
3908pub struct timer_hw_t {
3909 pub timehw: io_wo_32,
3910 pub timelw: io_wo_32,
3911 pub timehr: io_ro_32,
3912 pub timelr: io_ro_32,
3913 pub alarm: [io_rw_32; 4usize],
3914 pub armed: io_rw_32,
3915 pub timerawh: io_ro_32,
3916 pub timerawl: io_ro_32,
3917 pub dbgpause: io_rw_32,
3918 pub pause: io_rw_32,
3919 pub intr: io_rw_32,
3920 pub inte: io_rw_32,
3921 pub intf: io_rw_32,
3922 pub ints: io_ro_32,
3923}
3924#[test]
3925fn bindgen_test_layout_timer_hw_t() {
3926 assert_eq!(
3927 ::core::mem::size_of::<timer_hw_t>(),
3928 68usize,
3929 concat!("Size of: ", stringify!(timer_hw_t))
3930 );
3931 assert_eq!(
3932 ::core::mem::align_of::<timer_hw_t>(),
3933 4usize,
3934 concat!("Alignment of ", stringify!(timer_hw_t))
3935 );
3936 assert_eq!(
3937 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timehw as *const _ as usize },
3938 0usize,
3939 concat!(
3940 "Offset of field: ",
3941 stringify!(timer_hw_t),
3942 "::",
3943 stringify!(timehw)
3944 )
3945 );
3946 assert_eq!(
3947 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timelw as *const _ as usize },
3948 4usize,
3949 concat!(
3950 "Offset of field: ",
3951 stringify!(timer_hw_t),
3952 "::",
3953 stringify!(timelw)
3954 )
3955 );
3956 assert_eq!(
3957 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timehr as *const _ as usize },
3958 8usize,
3959 concat!(
3960 "Offset of field: ",
3961 stringify!(timer_hw_t),
3962 "::",
3963 stringify!(timehr)
3964 )
3965 );
3966 assert_eq!(
3967 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timelr as *const _ as usize },
3968 12usize,
3969 concat!(
3970 "Offset of field: ",
3971 stringify!(timer_hw_t),
3972 "::",
3973 stringify!(timelr)
3974 )
3975 );
3976 assert_eq!(
3977 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).alarm as *const _ as usize },
3978 16usize,
3979 concat!(
3980 "Offset of field: ",
3981 stringify!(timer_hw_t),
3982 "::",
3983 stringify!(alarm)
3984 )
3985 );
3986 assert_eq!(
3987 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).armed as *const _ as usize },
3988 32usize,
3989 concat!(
3990 "Offset of field: ",
3991 stringify!(timer_hw_t),
3992 "::",
3993 stringify!(armed)
3994 )
3995 );
3996 assert_eq!(
3997 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timerawh as *const _ as usize },
3998 36usize,
3999 concat!(
4000 "Offset of field: ",
4001 stringify!(timer_hw_t),
4002 "::",
4003 stringify!(timerawh)
4004 )
4005 );
4006 assert_eq!(
4007 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).timerawl as *const _ as usize },
4008 40usize,
4009 concat!(
4010 "Offset of field: ",
4011 stringify!(timer_hw_t),
4012 "::",
4013 stringify!(timerawl)
4014 )
4015 );
4016 assert_eq!(
4017 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).dbgpause as *const _ as usize },
4018 44usize,
4019 concat!(
4020 "Offset of field: ",
4021 stringify!(timer_hw_t),
4022 "::",
4023 stringify!(dbgpause)
4024 )
4025 );
4026 assert_eq!(
4027 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).pause as *const _ as usize },
4028 48usize,
4029 concat!(
4030 "Offset of field: ",
4031 stringify!(timer_hw_t),
4032 "::",
4033 stringify!(pause)
4034 )
4035 );
4036 assert_eq!(
4037 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).intr as *const _ as usize },
4038 52usize,
4039 concat!(
4040 "Offset of field: ",
4041 stringify!(timer_hw_t),
4042 "::",
4043 stringify!(intr)
4044 )
4045 );
4046 assert_eq!(
4047 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).inte as *const _ as usize },
4048 56usize,
4049 concat!(
4050 "Offset of field: ",
4051 stringify!(timer_hw_t),
4052 "::",
4053 stringify!(inte)
4054 )
4055 );
4056 assert_eq!(
4057 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).intf as *const _ as usize },
4058 60usize,
4059 concat!(
4060 "Offset of field: ",
4061 stringify!(timer_hw_t),
4062 "::",
4063 stringify!(intf)
4064 )
4065 );
4066 assert_eq!(
4067 unsafe { &(*(::core::ptr::null::<timer_hw_t>())).ints as *const _ as usize },
4068 64usize,
4069 concat!(
4070 "Offset of field: ",
4071 stringify!(timer_hw_t),
4072 "::",
4073 stringify!(ints)
4074 )
4075 );
4076}
4077extern "C" {
4078 #[doc = " \\brief Return the current 64 bit timestamp value in microseconds"]
4079 #[doc = " \\ingroup hardware_timer"]
4080 #[doc = ""]
4081 #[doc = " Returns the full 64 bits of the hardware timer. The \\ref pico_time and other functions rely on the fact that this"]
4082 #[doc = " value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps"]
4083 #[doc = " (we apologize for introducing a potential year 5851444 bug)."]
4084 #[doc = ""]
4085 #[doc = " \\return the 64 bit timestamp"]
4086 pub fn time_us_64() -> u64;
4087}
4088extern "C" {
4089 #[doc = " \\brief Busy wait wasting cycles for the given (32 bit) number of microseconds"]
4090 #[doc = " \\ingroup hardware_timer"]
4091 #[doc = ""]
4092 #[doc = " \\param delay_us delay amount"]
4093 pub fn busy_wait_us_32(delay_us: u32);
4094}
4095extern "C" {
4096 #[doc = " \\brief Busy wait wasting cycles for the given (64 bit) number of microseconds"]
4097 #[doc = " \\ingroup hardware_timer"]
4098 #[doc = ""]
4099 #[doc = " \\param delay_us delay amount"]
4100 pub fn busy_wait_us(delay_us: u64);
4101}
4102extern "C" {
4103 #[doc = " \\brief Busy wait wasting cycles until after the specified timestamp"]
4104 #[doc = " \\ingroup hardware_timer"]
4105 #[doc = ""]
4106 #[doc = " \\param t Absolute time to wait until"]
4107 pub fn busy_wait_until(t: absolute_time_t);
4108}
4109#[doc = " Callback function type for hardware alarms"]
4110#[doc = " \\ingroup hardware_timer"]
4111#[doc = ""]
4112#[doc = " \\param alarm_num the hardware alarm number"]
4113#[doc = " \\sa hardware_alarm_set_callback"]
4114pub type hardware_alarm_callback_t = ::core::option::Option<unsafe extern "C" fn(alarm_num: uint)>;
4115extern "C" {
4116 #[doc = " \\brief cooperatively claim the use of this hardware alarm_num"]
4117 #[doc = " \\ingroup hardware_timer"]
4118 #[doc = ""]
4119 #[doc = " This method hard asserts if the hardware alarm is currently claimed."]
4120 #[doc = ""]
4121 #[doc = " \\param alarm_num the hardware alarm to claim"]
4122 #[doc = " \\sa hardware_claiming"]
4123 pub fn hardware_alarm_claim(alarm_num: uint);
4124}
4125extern "C" {
4126 #[doc = " \\brief cooperatively release the claim on use of this hardware alarm_num"]
4127 #[doc = " \\ingroup hardware_timer"]
4128 #[doc = ""]
4129 #[doc = " \\param alarm_num the hardware alarm to unclaim"]
4130 #[doc = " \\sa hardware_claiming"]
4131 pub fn hardware_alarm_unclaim(alarm_num: uint);
4132}
4133extern "C" {
4134 #[doc = " \\brief Enable/Disable a callback for a hardware timer on this core"]
4135 #[doc = " \\ingroup hardware_timer"]
4136 #[doc = ""]
4137 #[doc = " This method enables/disables the alarm IRQ for the specified hardware alarm on the"]
4138 #[doc = " calling core, and set the specified callback to be associated with that alarm."]
4139 #[doc = ""]
4140 #[doc = " This callback will be used for the timeout set via hardware_alarm_set_target"]
4141 #[doc = ""]
4142 #[doc = " \\note This will install the handler on the current core if the IRQ handler isn't already set."]
4143 #[doc = " Therefore the user has the opportunity to call this up from the core of their choice"]
4144 #[doc = ""]
4145 #[doc = " \\param alarm_num the hardware alarm number"]
4146 #[doc = " \\param callback the callback to install, or NULL to unset"]
4147 #[doc = ""]
4148 #[doc = " \\sa hardware_alarm_set_target"]
4149 pub fn hardware_alarm_set_callback(alarm_num: uint, callback: hardware_alarm_callback_t);
4150}
4151extern "C" {
4152 #[doc = " \\brief Set the current target for the specified hardware alarm"]
4153 #[doc = ""]
4154 #[doc = " This will replace any existing target"]
4155 #[doc = ""]
4156 #[doc = " @param alarm_num the hardware alarm number"]
4157 #[doc = " @param t the target timestamp"]
4158 #[doc = " @return true if the target was \"missed\"; i.e. it was in the past, or occurred before a future hardware timeout could be set"]
4159 pub fn hardware_alarm_set_target(alarm_num: uint, t: absolute_time_t) -> bool;
4160}
4161extern "C" {
4162 #[doc = " \\brief Cancel an existing target (if any) for a given hardware_alarm"]
4163 #[doc = ""]
4164 #[doc = " @param alarm_num"]
4165 pub fn hardware_alarm_cancel(alarm_num: uint);
4166}
4167extern "C" {
4168 pub static at_the_end_of_time: absolute_time_t;
4169}
4170extern "C" {
4171 pub static nil_time: absolute_time_t;
4172}
4173extern "C" {
4174 #[doc = " \\brief Wait until after the given timestamp to return"]
4175 #[doc = " \\ingroup sleep"]
4176 #[doc = ""]
4177 #[doc = " \\note This method attempts to perform a lower power (WFE) sleep"]
4178 #[doc = ""]
4179 #[doc = " \\param target the time after which to return"]
4180 #[doc = " \\sa sleep_us()"]
4181 #[doc = " \\sa busy_wait_until()"]
4182 pub fn sleep_until(target: absolute_time_t);
4183}
4184extern "C" {
4185 #[doc = " \\brief Wait for the given number of microseconds before returning"]
4186 #[doc = " \\ingroup sleep"]
4187 #[doc = ""]
4188 #[doc = " \\note This method attempts to perform a lower power (WFE) sleep"]
4189 #[doc = ""]
4190 #[doc = " \\param us the number of microseconds to sleep"]
4191 #[doc = " \\sa busy_wait_us()"]
4192 pub fn sleep_us(us: u64);
4193}
4194extern "C" {
4195 #[doc = " \\brief Wait for the given number of milliseconds before returning"]
4196 #[doc = " \\ingroup sleep"]
4197 #[doc = ""]
4198 #[doc = " \\note This method attempts to perform a lower power sleep (using WFE) as much as possible."]
4199 #[doc = ""]
4200 #[doc = " \\param ms the number of milliseconds to sleep"]
4201 pub fn sleep_ms(ms: u32);
4202}
4203extern "C" {
4204 #[doc = " \\brief Helper method for blocking on a timeout"]
4205 #[doc = " \\ingroup sleep"]
4206 #[doc = ""]
4207 #[doc = " This method will return in response to a an event (as per __wfe) or"]
4208 #[doc = " when the target time is reached, or at any point before."]
4209 #[doc = ""]
4210 #[doc = " This method can be used to implement a lower power polling loop waiting on"]
4211 #[doc = " some condition signalled by an event (__sev())."]
4212 #[doc = ""]
4213 #[doc = " This is called \\a best_effort because under certain circumstances (notably the default timer pool"]
4214 #[doc = " being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling"]
4215 #[doc = " code into a busy wait."]
4216 #[doc = ""]
4217 #[doc = " Example usage:"]
4218 #[doc = " ```c"]
4219 #[doc = " bool my_function_with_timeout_us(uint64_t timeout_us) {"]
4220 #[doc = " absolute_time_t timeout_time = make_timeout_time_us(timeout_us);"]
4221 #[doc = " do {"]
4222 #[doc = " // each time round the loop, we check to see if the condition"]
4223 #[doc = " // we are waiting on has happened"]
4224 #[doc = " if (my_check_done()) {"]
4225 #[doc = " // do something"]
4226 #[doc = " return true;"]
4227 #[doc = " }"]
4228 #[doc = " // will try to sleep until timeout or the next processor event"]
4229 #[doc = " } while (!best_effort_wfe_or_timeout(timeout_time));"]
4230 #[doc = " return false; // timed out"]
4231 #[doc = " }"]
4232 #[doc = " ```"]
4233 #[doc = ""]
4234 #[doc = " @param timeout_timestamp the timeout time"]
4235 #[doc = " @return true if the target time is reached, false otherwise"]
4236 pub fn best_effort_wfe_or_timeout(timeout_timestamp: absolute_time_t) -> bool;
4237}
4238#[doc = " \\brief The identifier for an alarm"]
4239#[doc = ""]
4240#[doc = " \\note this identifier is signed because -1 is used as an error condition when creating alarms"]
4241#[doc = ""]
4242#[doc = " \\note alarm ids may be reused, however for convenience the implementation makes an attempt to defer"]
4243#[doc = " reusing as long as possible. You should certainly expect it to be hundreds of ids before one is"]
4244#[doc = " reused, although in most cases it is more. Nonetheless care must still be taken when cancelling"]
4245#[doc = " alarms or other functionality based on alarms when the alarm may have expired, as eventually"]
4246#[doc = " the alarm id may be reused for another alarm."]
4247#[doc = ""]
4248#[doc = " \\ingroup alarm"]
4249pub type alarm_id_t = i32;
4250#[doc = " \\brief User alarm callback"]
4251#[doc = " \\ingroup alarm"]
4252#[doc = " \\param id the alarm_id as returned when the alarm was added"]
4253#[doc = " \\param user_data the user data passed when the alarm was added"]
4254#[doc = " \\return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire"]
4255#[doc = " \\return >0 to reschedule the same alarm this many us from the time this method returns"]
4256#[doc = " \\return 0 to not reschedule the alarm"]
4257pub type alarm_callback_t = ::core::option::Option<
4258 unsafe extern "C" fn(id: alarm_id_t, user_data: *mut crate::ctypes::c_void) -> i64,
4259>;
4260#[repr(C)]
4261#[derive(Debug, Copy, Clone)]
4262pub struct alarm_pool {
4263 _unused: [u8; 0],
4264}
4265pub type alarm_pool_t = alarm_pool;
4266extern "C" {
4267 #[doc = " \\brief Create the default alarm pool (if not already created or disabled)"]
4268 #[doc = " \\ingroup alarm"]
4269 pub fn alarm_pool_init_default();
4270}
4271extern "C" {
4272 #[doc = " \\brief The default alarm pool used when alarms are added without specifying an alarm pool,"]
4273 #[doc = " and also used by the Pico SDK to support lower power sleeps and timeouts."]
4274 #[doc = ""]
4275 #[doc = " \\ingroup alarm"]
4276 #[doc = " \\sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM"]
4277 pub fn alarm_pool_get_default() -> *mut alarm_pool_t;
4278}
4279extern "C" {
4280 #[doc = " \\brief Create an alarm pool"]
4281 #[doc = ""]
4282 #[doc = " The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from."]
4283 #[doc = ""]
4284 #[doc = " In many situations there is never any need for anything other than the default alarm pool, however you"]
4285 #[doc = " might want to create another if you want alarm callbacks on core 1 or require alarm pools of"]
4286 #[doc = " different priority (IRQ priority based preemption of callbacks)"]
4287 #[doc = ""]
4288 #[doc = " \\note This method will hard assert if the hardware alarm is already claimed."]
4289 #[doc = ""]
4290 #[doc = " \\ingroup alarm"]
4291 #[doc = " \\param hardware_alarm_num the hardware alarm to use to back this pool"]
4292 #[doc = " \\param max_timers the maximum number of timers"]
4293 #[doc = " \\note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255"]
4294 #[doc = " \\sa alarm_pool_get_default()"]
4295 #[doc = " \\sa hardware_claiming"]
4296 pub fn alarm_pool_create(hardware_alarm_num: uint, max_timers: uint) -> *mut alarm_pool_t;
4297}
4298extern "C" {
4299 #[doc = " \\brief Return the hardware alarm used by an alarm pool"]
4300 #[doc = " \\ingroup alarm"]
4301 #[doc = " \\param pool the pool"]
4302 #[doc = " \\return the hardware alarm used by the pool"]
4303 pub fn alarm_pool_hardware_alarm_num(pool: *mut alarm_pool_t) -> uint;
4304}
4305extern "C" {
4306 #[doc = " \\brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm"]
4307 #[doc = " \\ingroup alarm"]
4308 #[doc = " \\param pool the pool"]
4309 #[doc = " \\return the hardware alarm used by the pool"]
4310 pub fn alarm_pool_destroy(pool: *mut alarm_pool_t);
4311}
4312extern "C" {
4313 #[doc = " \\brief Add an alarm callback to be called at a specific time"]
4314 #[doc = " \\ingroup alarm"]
4315 #[doc = ""]
4316 #[doc = " Generally the callback is called as soon as possible after the time specified from an IRQ handler"]
4317 #[doc = " on the core the alarm pool was created on. If the callback is in the past or happens before"]
4318 #[doc = " the alarm setup could be completed, then this method will optionally call the callback itself"]
4319 #[doc = " and then return a return code to indicate that the target time has passed."]
4320 #[doc = ""]
4321 #[doc = " \\note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core."]
4322 #[doc = ""]
4323 #[doc = " @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)"]
4324 #[doc = " @param time the timestamp when (after which) the callback should fire"]
4325 #[doc = " @param callback the callback function"]
4326 #[doc = " @param user_data user data to pass to the callback function"]
4327 #[doc = " @param fire_if_past if true, this method will call the callback itself before returning 0 if the timestamp happens before or during this method call"]
4328 #[doc = " @return >0 the alarm id"]
4329 #[doc = " @return 0 the target timestamp was during or before this method call (whether the callback was called depends on fire_if_past)"]
4330 #[doc = " @return -1 if there were no alarm slots available"]
4331 pub fn alarm_pool_add_alarm_at(
4332 pool: *mut alarm_pool_t,
4333 time: absolute_time_t,
4334 callback: alarm_callback_t,
4335 user_data: *mut crate::ctypes::c_void,
4336 fire_if_past: bool,
4337 ) -> alarm_id_t;
4338}
4339extern "C" {
4340 #[doc = " \\brief Cancel an alarm"]
4341 #[doc = " \\ingroup alarm"]
4342 #[doc = " \\param pool the alarm_pool containing the alarm"]
4343 #[doc = " \\param alarm_id the alarm"]
4344 #[doc = " \\return true if the alarm was cancelled, false if it didn't exist"]
4345 #[doc = " \\sa alarm_id_t for a note on reuse of IDs"]
4346 pub fn alarm_pool_cancel_alarm(pool: *mut alarm_pool_t, alarm_id: alarm_id_t) -> bool;
4347}
4348#[doc = " \\defgroup repeating_timer repeating_timer"]
4349#[doc = " \\ingroup pico_time"]
4350#[doc = " \\brief Repeating Timer functions for simple scheduling of repeated execution"]
4351#[doc = ""]
4352#[doc = " \\note The regular \\a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback),"]
4353#[doc = " however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which"]
4354#[doc = " the alarm framework does not have space for)."]
4355pub type repeating_timer_t = repeating_timer;
4356#[doc = " \\brief Callback for a repeating timer"]
4357#[doc = " \\ingroup repeating_timer"]
4358#[doc = " \\param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user"]
4359#[doc = " \\return true to continue repeating, false to stop."]
4360pub type repeating_timer_callback_t =
4361 ::core::option::Option<unsafe extern "C" fn(rt: *mut repeating_timer_t) -> bool>;
4362#[doc = " \\brief Information about a repeating timer"]
4363#[doc = " \\ingroup repeating_timer"]
4364#[doc = " \\return"]
4365#[repr(C)]
4366#[derive(Debug, Copy, Clone)]
4367pub struct repeating_timer {
4368 pub delay_us: i64,
4369 pub pool: *mut alarm_pool_t,
4370 pub alarm_id: alarm_id_t,
4371 pub callback: repeating_timer_callback_t,
4372 pub user_data: *mut crate::ctypes::c_void,
4373}
4374#[test]
4375fn bindgen_test_layout_repeating_timer() {
4376 assert_eq!(
4377 ::core::mem::size_of::<repeating_timer>(),
4378 40usize,
4379 concat!("Size of: ", stringify!(repeating_timer))
4380 );
4381 assert_eq!(
4382 ::core::mem::align_of::<repeating_timer>(),
4383 8usize,
4384 concat!("Alignment of ", stringify!(repeating_timer))
4385 );
4386 assert_eq!(
4387 unsafe { &(*(::core::ptr::null::<repeating_timer>())).delay_us as *const _ as usize },
4388 0usize,
4389 concat!(
4390 "Offset of field: ",
4391 stringify!(repeating_timer),
4392 "::",
4393 stringify!(delay_us)
4394 )
4395 );
4396 assert_eq!(
4397 unsafe { &(*(::core::ptr::null::<repeating_timer>())).pool as *const _ as usize },
4398 8usize,
4399 concat!(
4400 "Offset of field: ",
4401 stringify!(repeating_timer),
4402 "::",
4403 stringify!(pool)
4404 )
4405 );
4406 assert_eq!(
4407 unsafe { &(*(::core::ptr::null::<repeating_timer>())).alarm_id as *const _ as usize },
4408 16usize,
4409 concat!(
4410 "Offset of field: ",
4411 stringify!(repeating_timer),
4412 "::",
4413 stringify!(alarm_id)
4414 )
4415 );
4416 assert_eq!(
4417 unsafe { &(*(::core::ptr::null::<repeating_timer>())).callback as *const _ as usize },
4418 24usize,
4419 concat!(
4420 "Offset of field: ",
4421 stringify!(repeating_timer),
4422 "::",
4423 stringify!(callback)
4424 )
4425 );
4426 assert_eq!(
4427 unsafe { &(*(::core::ptr::null::<repeating_timer>())).user_data as *const _ as usize },
4428 32usize,
4429 concat!(
4430 "Offset of field: ",
4431 stringify!(repeating_timer),
4432 "::",
4433 stringify!(user_data)
4434 )
4435 );
4436}
4437extern "C" {
4438 #[doc = " \\brief Add a repeating timer that is called repeatedly at the specified interval in microseconds"]
4439 #[doc = " \\ingroup repeating_timer"]
4440 #[doc = ""]
4441 #[doc = " Generally the callback is called as soon as possible after the time specified from an IRQ handler"]
4442 #[doc = " on the core the alarm pool was created on. If the callback is in the past or happens before"]
4443 #[doc = " the alarm setup could be completed, then this method will optionally call the callback itself"]
4444 #[doc = " and then return a return code to indicate that the target time has passed."]
4445 #[doc = ""]
4446 #[doc = " \\note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core."]
4447 #[doc = ""]
4448 #[doc = " @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)"]
4449 #[doc = " @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1"]
4450 #[doc = " @param callback the repeating timer callback function"]
4451 #[doc = " @param user_data user data to pass to store in the repeating_timer structure for use by the callback."]
4452 #[doc = " @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space"]
4453 #[doc = " @return false if there were no alarm slots available to create the timer, true otherwise."]
4454 pub fn alarm_pool_add_repeating_timer_us(
4455 pool: *mut alarm_pool_t,
4456 delay_us: i64,
4457 callback: repeating_timer_callback_t,
4458 user_data: *mut crate::ctypes::c_void,
4459 out: *mut repeating_timer_t,
4460 ) -> bool;
4461}
4462extern "C" {
4463 #[doc = " \\brief Cancel a repeating timer"]
4464 #[doc = " \\ingroup repeating_timer"]
4465 #[doc = " \\param timer the repeating timer to cancel"]
4466 #[doc = " \\return true if the repeating timer was cancelled, false if it didn't exist"]
4467 #[doc = " \\sa alarm_id_t for a note on reuse of IDs"]
4468 pub fn cancel_repeating_timer(timer: *mut repeating_timer_t) -> bool;
4469}
4470#[repr(C)]
4471#[derive(Debug, Copy, Clone)]
4472pub struct interp_hw_t {
4473 pub accum: [io_rw_32; 2usize],
4474 pub base: [io_rw_32; 3usize],
4475 pub pop: [io_ro_32; 3usize],
4476 pub peek: [io_ro_32; 3usize],
4477 pub ctrl: [io_rw_32; 2usize],
4478 pub add_raw: [io_rw_32; 2usize],
4479 pub base01: io_wo_32,
4480}
4481#[test]
4482fn bindgen_test_layout_interp_hw_t() {
4483 assert_eq!(
4484 ::core::mem::size_of::<interp_hw_t>(),
4485 64usize,
4486 concat!("Size of: ", stringify!(interp_hw_t))
4487 );
4488 assert_eq!(
4489 ::core::mem::align_of::<interp_hw_t>(),
4490 4usize,
4491 concat!("Alignment of ", stringify!(interp_hw_t))
4492 );
4493 assert_eq!(
4494 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).accum as *const _ as usize },
4495 0usize,
4496 concat!(
4497 "Offset of field: ",
4498 stringify!(interp_hw_t),
4499 "::",
4500 stringify!(accum)
4501 )
4502 );
4503 assert_eq!(
4504 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).base as *const _ as usize },
4505 8usize,
4506 concat!(
4507 "Offset of field: ",
4508 stringify!(interp_hw_t),
4509 "::",
4510 stringify!(base)
4511 )
4512 );
4513 assert_eq!(
4514 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).pop as *const _ as usize },
4515 20usize,
4516 concat!(
4517 "Offset of field: ",
4518 stringify!(interp_hw_t),
4519 "::",
4520 stringify!(pop)
4521 )
4522 );
4523 assert_eq!(
4524 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).peek as *const _ as usize },
4525 32usize,
4526 concat!(
4527 "Offset of field: ",
4528 stringify!(interp_hw_t),
4529 "::",
4530 stringify!(peek)
4531 )
4532 );
4533 assert_eq!(
4534 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).ctrl as *const _ as usize },
4535 44usize,
4536 concat!(
4537 "Offset of field: ",
4538 stringify!(interp_hw_t),
4539 "::",
4540 stringify!(ctrl)
4541 )
4542 );
4543 assert_eq!(
4544 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).add_raw as *const _ as usize },
4545 52usize,
4546 concat!(
4547 "Offset of field: ",
4548 stringify!(interp_hw_t),
4549 "::",
4550 stringify!(add_raw)
4551 )
4552 );
4553 assert_eq!(
4554 unsafe { &(*(::core::ptr::null::<interp_hw_t>())).base01 as *const _ as usize },
4555 60usize,
4556 concat!(
4557 "Offset of field: ",
4558 stringify!(interp_hw_t),
4559 "::",
4560 stringify!(base01)
4561 )
4562 );
4563}
4564#[repr(C)]
4565#[derive(Debug, Copy, Clone)]
4566pub struct sio_hw_t {
4567 pub cpuid: io_ro_32,
4568 pub gpio_in: io_ro_32,
4569 pub gpio_hi_in: io_ro_32,
4570 pub _pad: u32,
4571 pub gpio_out: io_wo_32,
4572 pub gpio_set: io_wo_32,
4573 pub gpio_clr: io_wo_32,
4574 pub gpio_togl: io_wo_32,
4575 pub gpio_oe: io_wo_32,
4576 pub gpio_oe_set: io_wo_32,
4577 pub gpio_oe_clr: io_wo_32,
4578 pub gpio_oe_togl: io_wo_32,
4579 pub gpio_hi_out: io_wo_32,
4580 pub gpio_hi_set: io_wo_32,
4581 pub gpio_hi_clr: io_wo_32,
4582 pub gpio_hi_togl: io_wo_32,
4583 pub gpio_hi_oe: io_wo_32,
4584 pub gpio_hi_oe_set: io_wo_32,
4585 pub gpio_hi_oe_clr: io_wo_32,
4586 pub gpio_hi_oe_togl: io_wo_32,
4587 pub fifo_st: io_rw_32,
4588 pub fifo_wr: io_wo_32,
4589 pub fifo_rd: io_ro_32,
4590 pub spinlock_st: io_ro_32,
4591 pub div_udividend: io_rw_32,
4592 pub div_udivisor: io_rw_32,
4593 pub div_sdividend: io_rw_32,
4594 pub div_sdivisor: io_rw_32,
4595 pub div_quotient: io_rw_32,
4596 pub div_remainder: io_rw_32,
4597 pub div_csr: io_rw_32,
4598 pub _pad2: u32,
4599 pub interp: [interp_hw_t; 2usize],
4600}
4601#[test]
4602fn bindgen_test_layout_sio_hw_t() {
4603 assert_eq!(
4604 ::core::mem::size_of::<sio_hw_t>(),
4605 256usize,
4606 concat!("Size of: ", stringify!(sio_hw_t))
4607 );
4608 assert_eq!(
4609 ::core::mem::align_of::<sio_hw_t>(),
4610 4usize,
4611 concat!("Alignment of ", stringify!(sio_hw_t))
4612 );
4613 assert_eq!(
4614 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).cpuid as *const _ as usize },
4615 0usize,
4616 concat!(
4617 "Offset of field: ",
4618 stringify!(sio_hw_t),
4619 "::",
4620 stringify!(cpuid)
4621 )
4622 );
4623 assert_eq!(
4624 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_in as *const _ as usize },
4625 4usize,
4626 concat!(
4627 "Offset of field: ",
4628 stringify!(sio_hw_t),
4629 "::",
4630 stringify!(gpio_in)
4631 )
4632 );
4633 assert_eq!(
4634 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_in as *const _ as usize },
4635 8usize,
4636 concat!(
4637 "Offset of field: ",
4638 stringify!(sio_hw_t),
4639 "::",
4640 stringify!(gpio_hi_in)
4641 )
4642 );
4643 assert_eq!(
4644 unsafe { &(*(::core::ptr::null::<sio_hw_t>()))._pad as *const _ as usize },
4645 12usize,
4646 concat!(
4647 "Offset of field: ",
4648 stringify!(sio_hw_t),
4649 "::",
4650 stringify!(_pad)
4651 )
4652 );
4653 assert_eq!(
4654 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_out as *const _ as usize },
4655 16usize,
4656 concat!(
4657 "Offset of field: ",
4658 stringify!(sio_hw_t),
4659 "::",
4660 stringify!(gpio_out)
4661 )
4662 );
4663 assert_eq!(
4664 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_set as *const _ as usize },
4665 20usize,
4666 concat!(
4667 "Offset of field: ",
4668 stringify!(sio_hw_t),
4669 "::",
4670 stringify!(gpio_set)
4671 )
4672 );
4673 assert_eq!(
4674 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_clr as *const _ as usize },
4675 24usize,
4676 concat!(
4677 "Offset of field: ",
4678 stringify!(sio_hw_t),
4679 "::",
4680 stringify!(gpio_clr)
4681 )
4682 );
4683 assert_eq!(
4684 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_togl as *const _ as usize },
4685 28usize,
4686 concat!(
4687 "Offset of field: ",
4688 stringify!(sio_hw_t),
4689 "::",
4690 stringify!(gpio_togl)
4691 )
4692 );
4693 assert_eq!(
4694 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe as *const _ as usize },
4695 32usize,
4696 concat!(
4697 "Offset of field: ",
4698 stringify!(sio_hw_t),
4699 "::",
4700 stringify!(gpio_oe)
4701 )
4702 );
4703 assert_eq!(
4704 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_set as *const _ as usize },
4705 36usize,
4706 concat!(
4707 "Offset of field: ",
4708 stringify!(sio_hw_t),
4709 "::",
4710 stringify!(gpio_oe_set)
4711 )
4712 );
4713 assert_eq!(
4714 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_clr as *const _ as usize },
4715 40usize,
4716 concat!(
4717 "Offset of field: ",
4718 stringify!(sio_hw_t),
4719 "::",
4720 stringify!(gpio_oe_clr)
4721 )
4722 );
4723 assert_eq!(
4724 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_oe_togl as *const _ as usize },
4725 44usize,
4726 concat!(
4727 "Offset of field: ",
4728 stringify!(sio_hw_t),
4729 "::",
4730 stringify!(gpio_oe_togl)
4731 )
4732 );
4733 assert_eq!(
4734 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_out as *const _ as usize },
4735 48usize,
4736 concat!(
4737 "Offset of field: ",
4738 stringify!(sio_hw_t),
4739 "::",
4740 stringify!(gpio_hi_out)
4741 )
4742 );
4743 assert_eq!(
4744 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_set as *const _ as usize },
4745 52usize,
4746 concat!(
4747 "Offset of field: ",
4748 stringify!(sio_hw_t),
4749 "::",
4750 stringify!(gpio_hi_set)
4751 )
4752 );
4753 assert_eq!(
4754 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_clr as *const _ as usize },
4755 56usize,
4756 concat!(
4757 "Offset of field: ",
4758 stringify!(sio_hw_t),
4759 "::",
4760 stringify!(gpio_hi_clr)
4761 )
4762 );
4763 assert_eq!(
4764 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_togl as *const _ as usize },
4765 60usize,
4766 concat!(
4767 "Offset of field: ",
4768 stringify!(sio_hw_t),
4769 "::",
4770 stringify!(gpio_hi_togl)
4771 )
4772 );
4773 assert_eq!(
4774 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe as *const _ as usize },
4775 64usize,
4776 concat!(
4777 "Offset of field: ",
4778 stringify!(sio_hw_t),
4779 "::",
4780 stringify!(gpio_hi_oe)
4781 )
4782 );
4783 assert_eq!(
4784 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_set as *const _ as usize },
4785 68usize,
4786 concat!(
4787 "Offset of field: ",
4788 stringify!(sio_hw_t),
4789 "::",
4790 stringify!(gpio_hi_oe_set)
4791 )
4792 );
4793 assert_eq!(
4794 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_clr as *const _ as usize },
4795 72usize,
4796 concat!(
4797 "Offset of field: ",
4798 stringify!(sio_hw_t),
4799 "::",
4800 stringify!(gpio_hi_oe_clr)
4801 )
4802 );
4803 assert_eq!(
4804 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).gpio_hi_oe_togl as *const _ as usize },
4805 76usize,
4806 concat!(
4807 "Offset of field: ",
4808 stringify!(sio_hw_t),
4809 "::",
4810 stringify!(gpio_hi_oe_togl)
4811 )
4812 );
4813 assert_eq!(
4814 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_st as *const _ as usize },
4815 80usize,
4816 concat!(
4817 "Offset of field: ",
4818 stringify!(sio_hw_t),
4819 "::",
4820 stringify!(fifo_st)
4821 )
4822 );
4823 assert_eq!(
4824 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_wr as *const _ as usize },
4825 84usize,
4826 concat!(
4827 "Offset of field: ",
4828 stringify!(sio_hw_t),
4829 "::",
4830 stringify!(fifo_wr)
4831 )
4832 );
4833 assert_eq!(
4834 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).fifo_rd as *const _ as usize },
4835 88usize,
4836 concat!(
4837 "Offset of field: ",
4838 stringify!(sio_hw_t),
4839 "::",
4840 stringify!(fifo_rd)
4841 )
4842 );
4843 assert_eq!(
4844 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).spinlock_st as *const _ as usize },
4845 92usize,
4846 concat!(
4847 "Offset of field: ",
4848 stringify!(sio_hw_t),
4849 "::",
4850 stringify!(spinlock_st)
4851 )
4852 );
4853 assert_eq!(
4854 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_udividend as *const _ as usize },
4855 96usize,
4856 concat!(
4857 "Offset of field: ",
4858 stringify!(sio_hw_t),
4859 "::",
4860 stringify!(div_udividend)
4861 )
4862 );
4863 assert_eq!(
4864 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_udivisor as *const _ as usize },
4865 100usize,
4866 concat!(
4867 "Offset of field: ",
4868 stringify!(sio_hw_t),
4869 "::",
4870 stringify!(div_udivisor)
4871 )
4872 );
4873 assert_eq!(
4874 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_sdividend as *const _ as usize },
4875 104usize,
4876 concat!(
4877 "Offset of field: ",
4878 stringify!(sio_hw_t),
4879 "::",
4880 stringify!(div_sdividend)
4881 )
4882 );
4883 assert_eq!(
4884 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_sdivisor as *const _ as usize },
4885 108usize,
4886 concat!(
4887 "Offset of field: ",
4888 stringify!(sio_hw_t),
4889 "::",
4890 stringify!(div_sdivisor)
4891 )
4892 );
4893 assert_eq!(
4894 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_quotient as *const _ as usize },
4895 112usize,
4896 concat!(
4897 "Offset of field: ",
4898 stringify!(sio_hw_t),
4899 "::",
4900 stringify!(div_quotient)
4901 )
4902 );
4903 assert_eq!(
4904 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_remainder as *const _ as usize },
4905 116usize,
4906 concat!(
4907 "Offset of field: ",
4908 stringify!(sio_hw_t),
4909 "::",
4910 stringify!(div_remainder)
4911 )
4912 );
4913 assert_eq!(
4914 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).div_csr as *const _ as usize },
4915 120usize,
4916 concat!(
4917 "Offset of field: ",
4918 stringify!(sio_hw_t),
4919 "::",
4920 stringify!(div_csr)
4921 )
4922 );
4923 assert_eq!(
4924 unsafe { &(*(::core::ptr::null::<sio_hw_t>()))._pad2 as *const _ as usize },
4925 124usize,
4926 concat!(
4927 "Offset of field: ",
4928 stringify!(sio_hw_t),
4929 "::",
4930 stringify!(_pad2)
4931 )
4932 );
4933 assert_eq!(
4934 unsafe { &(*(::core::ptr::null::<sio_hw_t>())).interp as *const _ as usize },
4935 128usize,
4936 concat!(
4937 "Offset of field: ",
4938 stringify!(sio_hw_t),
4939 "::",
4940 stringify!(interp)
4941 )
4942 );
4943}
4944#[repr(C)]
4945#[derive(Debug, Copy, Clone)]
4946pub struct padsbank0_hw_t {
4947 pub voltage_select: io_rw_32,
4948 pub io: [io_rw_32; 30usize],
4949}
4950#[test]
4951fn bindgen_test_layout_padsbank0_hw_t() {
4952 assert_eq!(
4953 ::core::mem::size_of::<padsbank0_hw_t>(),
4954 124usize,
4955 concat!("Size of: ", stringify!(padsbank0_hw_t))
4956 );
4957 assert_eq!(
4958 ::core::mem::align_of::<padsbank0_hw_t>(),
4959 4usize,
4960 concat!("Alignment of ", stringify!(padsbank0_hw_t))
4961 );
4962 assert_eq!(
4963 unsafe { &(*(::core::ptr::null::<padsbank0_hw_t>())).voltage_select as *const _ as usize },
4964 0usize,
4965 concat!(
4966 "Offset of field: ",
4967 stringify!(padsbank0_hw_t),
4968 "::",
4969 stringify!(voltage_select)
4970 )
4971 );
4972 assert_eq!(
4973 unsafe { &(*(::core::ptr::null::<padsbank0_hw_t>())).io as *const _ as usize },
4974 4usize,
4975 concat!(
4976 "Offset of field: ",
4977 stringify!(padsbank0_hw_t),
4978 "::",
4979 stringify!(io)
4980 )
4981 );
4982}
4983pub const gpio_function_GPIO_FUNC_XIP: gpio_function = 0;
4984pub const gpio_function_GPIO_FUNC_SPI: gpio_function = 1;
4985pub const gpio_function_GPIO_FUNC_UART: gpio_function = 2;
4986pub const gpio_function_GPIO_FUNC_I2C: gpio_function = 3;
4987pub const gpio_function_GPIO_FUNC_PWM: gpio_function = 4;
4988pub const gpio_function_GPIO_FUNC_SIO: gpio_function = 5;
4989pub const gpio_function_GPIO_FUNC_PIO0: gpio_function = 6;
4990pub const gpio_function_GPIO_FUNC_PIO1: gpio_function = 7;
4991pub const gpio_function_GPIO_FUNC_GPCK: gpio_function = 8;
4992pub const gpio_function_GPIO_FUNC_USB: gpio_function = 9;
4993pub const gpio_function_GPIO_FUNC_NULL: gpio_function = 15;
4994#[doc = " \\brief GPIO function definitions for use with function select"]
4995#[doc = " \\ingroup hardware_gpio"]
4996#[doc = " \\brief GPIO function selectors"]
4997#[doc = ""]
4998#[doc = " Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be"]
4999#[doc = " selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical"]
5000#[doc = " OR of these GPIO inputs."]
5001#[doc = ""]
5002#[doc = " Please refer to the datsheet for more information on GPIO function selection."]
5003pub type gpio_function = crate::ctypes::c_uint;
5004pub const gpio_irq_level_GPIO_IRQ_LEVEL_LOW: gpio_irq_level = 1;
5005pub const gpio_irq_level_GPIO_IRQ_LEVEL_HIGH: gpio_irq_level = 2;
5006pub const gpio_irq_level_GPIO_IRQ_EDGE_FALL: gpio_irq_level = 4;
5007pub const gpio_irq_level_GPIO_IRQ_EDGE_RISE: gpio_irq_level = 8;
5008#[doc = " \\brief GPIO Interrupt level definitions"]
5009#[doc = " \\ingroup hardware_gpio"]
5010#[doc = " \\brief GPIO Interrupt levels"]
5011#[doc = ""]
5012#[doc = " An interrupt can be generated for every GPIO pin in 4 scenarios:"]
5013#[doc = ""]
5014#[doc = " * Level High: the GPIO pin is a logical 1"]
5015#[doc = " * Level Low: the GPIO pin is a logical 0"]
5016#[doc = " * Edge High: the GPIO has transitioned from a logical 0 to a logical 1"]
5017#[doc = " * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0"]
5018#[doc = ""]
5019#[doc = " The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will"]
5020#[doc = " become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be"]
5021#[doc = " cleared by writing to the INTR register."]
5022pub type gpio_irq_level = crate::ctypes::c_uint;
5023pub type gpio_irq_callback_t =
5024 ::core::option::Option<unsafe extern "C" fn(gpio: uint, events: u32)>;
5025#[doc = "< peripheral signal selected via \\ref gpio_set_function"]
5026pub const gpio_override_GPIO_OVERRIDE_NORMAL: gpio_override = 0;
5027#[doc = "< invert peripheral signal selected via \\ref gpio_set_function"]
5028pub const gpio_override_GPIO_OVERRIDE_INVERT: gpio_override = 1;
5029#[doc = "< drive low/disable output"]
5030pub const gpio_override_GPIO_OVERRIDE_LOW: gpio_override = 2;
5031#[doc = "< drive high/enable output"]
5032pub const gpio_override_GPIO_OVERRIDE_HIGH: gpio_override = 3;
5033pub type gpio_override = crate::ctypes::c_uint;
5034extern "C" {
5035 #[doc = " \\brief Select GPIO function"]
5036 #[doc = " \\ingroup hardware_gpio"]
5037 #[doc = ""]
5038 #[doc = " \\param gpio GPIO number"]
5039 #[doc = " \\param fn Which GPIO function select to use from list \\ref gpio_function"]
5040 pub fn gpio_set_function(gpio: uint, fn_: gpio_function);
5041}
5042extern "C" {
5043 pub fn gpio_get_function(gpio: uint) -> gpio_function;
5044}
5045extern "C" {
5046 #[doc = " \\brief Select up and down pulls on specific GPIO"]
5047 #[doc = " \\ingroup hardware_gpio"]
5048 #[doc = ""]
5049 #[doc = " \\param gpio GPIO number"]
5050 #[doc = " \\param up If true set a pull up on the GPIO"]
5051 #[doc = " \\param down If true set a pull down on the GPIO"]
5052 #[doc = ""]
5053 #[doc = " \\note On the RP2040, setting both pulls enables a \"bus keep\" function,"]
5054 #[doc = " i.e. a weak pull to whatever is current high/low state of GPIO."]
5055 pub fn gpio_set_pulls(gpio: uint, up: bool, down: bool);
5056}
5057extern "C" {
5058 #[doc = " \\brief Set GPIO output override"]
5059 #[doc = " \\ingroup hardware_gpio"]
5060 #[doc = ""]
5061 #[doc = " \\param gpio GPIO number"]
5062 #[doc = " \\param value See \\ref gpio_override"]
5063 pub fn gpio_set_outover(gpio: uint, value: uint);
5064}
5065extern "C" {
5066 #[doc = " \\brief Select GPIO input override"]
5067 #[doc = " \\ingroup hardware_gpio"]
5068 #[doc = ""]
5069 #[doc = " \\param gpio GPIO number"]
5070 #[doc = " \\param value See \\ref gpio_override"]
5071 pub fn gpio_set_inover(gpio: uint, value: uint);
5072}
5073extern "C" {
5074 #[doc = " \\brief Select GPIO output enable override"]
5075 #[doc = " \\ingroup hardware_gpio"]
5076 #[doc = ""]
5077 #[doc = " \\param gpio GPIO number"]
5078 #[doc = " \\param value See \\ref gpio_override"]
5079 pub fn gpio_set_oeover(gpio: uint, value: uint);
5080}
5081extern "C" {
5082 #[doc = " \\brief Enable GPIO input"]
5083 #[doc = " \\ingroup hardware_gpio"]
5084 #[doc = ""]
5085 #[doc = " \\param gpio GPIO number"]
5086 #[doc = " \\param enabled true to enable input on specified GPIO"]
5087 pub fn gpio_set_input_enabled(gpio: uint, enabled: bool);
5088}
5089extern "C" {
5090 #[doc = " \\brief Enable or disable interrupts for specified GPIO"]
5091 #[doc = " \\ingroup hardware_gpio"]
5092 #[doc = ""]
5093 #[doc = " \\note The IO IRQs are independent per-processor. This configures IRQs for"]
5094 #[doc = " the processor that calls the function."]
5095 #[doc = ""]
5096 #[doc = " \\param gpio GPIO number"]
5097 #[doc = " \\param events Which events will cause an interrupt"]
5098 #[doc = " \\param enabled Enable or disable flag"]
5099 #[doc = ""]
5100 #[doc = " Events is a bitmask of the following:"]
5101 #[doc = ""]
5102 #[doc = " bit | interrupt"]
5103 #[doc = " ----|----------"]
5104 #[doc = " 0 | Low level"]
5105 #[doc = " 1 | High level"]
5106 #[doc = " 2 | Edge low"]
5107 #[doc = " 3 | Edge high"]
5108 pub fn gpio_set_irq_enabled(gpio: uint, events: u32, enabled: bool);
5109}
5110extern "C" {
5111 #[doc = " \\brief Enable interrupts for specified GPIO"]
5112 #[doc = " \\ingroup hardware_gpio"]
5113 #[doc = ""]
5114 #[doc = " \\note The IO IRQs are independent per-processor. This configures IRQs for"]
5115 #[doc = " the processor that calls the function."]
5116 #[doc = ""]
5117 #[doc = " \\param gpio GPIO number"]
5118 #[doc = " \\param events Which events will cause an interrupt See \\ref gpio_set_irq_enabled for details."]
5119 #[doc = " \\param enabled Enable or disable flag"]
5120 #[doc = " \\param callback user function to call on GPIO irq. Note only one of these can be set per processor."]
5121 #[doc = ""]
5122 #[doc = " \\note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin."]
5123 #[doc = ""]
5124 pub fn gpio_set_irq_enabled_with_callback(
5125 gpio: uint,
5126 events: u32,
5127 enabled: bool,
5128 callback: gpio_irq_callback_t,
5129 );
5130}
5131extern "C" {
5132 #[doc = " \\brief Enable dormant wake up interrupt for specified GPIO"]
5133 #[doc = " \\ingroup hardware_gpio"]
5134 #[doc = ""]
5135 #[doc = " This configures IRQs to restart the XOSC or ROSC when they are"]
5136 #[doc = " disabled in dormant mode"]
5137 #[doc = ""]
5138 #[doc = " \\param gpio GPIO number"]
5139 #[doc = " \\param events Which events will cause an interrupt. See \\ref gpio_set_irq_enabled for details."]
5140 #[doc = " \\param enabled Enable/disable flag"]
5141 pub fn gpio_set_dormant_irq_enabled(gpio: uint, events: u32, enabled: bool);
5142}
5143extern "C" {
5144 #[doc = " \\brief Acknowledge a GPIO interrupt"]
5145 #[doc = " \\ingroup hardware_gpio"]
5146 #[doc = ""]
5147 #[doc = " \\param gpio GPIO number"]
5148 #[doc = " \\param events Bitmask of events to clear. See \\ref gpio_set_irq_enabled for details."]
5149 #[doc = ""]
5150 pub fn gpio_acknowledge_irq(gpio: uint, events: u32);
5151}
5152extern "C" {
5153 #[doc = " \\brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)"]
5154 #[doc = " \\ingroup hardware_gpio"]
5155 #[doc = ""]
5156 #[doc = " Clear the output enable (i.e. set to input)"]
5157 #[doc = " Clear any output value."]
5158 #[doc = ""]
5159 #[doc = " \\param gpio GPIO number"]
5160 pub fn gpio_init(gpio: uint);
5161}
5162extern "C" {
5163 #[doc = " \\brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)"]
5164 #[doc = " \\ingroup hardware_gpio"]
5165 #[doc = ""]
5166 #[doc = " Clear the output enable (i.e. set to input)"]
5167 #[doc = " Clear any output value."]
5168 #[doc = ""]
5169 #[doc = " \\param gpio_mask Mask with 1 bit per GPIO number to initialize"]
5170 pub fn gpio_init_mask(gpio_mask: uint);
5171}
5172extern "C" {
5173 pub fn gpio_debug_pins_init();
5174}
5175#[repr(C)]
5176#[derive(Debug, Copy, Clone)]
5177pub struct uart_hw_t {
5178 pub dr: io_rw_32,
5179 pub rsr: io_rw_32,
5180 pub _pad0: [u32; 4usize],
5181 pub fr: io_rw_32,
5182 pub _pad1: u32,
5183 pub ilpr: io_rw_32,
5184 pub ibrd: io_rw_32,
5185 pub fbrd: io_rw_32,
5186 pub lcr_h: io_rw_32,
5187 pub cr: io_rw_32,
5188 pub ifls: io_rw_32,
5189 pub imsc: io_rw_32,
5190 pub ris: io_rw_32,
5191 pub mis: io_rw_32,
5192 pub icr: io_rw_32,
5193 pub dmacr: io_rw_32,
5194}
5195#[test]
5196fn bindgen_test_layout_uart_hw_t() {
5197 assert_eq!(
5198 ::core::mem::size_of::<uart_hw_t>(),
5199 76usize,
5200 concat!("Size of: ", stringify!(uart_hw_t))
5201 );
5202 assert_eq!(
5203 ::core::mem::align_of::<uart_hw_t>(),
5204 4usize,
5205 concat!("Alignment of ", stringify!(uart_hw_t))
5206 );
5207 assert_eq!(
5208 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).dr as *const _ as usize },
5209 0usize,
5210 concat!(
5211 "Offset of field: ",
5212 stringify!(uart_hw_t),
5213 "::",
5214 stringify!(dr)
5215 )
5216 );
5217 assert_eq!(
5218 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).rsr as *const _ as usize },
5219 4usize,
5220 concat!(
5221 "Offset of field: ",
5222 stringify!(uart_hw_t),
5223 "::",
5224 stringify!(rsr)
5225 )
5226 );
5227 assert_eq!(
5228 unsafe { &(*(::core::ptr::null::<uart_hw_t>()))._pad0 as *const _ as usize },
5229 8usize,
5230 concat!(
5231 "Offset of field: ",
5232 stringify!(uart_hw_t),
5233 "::",
5234 stringify!(_pad0)
5235 )
5236 );
5237 assert_eq!(
5238 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).fr as *const _ as usize },
5239 24usize,
5240 concat!(
5241 "Offset of field: ",
5242 stringify!(uart_hw_t),
5243 "::",
5244 stringify!(fr)
5245 )
5246 );
5247 assert_eq!(
5248 unsafe { &(*(::core::ptr::null::<uart_hw_t>()))._pad1 as *const _ as usize },
5249 28usize,
5250 concat!(
5251 "Offset of field: ",
5252 stringify!(uart_hw_t),
5253 "::",
5254 stringify!(_pad1)
5255 )
5256 );
5257 assert_eq!(
5258 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ilpr as *const _ as usize },
5259 32usize,
5260 concat!(
5261 "Offset of field: ",
5262 stringify!(uart_hw_t),
5263 "::",
5264 stringify!(ilpr)
5265 )
5266 );
5267 assert_eq!(
5268 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ibrd as *const _ as usize },
5269 36usize,
5270 concat!(
5271 "Offset of field: ",
5272 stringify!(uart_hw_t),
5273 "::",
5274 stringify!(ibrd)
5275 )
5276 );
5277 assert_eq!(
5278 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).fbrd as *const _ as usize },
5279 40usize,
5280 concat!(
5281 "Offset of field: ",
5282 stringify!(uart_hw_t),
5283 "::",
5284 stringify!(fbrd)
5285 )
5286 );
5287 assert_eq!(
5288 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).lcr_h as *const _ as usize },
5289 44usize,
5290 concat!(
5291 "Offset of field: ",
5292 stringify!(uart_hw_t),
5293 "::",
5294 stringify!(lcr_h)
5295 )
5296 );
5297 assert_eq!(
5298 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).cr as *const _ as usize },
5299 48usize,
5300 concat!(
5301 "Offset of field: ",
5302 stringify!(uart_hw_t),
5303 "::",
5304 stringify!(cr)
5305 )
5306 );
5307 assert_eq!(
5308 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ifls as *const _ as usize },
5309 52usize,
5310 concat!(
5311 "Offset of field: ",
5312 stringify!(uart_hw_t),
5313 "::",
5314 stringify!(ifls)
5315 )
5316 );
5317 assert_eq!(
5318 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).imsc as *const _ as usize },
5319 56usize,
5320 concat!(
5321 "Offset of field: ",
5322 stringify!(uart_hw_t),
5323 "::",
5324 stringify!(imsc)
5325 )
5326 );
5327 assert_eq!(
5328 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).ris as *const _ as usize },
5329 60usize,
5330 concat!(
5331 "Offset of field: ",
5332 stringify!(uart_hw_t),
5333 "::",
5334 stringify!(ris)
5335 )
5336 );
5337 assert_eq!(
5338 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).mis as *const _ as usize },
5339 64usize,
5340 concat!(
5341 "Offset of field: ",
5342 stringify!(uart_hw_t),
5343 "::",
5344 stringify!(mis)
5345 )
5346 );
5347 assert_eq!(
5348 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).icr as *const _ as usize },
5349 68usize,
5350 concat!(
5351 "Offset of field: ",
5352 stringify!(uart_hw_t),
5353 "::",
5354 stringify!(icr)
5355 )
5356 );
5357 assert_eq!(
5358 unsafe { &(*(::core::ptr::null::<uart_hw_t>())).dmacr as *const _ as usize },
5359 72usize,
5360 concat!(
5361 "Offset of field: ",
5362 stringify!(uart_hw_t),
5363 "::",
5364 stringify!(dmacr)
5365 )
5366 );
5367}
5368#[repr(C)]
5369#[derive(Debug, Copy, Clone)]
5370pub struct uart_inst {
5371 _unused: [u8; 0],
5372}
5373#[doc = " \\file hardware/uart.h"]
5374#[doc = " \\defgroup hardware_uart hardware_uart"]
5375#[doc = ""]
5376#[doc = " Hardware UART API"]
5377#[doc = ""]
5378#[doc = " RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number"]
5379#[doc = " of GPIO pins as defined in the GPIO muxing."]
5380#[doc = ""]
5381#[doc = " Only the TX, RX, RTS, and CTS signals are"]
5382#[doc = " connected, meaning that the modem mode and IrDA mode of the PL011 are not supported."]
5383#[doc = ""]
5384#[doc = " \\subsection uart_example Example"]
5385#[doc = " \\addtogroup hardware_uart"]
5386#[doc = ""]
5387#[doc = " \\code"]
5388#[doc = " int main() {"]
5389#[doc = ""]
5390#[doc = " // Initialise UART 0"]
5391#[doc = " uart_init(uart0, 115200);"]
5392#[doc = ""]
5393#[doc = " // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX"]
5394#[doc = " gpio_set_function(0, GPIO_FUNC_UART);"]
5395#[doc = " gpio_set_function(1, GPIO_FUNC_UART);"]
5396#[doc = ""]
5397#[doc = " uart_puts(uart0, \"Hello world!\");"]
5398#[doc = " }"]
5399#[doc = " \\endcode"]
5400pub type uart_inst_t = uart_inst;
5401pub const uart_parity_t_UART_PARITY_NONE: uart_parity_t = 0;
5402pub const uart_parity_t_UART_PARITY_EVEN: uart_parity_t = 1;
5403pub const uart_parity_t_UART_PARITY_ODD: uart_parity_t = 2;
5404#[doc = " \\brief UART Parity enumeration"]
5405#[doc = " \\ingroup hardware_uart"]
5406pub type uart_parity_t = crate::ctypes::c_uint;
5407extern "C" {
5408 #[doc = " \\brief Initialise a UART"]
5409 #[doc = " \\ingroup hardware_uart"]
5410 #[doc = ""]
5411 #[doc = " Put the UART into a known state, and enable it. Must be called before other"]
5412 #[doc = " functions."]
5413 #[doc = ""]
5414 #[doc = " \\note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen,"]
5415 #[doc = " and this function will return the configured baud rate."]
5416 #[doc = ""]
5417 #[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
5418 #[doc = " \\param baudrate Baudrate of UART in Hz"]
5419 #[doc = " \\return Actual set baudrate"]
5420 pub fn uart_init(uart: *mut uart_inst_t, baudrate: uint) -> uint;
5421}
5422extern "C" {
5423 #[doc = " \\brief DeInitialise a UART"]
5424 #[doc = " \\ingroup hardware_uart"]
5425 #[doc = ""]
5426 #[doc = " Disable the UART if it is no longer used. Must be reinitialised before"]
5427 #[doc = " being used again."]
5428 #[doc = ""]
5429 #[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
5430 pub fn uart_deinit(uart: *mut uart_inst_t);
5431}
5432extern "C" {
5433 #[doc = " \\brief Set UART baud rate"]
5434 #[doc = " \\ingroup hardware_uart"]
5435 #[doc = ""]
5436 #[doc = " Set baud rate as close as possible to requested, and return actual rate selected."]
5437 #[doc = ""]
5438 #[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
5439 #[doc = " \\param baudrate Baudrate in Hz"]
5440 pub fn uart_set_baudrate(uart: *mut uart_inst_t, baudrate: uint) -> uint;
5441}
5442extern "C" {
5443 #[doc = " \\brief Set CR/LF conversion on UART"]
5444 #[doc = " \\ingroup hardware_uart"]
5445 #[doc = ""]
5446 #[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
5447 #[doc = " \\param translate If true, convert line feeds to carriage return on transmissions"]
5448 pub fn uart_set_translate_crlf(uart: *mut uart_inst_t, translate: bool);
5449}
5450extern "C" {
5451 #[doc = " \\brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty"]
5452 #[doc = " \\ingroup hardware_uart"]
5453 #[doc = ""]
5454 #[doc = " \\param uart UART instance. \\ref uart0 or \\ref uart1"]
5455 #[doc = " \\param us the number of microseconds to wait at most (may be 0 for an instantaneous check)"]
5456 #[doc = " \\return true if the RX FIFO became non empty before the timeout, false otherwise"]
5457 pub fn uart_is_readable_within_us(uart: *mut uart_inst_t, us: u32) -> bool;
5458}
5459extern "C" {
5460 #[doc = " \\brief Set up the default UART and assign it to the default GPIO's"]
5461 #[doc = " \\ingroup pico_stdlib"]
5462 #[doc = ""]
5463 #[doc = " By default this will use UART 0, with TX to pin GPIO 0,"]
5464 #[doc = " RX to pin GPIO 1, and the baudrate to 115200"]
5465 #[doc = ""]
5466 #[doc = " Calling this method also initializes stdin/stdout over UART if the"]
5467 #[doc = " @ref pico_stdio_uart library is linked."]
5468 #[doc = ""]
5469 #[doc = " Defaults can be changed using configuration defines,"]
5470 #[doc = " PICO_DEFAULT_UART_INSTANCE,"]
5471 #[doc = " PICO_DEFAULT_UART_BAUD_RATE"]
5472 #[doc = " PICO_DEFAULT_UART_TX_PIN"]
5473 #[doc = " PICO_DEFAULT_UART_RX_PIN"]
5474 pub fn setup_default_uart();
5475}
5476extern "C" {
5477 #[doc = " \\brief Initialise the system clock to 48MHz"]
5478 #[doc = " \\ingroup pico_stdlib"]
5479 #[doc = ""]
5480 #[doc = " Set the system clock to 48MHz, and set the peripheral clock to match."]
5481 pub fn set_sys_clock_48mhz();
5482}
5483extern "C" {
5484 #[doc = " \\brief Initialise the system clock"]
5485 #[doc = " \\ingroup pico_stdlib"]
5486 #[doc = ""]
5487 #[doc = " \\param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL"]
5488 #[doc = " \\param post_div1 The first post divider for the SYS PLL"]
5489 #[doc = " \\param post_div2 The second post divider for the SYS PLL."]
5490 #[doc = ""]
5491 #[doc = " See the PLL documentation in the datasheet for details of driving the PLLs."]
5492 pub fn set_sys_clock_pll(vco_freq: u32, post_div1: uint, post_div2: uint);
5493}
5494extern "C" {
5495 #[doc = " \\brief Check if a given system clock frequency is valid/attainable"]
5496 #[doc = " \\ingroup pico_stdlib"]
5497 #[doc = ""]
5498 #[doc = " \\param freq_khz Requested frequency"]
5499 #[doc = " \\param vco_freq_out On success, the voltage controller oscillator frequeucny to be used by the SYS PLL"]
5500 #[doc = " \\param post_div1_out On success, The first post divider for the SYS PLL"]
5501 #[doc = " \\param post_div2_out On success, The second post divider for the SYS PLL."]
5502 #[doc = " @return true if the frequency is possible and the output parameters have been written."]
5503 pub fn check_sys_clock_khz(
5504 freq_khz: u32,
5505 vco_freq_out: *mut uint,
5506 post_div1_out: *mut uint,
5507 post_div2_out: *mut uint,
5508 ) -> bool;
5509}
5510pub type __builtin_va_list = [__va_list_tag; 1usize];
5511#[repr(C)]
5512#[derive(Debug, Copy, Clone)]
5513pub struct __va_list_tag {
5514 pub gp_offset: crate::ctypes::c_uint,
5515 pub fp_offset: crate::ctypes::c_uint,
5516 pub overflow_arg_area: *mut crate::ctypes::c_void,
5517 pub reg_save_area: *mut crate::ctypes::c_void,
5518}
5519#[test]
5520fn bindgen_test_layout___va_list_tag() {
5521 assert_eq!(
5522 ::core::mem::size_of::<__va_list_tag>(),
5523 24usize,
5524 concat!("Size of: ", stringify!(__va_list_tag))
5525 );
5526 assert_eq!(
5527 ::core::mem::align_of::<__va_list_tag>(),
5528 8usize,
5529 concat!("Alignment of ", stringify!(__va_list_tag))
5530 );
5531 assert_eq!(
5532 unsafe { &(*(::core::ptr::null::<__va_list_tag>())).gp_offset as *const _ as usize },
5533 0usize,
5534 concat!(
5535 "Offset of field: ",
5536 stringify!(__va_list_tag),
5537 "::",
5538 stringify!(gp_offset)
5539 )
5540 );
5541 assert_eq!(
5542 unsafe { &(*(::core::ptr::null::<__va_list_tag>())).fp_offset as *const _ as usize },
5543 4usize,
5544 concat!(
5545 "Offset of field: ",
5546 stringify!(__va_list_tag),
5547 "::",
5548 stringify!(fp_offset)
5549 )
5550 );
5551 assert_eq!(
5552 unsafe {
5553 &(*(::core::ptr::null::<__va_list_tag>())).overflow_arg_area as *const _ as usize
5554 },
5555 8usize,
5556 concat!(
5557 "Offset of field: ",
5558 stringify!(__va_list_tag),
5559 "::",
5560 stringify!(overflow_arg_area)
5561 )
5562 );
5563 assert_eq!(
5564 unsafe { &(*(::core::ptr::null::<__va_list_tag>())).reg_save_area as *const _ as usize },
5565 16usize,
5566 concat!(
5567 "Offset of field: ",
5568 stringify!(__va_list_tag),
5569 "::",
5570 stringify!(reg_save_area)
5571 )
5572 );
5573}