Modules§
- ctypes
- ctypes for no-std
Structs§
- __
Bindgen Union Field - __
darwin_ pthread_ handler_ rec - __
mbstate_ t - __
va_ list_ tag - _opaque_
pthread_ attr_ t - _opaque_
pthread_ cond_ t - _opaque_
pthread_ condattr_ t - _opaque_
pthread_ mutex_ t - _opaque_
pthread_ mutexattr_ t - _opaque_
pthread_ once_ t - _opaque_
pthread_ rwlock_ t - _opaque_
pthread_ rwlockattr_ t - _opaque_
pthread_ t - absolute_
time_ t - alarm_
pool - datetime_
t - \struct datetime_t \ingroup util_datetime \brief Structure containing date and time information
- interp_
hw_ t - padsbank0_
hw_ t - repeating_
timer - \brief Information about a repeating timer \ingroup repeating_timer \return
- sio_
hw_ t - stdio_
driver - timer_
hw_ t - uart_
hw_ t - uart_
inst
Constants§
- ADC_
BASE - BUSCTRL_
BASE - CLOCKS_
BASE - DMA_
BASE - GPIO_IN
- GPIO_
OUT - I2C0_
BASE - I2C1_
BASE - INT8_
MAX - INT8_
MIN - INT16_
MAX - INT16_
MIN - INT32_
MAX - INT32_
MIN - INT64_
MAX - INT64_
MIN - INTPTR_
MAX - INTPTR_
MIN - INT_
FAST8_ MAX - INT_
FAST8_ MIN - INT_
FAST16_ MAX - INT_
FAST16_ MIN - INT_
FAST32_ MAX - INT_
FAST32_ MIN - INT_
FAST64_ MAX - INT_
FAST64_ MIN - INT_
LEAS T8_ MAX - INT_
LEAS T8_ MIN - INT_
LEAS T16_ MAX - INT_
LEAS T16_ MIN - INT_
LEAS T32_ MAX - INT_
LEAS T32_ MIN - INT_
LEAS T64_ MAX - INT_
LEAS T64_ MIN - IO_
BANK0_ BASE - IO_
QSPI_ BASE - NUM_
BANK0_ GPIOS - NUM_
CORES - NUM_
DMA_ CHANNELS - NUM_
IRQS - NUM_
PIOS - NUM_
PIO_ STATE_ MACHINES - NUM_
PWM_ SLICES - NUM_
SPIN_ LOCKS - NUM_
TIMERS - NUM_
UARTS - N_GPIOS
- PADS_
BANK0_ BASE - PADS_
BANK0_ GPIO0_ BITS - PADS_
BANK0_ GPIO0_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO0_ DRIVE_ BITS - PADS_
BANK0_ GPIO0_ DRIVE_ LSB - PADS_
BANK0_ GPIO0_ DRIVE_ MSB - PADS_
BANK0_ GPIO0_ DRIVE_ RESET - PADS_
BANK0_ GPIO0_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO0_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO0_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO0_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO0_ IE_ ACCESS - PADS_
BANK0_ GPIO0_ IE_ BITS - PADS_
BANK0_ GPIO0_ IE_ LSB - PADS_
BANK0_ GPIO0_ IE_ MSB - PADS_
BANK0_ GPIO0_ IE_ RESET - PADS_
BANK0_ GPIO0_ OD_ ACCESS - PADS_
BANK0_ GPIO0_ OD_ BITS - PADS_
BANK0_ GPIO0_ OD_ LSB - PADS_
BANK0_ GPIO0_ OD_ MSB - PADS_
BANK0_ GPIO0_ OD_ RESET - PADS_
BANK0_ GPIO0_ OFFSET - PADS_
BANK0_ GPIO0_ PDE_ ACCESS - PADS_
BANK0_ GPIO0_ PDE_ BITS - PADS_
BANK0_ GPIO0_ PDE_ LSB - PADS_
BANK0_ GPIO0_ PDE_ MSB - PADS_
BANK0_ GPIO0_ PDE_ RESET - PADS_
BANK0_ GPIO0_ PUE_ ACCESS - PADS_
BANK0_ GPIO0_ PUE_ BITS - PADS_
BANK0_ GPIO0_ PUE_ LSB - PADS_
BANK0_ GPIO0_ PUE_ MSB - PADS_
BANK0_ GPIO0_ PUE_ RESET - PADS_
BANK0_ GPIO0_ RESET - PADS_
BANK0_ GPIO0_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO0_ SCHMITT_ BITS - PADS_
BANK0_ GPIO0_ SCHMITT_ LSB - PADS_
BANK0_ GPIO0_ SCHMITT_ MSB - PADS_
BANK0_ GPIO0_ SCHMITT_ RESET - PADS_
BANK0_ GPIO0_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO0_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO0_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO0_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO0_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO1_ BITS - PADS_
BANK0_ GPIO1_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO1_ DRIVE_ BITS - PADS_
BANK0_ GPIO1_ DRIVE_ LSB - PADS_
BANK0_ GPIO1_ DRIVE_ MSB - PADS_
BANK0_ GPIO1_ DRIVE_ RESET - PADS_
BANK0_ GPIO1_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO1_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO1_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO1_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO1_ IE_ ACCESS - PADS_
BANK0_ GPIO1_ IE_ BITS - PADS_
BANK0_ GPIO1_ IE_ LSB - PADS_
BANK0_ GPIO1_ IE_ MSB - PADS_
BANK0_ GPIO1_ IE_ RESET - PADS_
BANK0_ GPIO1_ OD_ ACCESS - PADS_
BANK0_ GPIO1_ OD_ BITS - PADS_
BANK0_ GPIO1_ OD_ LSB - PADS_
BANK0_ GPIO1_ OD_ MSB - PADS_
BANK0_ GPIO1_ OD_ RESET - PADS_
BANK0_ GPIO1_ OFFSET - PADS_
BANK0_ GPIO1_ PDE_ ACCESS - PADS_
BANK0_ GPIO1_ PDE_ BITS - PADS_
BANK0_ GPIO1_ PDE_ LSB - PADS_
BANK0_ GPIO1_ PDE_ MSB - PADS_
BANK0_ GPIO1_ PDE_ RESET - PADS_
BANK0_ GPIO1_ PUE_ ACCESS - PADS_
BANK0_ GPIO1_ PUE_ BITS - PADS_
BANK0_ GPIO1_ PUE_ LSB - PADS_
BANK0_ GPIO1_ PUE_ MSB - PADS_
BANK0_ GPIO1_ PUE_ RESET - PADS_
BANK0_ GPIO1_ RESET - PADS_
BANK0_ GPIO1_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO1_ SCHMITT_ BITS - PADS_
BANK0_ GPIO1_ SCHMITT_ LSB - PADS_
BANK0_ GPIO1_ SCHMITT_ MSB - PADS_
BANK0_ GPIO1_ SCHMITT_ RESET - PADS_
BANK0_ GPIO1_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO1_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO1_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO1_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO1_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO2_ BITS - PADS_
BANK0_ GPIO2_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO2_ DRIVE_ BITS - PADS_
BANK0_ GPIO2_ DRIVE_ LSB - PADS_
BANK0_ GPIO2_ DRIVE_ MSB - PADS_
BANK0_ GPIO2_ DRIVE_ RESET - PADS_
BANK0_ GPIO2_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO2_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO2_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO2_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO2_ IE_ ACCESS - PADS_
BANK0_ GPIO2_ IE_ BITS - PADS_
BANK0_ GPIO2_ IE_ LSB - PADS_
BANK0_ GPIO2_ IE_ MSB - PADS_
BANK0_ GPIO2_ IE_ RESET - PADS_
BANK0_ GPIO2_ OD_ ACCESS - PADS_
BANK0_ GPIO2_ OD_ BITS - PADS_
BANK0_ GPIO2_ OD_ LSB - PADS_
BANK0_ GPIO2_ OD_ MSB - PADS_
BANK0_ GPIO2_ OD_ RESET - PADS_
BANK0_ GPIO2_ OFFSET - PADS_
BANK0_ GPIO2_ PDE_ ACCESS - PADS_
BANK0_ GPIO2_ PDE_ BITS - PADS_
BANK0_ GPIO2_ PDE_ LSB - PADS_
BANK0_ GPIO2_ PDE_ MSB - PADS_
BANK0_ GPIO2_ PDE_ RESET - PADS_
BANK0_ GPIO2_ PUE_ ACCESS - PADS_
BANK0_ GPIO2_ PUE_ BITS - PADS_
BANK0_ GPIO2_ PUE_ LSB - PADS_
BANK0_ GPIO2_ PUE_ MSB - PADS_
BANK0_ GPIO2_ PUE_ RESET - PADS_
BANK0_ GPIO2_ RESET - PADS_
BANK0_ GPIO2_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO2_ SCHMITT_ BITS - PADS_
BANK0_ GPIO2_ SCHMITT_ LSB - PADS_
BANK0_ GPIO2_ SCHMITT_ MSB - PADS_
BANK0_ GPIO2_ SCHMITT_ RESET - PADS_
BANK0_ GPIO2_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO2_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO2_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO2_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO2_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO3_ BITS - PADS_
BANK0_ GPIO3_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO3_ DRIVE_ BITS - PADS_
BANK0_ GPIO3_ DRIVE_ LSB - PADS_
BANK0_ GPIO3_ DRIVE_ MSB - PADS_
BANK0_ GPIO3_ DRIVE_ RESET - PADS_
BANK0_ GPIO3_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO3_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO3_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO3_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO3_ IE_ ACCESS - PADS_
BANK0_ GPIO3_ IE_ BITS - PADS_
BANK0_ GPIO3_ IE_ LSB - PADS_
BANK0_ GPIO3_ IE_ MSB - PADS_
BANK0_ GPIO3_ IE_ RESET - PADS_
BANK0_ GPIO3_ OD_ ACCESS - PADS_
BANK0_ GPIO3_ OD_ BITS - PADS_
BANK0_ GPIO3_ OD_ LSB - PADS_
BANK0_ GPIO3_ OD_ MSB - PADS_
BANK0_ GPIO3_ OD_ RESET - PADS_
BANK0_ GPIO3_ OFFSET - PADS_
BANK0_ GPIO3_ PDE_ ACCESS - PADS_
BANK0_ GPIO3_ PDE_ BITS - PADS_
BANK0_ GPIO3_ PDE_ LSB - PADS_
BANK0_ GPIO3_ PDE_ MSB - PADS_
BANK0_ GPIO3_ PDE_ RESET - PADS_
BANK0_ GPIO3_ PUE_ ACCESS - PADS_
BANK0_ GPIO3_ PUE_ BITS - PADS_
BANK0_ GPIO3_ PUE_ LSB - PADS_
BANK0_ GPIO3_ PUE_ MSB - PADS_
BANK0_ GPIO3_ PUE_ RESET - PADS_
BANK0_ GPIO3_ RESET - PADS_
BANK0_ GPIO3_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO3_ SCHMITT_ BITS - PADS_
BANK0_ GPIO3_ SCHMITT_ LSB - PADS_
BANK0_ GPIO3_ SCHMITT_ MSB - PADS_
BANK0_ GPIO3_ SCHMITT_ RESET - PADS_
BANK0_ GPIO3_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO3_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO3_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO3_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO3_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO4_ BITS - PADS_
BANK0_ GPIO4_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO4_ DRIVE_ BITS - PADS_
BANK0_ GPIO4_ DRIVE_ LSB - PADS_
BANK0_ GPIO4_ DRIVE_ MSB - PADS_
BANK0_ GPIO4_ DRIVE_ RESET - PADS_
BANK0_ GPIO4_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO4_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO4_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO4_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO4_ IE_ ACCESS - PADS_
BANK0_ GPIO4_ IE_ BITS - PADS_
BANK0_ GPIO4_ IE_ LSB - PADS_
BANK0_ GPIO4_ IE_ MSB - PADS_
BANK0_ GPIO4_ IE_ RESET - PADS_
BANK0_ GPIO4_ OD_ ACCESS - PADS_
BANK0_ GPIO4_ OD_ BITS - PADS_
BANK0_ GPIO4_ OD_ LSB - PADS_
BANK0_ GPIO4_ OD_ MSB - PADS_
BANK0_ GPIO4_ OD_ RESET - PADS_
BANK0_ GPIO4_ OFFSET - PADS_
BANK0_ GPIO4_ PDE_ ACCESS - PADS_
BANK0_ GPIO4_ PDE_ BITS - PADS_
BANK0_ GPIO4_ PDE_ LSB - PADS_
BANK0_ GPIO4_ PDE_ MSB - PADS_
BANK0_ GPIO4_ PDE_ RESET - PADS_
BANK0_ GPIO4_ PUE_ ACCESS - PADS_
BANK0_ GPIO4_ PUE_ BITS - PADS_
BANK0_ GPIO4_ PUE_ LSB - PADS_
BANK0_ GPIO4_ PUE_ MSB - PADS_
BANK0_ GPIO4_ PUE_ RESET - PADS_
BANK0_ GPIO4_ RESET - PADS_
BANK0_ GPIO4_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO4_ SCHMITT_ BITS - PADS_
BANK0_ GPIO4_ SCHMITT_ LSB - PADS_
BANK0_ GPIO4_ SCHMITT_ MSB - PADS_
BANK0_ GPIO4_ SCHMITT_ RESET - PADS_
BANK0_ GPIO4_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO4_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO4_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO4_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO4_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO5_ BITS - PADS_
BANK0_ GPIO5_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO5_ DRIVE_ BITS - PADS_
BANK0_ GPIO5_ DRIVE_ LSB - PADS_
BANK0_ GPIO5_ DRIVE_ MSB - PADS_
BANK0_ GPIO5_ DRIVE_ RESET - PADS_
BANK0_ GPIO5_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO5_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO5_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO5_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO5_ IE_ ACCESS - PADS_
BANK0_ GPIO5_ IE_ BITS - PADS_
BANK0_ GPIO5_ IE_ LSB - PADS_
BANK0_ GPIO5_ IE_ MSB - PADS_
BANK0_ GPIO5_ IE_ RESET - PADS_
BANK0_ GPIO5_ OD_ ACCESS - PADS_
BANK0_ GPIO5_ OD_ BITS - PADS_
BANK0_ GPIO5_ OD_ LSB - PADS_
BANK0_ GPIO5_ OD_ MSB - PADS_
BANK0_ GPIO5_ OD_ RESET - PADS_
BANK0_ GPIO5_ OFFSET - PADS_
BANK0_ GPIO5_ PDE_ ACCESS - PADS_
BANK0_ GPIO5_ PDE_ BITS - PADS_
BANK0_ GPIO5_ PDE_ LSB - PADS_
BANK0_ GPIO5_ PDE_ MSB - PADS_
BANK0_ GPIO5_ PDE_ RESET - PADS_
BANK0_ GPIO5_ PUE_ ACCESS - PADS_
BANK0_ GPIO5_ PUE_ BITS - PADS_
BANK0_ GPIO5_ PUE_ LSB - PADS_
BANK0_ GPIO5_ PUE_ MSB - PADS_
BANK0_ GPIO5_ PUE_ RESET - PADS_
BANK0_ GPIO5_ RESET - PADS_
BANK0_ GPIO5_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO5_ SCHMITT_ BITS - PADS_
BANK0_ GPIO5_ SCHMITT_ LSB - PADS_
BANK0_ GPIO5_ SCHMITT_ MSB - PADS_
BANK0_ GPIO5_ SCHMITT_ RESET - PADS_
BANK0_ GPIO5_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO5_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO5_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO5_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO5_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO6_ BITS - PADS_
BANK0_ GPIO6_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO6_ DRIVE_ BITS - PADS_
BANK0_ GPIO6_ DRIVE_ LSB - PADS_
BANK0_ GPIO6_ DRIVE_ MSB - PADS_
BANK0_ GPIO6_ DRIVE_ RESET - PADS_
BANK0_ GPIO6_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO6_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO6_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO6_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO6_ IE_ ACCESS - PADS_
BANK0_ GPIO6_ IE_ BITS - PADS_
BANK0_ GPIO6_ IE_ LSB - PADS_
BANK0_ GPIO6_ IE_ MSB - PADS_
BANK0_ GPIO6_ IE_ RESET - PADS_
BANK0_ GPIO6_ OD_ ACCESS - PADS_
BANK0_ GPIO6_ OD_ BITS - PADS_
BANK0_ GPIO6_ OD_ LSB - PADS_
BANK0_ GPIO6_ OD_ MSB - PADS_
BANK0_ GPIO6_ OD_ RESET - PADS_
BANK0_ GPIO6_ OFFSET - PADS_
BANK0_ GPIO6_ PDE_ ACCESS - PADS_
BANK0_ GPIO6_ PDE_ BITS - PADS_
BANK0_ GPIO6_ PDE_ LSB - PADS_
BANK0_ GPIO6_ PDE_ MSB - PADS_
BANK0_ GPIO6_ PDE_ RESET - PADS_
BANK0_ GPIO6_ PUE_ ACCESS - PADS_
BANK0_ GPIO6_ PUE_ BITS - PADS_
BANK0_ GPIO6_ PUE_ LSB - PADS_
BANK0_ GPIO6_ PUE_ MSB - PADS_
BANK0_ GPIO6_ PUE_ RESET - PADS_
BANK0_ GPIO6_ RESET - PADS_
BANK0_ GPIO6_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO6_ SCHMITT_ BITS - PADS_
BANK0_ GPIO6_ SCHMITT_ LSB - PADS_
BANK0_ GPIO6_ SCHMITT_ MSB - PADS_
BANK0_ GPIO6_ SCHMITT_ RESET - PADS_
BANK0_ GPIO6_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO6_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO6_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO6_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO6_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO7_ BITS - PADS_
BANK0_ GPIO7_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO7_ DRIVE_ BITS - PADS_
BANK0_ GPIO7_ DRIVE_ LSB - PADS_
BANK0_ GPIO7_ DRIVE_ MSB - PADS_
BANK0_ GPIO7_ DRIVE_ RESET - PADS_
BANK0_ GPIO7_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO7_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO7_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO7_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO7_ IE_ ACCESS - PADS_
BANK0_ GPIO7_ IE_ BITS - PADS_
BANK0_ GPIO7_ IE_ LSB - PADS_
BANK0_ GPIO7_ IE_ MSB - PADS_
BANK0_ GPIO7_ IE_ RESET - PADS_
BANK0_ GPIO7_ OD_ ACCESS - PADS_
BANK0_ GPIO7_ OD_ BITS - PADS_
BANK0_ GPIO7_ OD_ LSB - PADS_
BANK0_ GPIO7_ OD_ MSB - PADS_
BANK0_ GPIO7_ OD_ RESET - PADS_
BANK0_ GPIO7_ OFFSET - PADS_
BANK0_ GPIO7_ PDE_ ACCESS - PADS_
BANK0_ GPIO7_ PDE_ BITS - PADS_
BANK0_ GPIO7_ PDE_ LSB - PADS_
BANK0_ GPIO7_ PDE_ MSB - PADS_
BANK0_ GPIO7_ PDE_ RESET - PADS_
BANK0_ GPIO7_ PUE_ ACCESS - PADS_
BANK0_ GPIO7_ PUE_ BITS - PADS_
BANK0_ GPIO7_ PUE_ LSB - PADS_
BANK0_ GPIO7_ PUE_ MSB - PADS_
BANK0_ GPIO7_ PUE_ RESET - PADS_
BANK0_ GPIO7_ RESET - PADS_
BANK0_ GPIO7_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO7_ SCHMITT_ BITS - PADS_
BANK0_ GPIO7_ SCHMITT_ LSB - PADS_
BANK0_ GPIO7_ SCHMITT_ MSB - PADS_
BANK0_ GPIO7_ SCHMITT_ RESET - PADS_
BANK0_ GPIO7_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO7_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO7_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO7_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO7_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO8_ BITS - PADS_
BANK0_ GPIO8_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO8_ DRIVE_ BITS - PADS_
BANK0_ GPIO8_ DRIVE_ LSB - PADS_
BANK0_ GPIO8_ DRIVE_ MSB - PADS_
BANK0_ GPIO8_ DRIVE_ RESET - PADS_
BANK0_ GPIO8_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO8_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO8_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO8_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO8_ IE_ ACCESS - PADS_
BANK0_ GPIO8_ IE_ BITS - PADS_
BANK0_ GPIO8_ IE_ LSB - PADS_
BANK0_ GPIO8_ IE_ MSB - PADS_
BANK0_ GPIO8_ IE_ RESET - PADS_
BANK0_ GPIO8_ OD_ ACCESS - PADS_
BANK0_ GPIO8_ OD_ BITS - PADS_
BANK0_ GPIO8_ OD_ LSB - PADS_
BANK0_ GPIO8_ OD_ MSB - PADS_
BANK0_ GPIO8_ OD_ RESET - PADS_
BANK0_ GPIO8_ OFFSET - PADS_
BANK0_ GPIO8_ PDE_ ACCESS - PADS_
BANK0_ GPIO8_ PDE_ BITS - PADS_
BANK0_ GPIO8_ PDE_ LSB - PADS_
BANK0_ GPIO8_ PDE_ MSB - PADS_
BANK0_ GPIO8_ PDE_ RESET - PADS_
BANK0_ GPIO8_ PUE_ ACCESS - PADS_
BANK0_ GPIO8_ PUE_ BITS - PADS_
BANK0_ GPIO8_ PUE_ LSB - PADS_
BANK0_ GPIO8_ PUE_ MSB - PADS_
BANK0_ GPIO8_ PUE_ RESET - PADS_
BANK0_ GPIO8_ RESET - PADS_
BANK0_ GPIO8_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO8_ SCHMITT_ BITS - PADS_
BANK0_ GPIO8_ SCHMITT_ LSB - PADS_
BANK0_ GPIO8_ SCHMITT_ MSB - PADS_
BANK0_ GPIO8_ SCHMITT_ RESET - PADS_
BANK0_ GPIO8_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO8_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO8_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO8_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO8_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO9_ BITS - PADS_
BANK0_ GPIO9_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO9_ DRIVE_ BITS - PADS_
BANK0_ GPIO9_ DRIVE_ LSB - PADS_
BANK0_ GPIO9_ DRIVE_ MSB - PADS_
BANK0_ GPIO9_ DRIVE_ RESET - PADS_
BANK0_ GPIO9_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO9_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO9_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO9_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO9_ IE_ ACCESS - PADS_
BANK0_ GPIO9_ IE_ BITS - PADS_
BANK0_ GPIO9_ IE_ LSB - PADS_
BANK0_ GPIO9_ IE_ MSB - PADS_
BANK0_ GPIO9_ IE_ RESET - PADS_
BANK0_ GPIO9_ OD_ ACCESS - PADS_
BANK0_ GPIO9_ OD_ BITS - PADS_
BANK0_ GPIO9_ OD_ LSB - PADS_
BANK0_ GPIO9_ OD_ MSB - PADS_
BANK0_ GPIO9_ OD_ RESET - PADS_
BANK0_ GPIO9_ OFFSET - PADS_
BANK0_ GPIO9_ PDE_ ACCESS - PADS_
BANK0_ GPIO9_ PDE_ BITS - PADS_
BANK0_ GPIO9_ PDE_ LSB - PADS_
BANK0_ GPIO9_ PDE_ MSB - PADS_
BANK0_ GPIO9_ PDE_ RESET - PADS_
BANK0_ GPIO9_ PUE_ ACCESS - PADS_
BANK0_ GPIO9_ PUE_ BITS - PADS_
BANK0_ GPIO9_ PUE_ LSB - PADS_
BANK0_ GPIO9_ PUE_ MSB - PADS_
BANK0_ GPIO9_ PUE_ RESET - PADS_
BANK0_ GPIO9_ RESET - PADS_
BANK0_ GPIO9_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO9_ SCHMITT_ BITS - PADS_
BANK0_ GPIO9_ SCHMITT_ LSB - PADS_
BANK0_ GPIO9_ SCHMITT_ MSB - PADS_
BANK0_ GPIO9_ SCHMITT_ RESET - PADS_
BANK0_ GPIO9_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO9_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO9_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO9_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO9_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO10_ BITS - PADS_
BANK0_ GPIO10_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO10_ DRIVE_ BITS - PADS_
BANK0_ GPIO10_ DRIVE_ LSB - PADS_
BANK0_ GPIO10_ DRIVE_ MSB - PADS_
BANK0_ GPIO10_ DRIVE_ RESET - PADS_
BANK0_ GPIO10_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO10_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO10_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO10_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO10_ IE_ ACCESS - PADS_
BANK0_ GPIO10_ IE_ BITS - PADS_
BANK0_ GPIO10_ IE_ LSB - PADS_
BANK0_ GPIO10_ IE_ MSB - PADS_
BANK0_ GPIO10_ IE_ RESET - PADS_
BANK0_ GPIO10_ OD_ ACCESS - PADS_
BANK0_ GPIO10_ OD_ BITS - PADS_
BANK0_ GPIO10_ OD_ LSB - PADS_
BANK0_ GPIO10_ OD_ MSB - PADS_
BANK0_ GPIO10_ OD_ RESET - PADS_
BANK0_ GPIO10_ OFFSET - PADS_
BANK0_ GPIO10_ PDE_ ACCESS - PADS_
BANK0_ GPIO10_ PDE_ BITS - PADS_
BANK0_ GPIO10_ PDE_ LSB - PADS_
BANK0_ GPIO10_ PDE_ MSB - PADS_
BANK0_ GPIO10_ PDE_ RESET - PADS_
BANK0_ GPIO10_ PUE_ ACCESS - PADS_
BANK0_ GPIO10_ PUE_ BITS - PADS_
BANK0_ GPIO10_ PUE_ LSB - PADS_
BANK0_ GPIO10_ PUE_ MSB - PADS_
BANK0_ GPIO10_ PUE_ RESET - PADS_
BANK0_ GPIO10_ RESET - PADS_
BANK0_ GPIO10_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO10_ SCHMITT_ BITS - PADS_
BANK0_ GPIO10_ SCHMITT_ LSB - PADS_
BANK0_ GPIO10_ SCHMITT_ MSB - PADS_
BANK0_ GPIO10_ SCHMITT_ RESET - PADS_
BANK0_ GPIO10_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO10_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO10_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO10_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO10_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO11_ BITS - PADS_
BANK0_ GPIO11_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO11_ DRIVE_ BITS - PADS_
BANK0_ GPIO11_ DRIVE_ LSB - PADS_
BANK0_ GPIO11_ DRIVE_ MSB - PADS_
BANK0_ GPIO11_ DRIVE_ RESET - PADS_
BANK0_ GPIO11_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO11_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO11_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO11_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO11_ IE_ ACCESS - PADS_
BANK0_ GPIO11_ IE_ BITS - PADS_
BANK0_ GPIO11_ IE_ LSB - PADS_
BANK0_ GPIO11_ IE_ MSB - PADS_
BANK0_ GPIO11_ IE_ RESET - PADS_
BANK0_ GPIO11_ OD_ ACCESS - PADS_
BANK0_ GPIO11_ OD_ BITS - PADS_
BANK0_ GPIO11_ OD_ LSB - PADS_
BANK0_ GPIO11_ OD_ MSB - PADS_
BANK0_ GPIO11_ OD_ RESET - PADS_
BANK0_ GPIO11_ OFFSET - PADS_
BANK0_ GPIO11_ PDE_ ACCESS - PADS_
BANK0_ GPIO11_ PDE_ BITS - PADS_
BANK0_ GPIO11_ PDE_ LSB - PADS_
BANK0_ GPIO11_ PDE_ MSB - PADS_
BANK0_ GPIO11_ PDE_ RESET - PADS_
BANK0_ GPIO11_ PUE_ ACCESS - PADS_
BANK0_ GPIO11_ PUE_ BITS - PADS_
BANK0_ GPIO11_ PUE_ LSB - PADS_
BANK0_ GPIO11_ PUE_ MSB - PADS_
BANK0_ GPIO11_ PUE_ RESET - PADS_
BANK0_ GPIO11_ RESET - PADS_
BANK0_ GPIO11_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO11_ SCHMITT_ BITS - PADS_
BANK0_ GPIO11_ SCHMITT_ LSB - PADS_
BANK0_ GPIO11_ SCHMITT_ MSB - PADS_
BANK0_ GPIO11_ SCHMITT_ RESET - PADS_
BANK0_ GPIO11_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO11_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO11_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO11_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO11_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO12_ BITS - PADS_
BANK0_ GPIO12_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO12_ DRIVE_ BITS - PADS_
BANK0_ GPIO12_ DRIVE_ LSB - PADS_
BANK0_ GPIO12_ DRIVE_ MSB - PADS_
BANK0_ GPIO12_ DRIVE_ RESET - PADS_
BANK0_ GPIO12_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO12_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO12_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO12_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO12_ IE_ ACCESS - PADS_
BANK0_ GPIO12_ IE_ BITS - PADS_
BANK0_ GPIO12_ IE_ LSB - PADS_
BANK0_ GPIO12_ IE_ MSB - PADS_
BANK0_ GPIO12_ IE_ RESET - PADS_
BANK0_ GPIO12_ OD_ ACCESS - PADS_
BANK0_ GPIO12_ OD_ BITS - PADS_
BANK0_ GPIO12_ OD_ LSB - PADS_
BANK0_ GPIO12_ OD_ MSB - PADS_
BANK0_ GPIO12_ OD_ RESET - PADS_
BANK0_ GPIO12_ OFFSET - PADS_
BANK0_ GPIO12_ PDE_ ACCESS - PADS_
BANK0_ GPIO12_ PDE_ BITS - PADS_
BANK0_ GPIO12_ PDE_ LSB - PADS_
BANK0_ GPIO12_ PDE_ MSB - PADS_
BANK0_ GPIO12_ PDE_ RESET - PADS_
BANK0_ GPIO12_ PUE_ ACCESS - PADS_
BANK0_ GPIO12_ PUE_ BITS - PADS_
BANK0_ GPIO12_ PUE_ LSB - PADS_
BANK0_ GPIO12_ PUE_ MSB - PADS_
BANK0_ GPIO12_ PUE_ RESET - PADS_
BANK0_ GPIO12_ RESET - PADS_
BANK0_ GPIO12_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO12_ SCHMITT_ BITS - PADS_
BANK0_ GPIO12_ SCHMITT_ LSB - PADS_
BANK0_ GPIO12_ SCHMITT_ MSB - PADS_
BANK0_ GPIO12_ SCHMITT_ RESET - PADS_
BANK0_ GPIO12_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO12_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO12_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO12_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO12_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO13_ BITS - PADS_
BANK0_ GPIO13_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO13_ DRIVE_ BITS - PADS_
BANK0_ GPIO13_ DRIVE_ LSB - PADS_
BANK0_ GPIO13_ DRIVE_ MSB - PADS_
BANK0_ GPIO13_ DRIVE_ RESET - PADS_
BANK0_ GPIO13_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO13_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO13_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO13_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO13_ IE_ ACCESS - PADS_
BANK0_ GPIO13_ IE_ BITS - PADS_
BANK0_ GPIO13_ IE_ LSB - PADS_
BANK0_ GPIO13_ IE_ MSB - PADS_
BANK0_ GPIO13_ IE_ RESET - PADS_
BANK0_ GPIO13_ OD_ ACCESS - PADS_
BANK0_ GPIO13_ OD_ BITS - PADS_
BANK0_ GPIO13_ OD_ LSB - PADS_
BANK0_ GPIO13_ OD_ MSB - PADS_
BANK0_ GPIO13_ OD_ RESET - PADS_
BANK0_ GPIO13_ OFFSET - PADS_
BANK0_ GPIO13_ PDE_ ACCESS - PADS_
BANK0_ GPIO13_ PDE_ BITS - PADS_
BANK0_ GPIO13_ PDE_ LSB - PADS_
BANK0_ GPIO13_ PDE_ MSB - PADS_
BANK0_ GPIO13_ PDE_ RESET - PADS_
BANK0_ GPIO13_ PUE_ ACCESS - PADS_
BANK0_ GPIO13_ PUE_ BITS - PADS_
BANK0_ GPIO13_ PUE_ LSB - PADS_
BANK0_ GPIO13_ PUE_ MSB - PADS_
BANK0_ GPIO13_ PUE_ RESET - PADS_
BANK0_ GPIO13_ RESET - PADS_
BANK0_ GPIO13_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO13_ SCHMITT_ BITS - PADS_
BANK0_ GPIO13_ SCHMITT_ LSB - PADS_
BANK0_ GPIO13_ SCHMITT_ MSB - PADS_
BANK0_ GPIO13_ SCHMITT_ RESET - PADS_
BANK0_ GPIO13_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO13_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO13_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO13_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO13_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO14_ BITS - PADS_
BANK0_ GPIO14_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO14_ DRIVE_ BITS - PADS_
BANK0_ GPIO14_ DRIVE_ LSB - PADS_
BANK0_ GPIO14_ DRIVE_ MSB - PADS_
BANK0_ GPIO14_ DRIVE_ RESET - PADS_
BANK0_ GPIO14_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO14_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO14_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO14_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO14_ IE_ ACCESS - PADS_
BANK0_ GPIO14_ IE_ BITS - PADS_
BANK0_ GPIO14_ IE_ LSB - PADS_
BANK0_ GPIO14_ IE_ MSB - PADS_
BANK0_ GPIO14_ IE_ RESET - PADS_
BANK0_ GPIO14_ OD_ ACCESS - PADS_
BANK0_ GPIO14_ OD_ BITS - PADS_
BANK0_ GPIO14_ OD_ LSB - PADS_
BANK0_ GPIO14_ OD_ MSB - PADS_
BANK0_ GPIO14_ OD_ RESET - PADS_
BANK0_ GPIO14_ OFFSET - PADS_
BANK0_ GPIO14_ PDE_ ACCESS - PADS_
BANK0_ GPIO14_ PDE_ BITS - PADS_
BANK0_ GPIO14_ PDE_ LSB - PADS_
BANK0_ GPIO14_ PDE_ MSB - PADS_
BANK0_ GPIO14_ PDE_ RESET - PADS_
BANK0_ GPIO14_ PUE_ ACCESS - PADS_
BANK0_ GPIO14_ PUE_ BITS - PADS_
BANK0_ GPIO14_ PUE_ LSB - PADS_
BANK0_ GPIO14_ PUE_ MSB - PADS_
BANK0_ GPIO14_ PUE_ RESET - PADS_
BANK0_ GPIO14_ RESET - PADS_
BANK0_ GPIO14_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO14_ SCHMITT_ BITS - PADS_
BANK0_ GPIO14_ SCHMITT_ LSB - PADS_
BANK0_ GPIO14_ SCHMITT_ MSB - PADS_
BANK0_ GPIO14_ SCHMITT_ RESET - PADS_
BANK0_ GPIO14_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO14_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO14_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO14_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO14_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO15_ BITS - PADS_
BANK0_ GPIO15_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO15_ DRIVE_ BITS - PADS_
BANK0_ GPIO15_ DRIVE_ LSB - PADS_
BANK0_ GPIO15_ DRIVE_ MSB - PADS_
BANK0_ GPIO15_ DRIVE_ RESET - PADS_
BANK0_ GPIO15_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO15_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO15_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO15_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO15_ IE_ ACCESS - PADS_
BANK0_ GPIO15_ IE_ BITS - PADS_
BANK0_ GPIO15_ IE_ LSB - PADS_
BANK0_ GPIO15_ IE_ MSB - PADS_
BANK0_ GPIO15_ IE_ RESET - PADS_
BANK0_ GPIO15_ OD_ ACCESS - PADS_
BANK0_ GPIO15_ OD_ BITS - PADS_
BANK0_ GPIO15_ OD_ LSB - PADS_
BANK0_ GPIO15_ OD_ MSB - PADS_
BANK0_ GPIO15_ OD_ RESET - PADS_
BANK0_ GPIO15_ OFFSET - PADS_
BANK0_ GPIO15_ PDE_ ACCESS - PADS_
BANK0_ GPIO15_ PDE_ BITS - PADS_
BANK0_ GPIO15_ PDE_ LSB - PADS_
BANK0_ GPIO15_ PDE_ MSB - PADS_
BANK0_ GPIO15_ PDE_ RESET - PADS_
BANK0_ GPIO15_ PUE_ ACCESS - PADS_
BANK0_ GPIO15_ PUE_ BITS - PADS_
BANK0_ GPIO15_ PUE_ LSB - PADS_
BANK0_ GPIO15_ PUE_ MSB - PADS_
BANK0_ GPIO15_ PUE_ RESET - PADS_
BANK0_ GPIO15_ RESET - PADS_
BANK0_ GPIO15_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO15_ SCHMITT_ BITS - PADS_
BANK0_ GPIO15_ SCHMITT_ LSB - PADS_
BANK0_ GPIO15_ SCHMITT_ MSB - PADS_
BANK0_ GPIO15_ SCHMITT_ RESET - PADS_
BANK0_ GPIO15_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO15_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO15_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO15_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO15_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO16_ BITS - PADS_
BANK0_ GPIO16_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO16_ DRIVE_ BITS - PADS_
BANK0_ GPIO16_ DRIVE_ LSB - PADS_
BANK0_ GPIO16_ DRIVE_ MSB - PADS_
BANK0_ GPIO16_ DRIVE_ RESET - PADS_
BANK0_ GPIO16_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO16_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO16_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO16_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO16_ IE_ ACCESS - PADS_
BANK0_ GPIO16_ IE_ BITS - PADS_
BANK0_ GPIO16_ IE_ LSB - PADS_
BANK0_ GPIO16_ IE_ MSB - PADS_
BANK0_ GPIO16_ IE_ RESET - PADS_
BANK0_ GPIO16_ OD_ ACCESS - PADS_
BANK0_ GPIO16_ OD_ BITS - PADS_
BANK0_ GPIO16_ OD_ LSB - PADS_
BANK0_ GPIO16_ OD_ MSB - PADS_
BANK0_ GPIO16_ OD_ RESET - PADS_
BANK0_ GPIO16_ OFFSET - PADS_
BANK0_ GPIO16_ PDE_ ACCESS - PADS_
BANK0_ GPIO16_ PDE_ BITS - PADS_
BANK0_ GPIO16_ PDE_ LSB - PADS_
BANK0_ GPIO16_ PDE_ MSB - PADS_
BANK0_ GPIO16_ PDE_ RESET - PADS_
BANK0_ GPIO16_ PUE_ ACCESS - PADS_
BANK0_ GPIO16_ PUE_ BITS - PADS_
BANK0_ GPIO16_ PUE_ LSB - PADS_
BANK0_ GPIO16_ PUE_ MSB - PADS_
BANK0_ GPIO16_ PUE_ RESET - PADS_
BANK0_ GPIO16_ RESET - PADS_
BANK0_ GPIO16_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO16_ SCHMITT_ BITS - PADS_
BANK0_ GPIO16_ SCHMITT_ LSB - PADS_
BANK0_ GPIO16_ SCHMITT_ MSB - PADS_
BANK0_ GPIO16_ SCHMITT_ RESET - PADS_
BANK0_ GPIO16_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO16_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO16_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO16_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO16_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO17_ BITS - PADS_
BANK0_ GPIO17_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO17_ DRIVE_ BITS - PADS_
BANK0_ GPIO17_ DRIVE_ LSB - PADS_
BANK0_ GPIO17_ DRIVE_ MSB - PADS_
BANK0_ GPIO17_ DRIVE_ RESET - PADS_
BANK0_ GPIO17_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO17_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO17_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO17_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO17_ IE_ ACCESS - PADS_
BANK0_ GPIO17_ IE_ BITS - PADS_
BANK0_ GPIO17_ IE_ LSB - PADS_
BANK0_ GPIO17_ IE_ MSB - PADS_
BANK0_ GPIO17_ IE_ RESET - PADS_
BANK0_ GPIO17_ OD_ ACCESS - PADS_
BANK0_ GPIO17_ OD_ BITS - PADS_
BANK0_ GPIO17_ OD_ LSB - PADS_
BANK0_ GPIO17_ OD_ MSB - PADS_
BANK0_ GPIO17_ OD_ RESET - PADS_
BANK0_ GPIO17_ OFFSET - PADS_
BANK0_ GPIO17_ PDE_ ACCESS - PADS_
BANK0_ GPIO17_ PDE_ BITS - PADS_
BANK0_ GPIO17_ PDE_ LSB - PADS_
BANK0_ GPIO17_ PDE_ MSB - PADS_
BANK0_ GPIO17_ PDE_ RESET - PADS_
BANK0_ GPIO17_ PUE_ ACCESS - PADS_
BANK0_ GPIO17_ PUE_ BITS - PADS_
BANK0_ GPIO17_ PUE_ LSB - PADS_
BANK0_ GPIO17_ PUE_ MSB - PADS_
BANK0_ GPIO17_ PUE_ RESET - PADS_
BANK0_ GPIO17_ RESET - PADS_
BANK0_ GPIO17_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO17_ SCHMITT_ BITS - PADS_
BANK0_ GPIO17_ SCHMITT_ LSB - PADS_
BANK0_ GPIO17_ SCHMITT_ MSB - PADS_
BANK0_ GPIO17_ SCHMITT_ RESET - PADS_
BANK0_ GPIO17_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO17_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO17_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO17_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO17_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO18_ BITS - PADS_
BANK0_ GPIO18_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO18_ DRIVE_ BITS - PADS_
BANK0_ GPIO18_ DRIVE_ LSB - PADS_
BANK0_ GPIO18_ DRIVE_ MSB - PADS_
BANK0_ GPIO18_ DRIVE_ RESET - PADS_
BANK0_ GPIO18_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO18_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO18_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO18_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO18_ IE_ ACCESS - PADS_
BANK0_ GPIO18_ IE_ BITS - PADS_
BANK0_ GPIO18_ IE_ LSB - PADS_
BANK0_ GPIO18_ IE_ MSB - PADS_
BANK0_ GPIO18_ IE_ RESET - PADS_
BANK0_ GPIO18_ OD_ ACCESS - PADS_
BANK0_ GPIO18_ OD_ BITS - PADS_
BANK0_ GPIO18_ OD_ LSB - PADS_
BANK0_ GPIO18_ OD_ MSB - PADS_
BANK0_ GPIO18_ OD_ RESET - PADS_
BANK0_ GPIO18_ OFFSET - PADS_
BANK0_ GPIO18_ PDE_ ACCESS - PADS_
BANK0_ GPIO18_ PDE_ BITS - PADS_
BANK0_ GPIO18_ PDE_ LSB - PADS_
BANK0_ GPIO18_ PDE_ MSB - PADS_
BANK0_ GPIO18_ PDE_ RESET - PADS_
BANK0_ GPIO18_ PUE_ ACCESS - PADS_
BANK0_ GPIO18_ PUE_ BITS - PADS_
BANK0_ GPIO18_ PUE_ LSB - PADS_
BANK0_ GPIO18_ PUE_ MSB - PADS_
BANK0_ GPIO18_ PUE_ RESET - PADS_
BANK0_ GPIO18_ RESET - PADS_
BANK0_ GPIO18_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO18_ SCHMITT_ BITS - PADS_
BANK0_ GPIO18_ SCHMITT_ LSB - PADS_
BANK0_ GPIO18_ SCHMITT_ MSB - PADS_
BANK0_ GPIO18_ SCHMITT_ RESET - PADS_
BANK0_ GPIO18_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO18_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO18_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO18_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO18_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO19_ BITS - PADS_
BANK0_ GPIO19_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO19_ DRIVE_ BITS - PADS_
BANK0_ GPIO19_ DRIVE_ LSB - PADS_
BANK0_ GPIO19_ DRIVE_ MSB - PADS_
BANK0_ GPIO19_ DRIVE_ RESET - PADS_
BANK0_ GPIO19_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO19_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO19_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO19_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO19_ IE_ ACCESS - PADS_
BANK0_ GPIO19_ IE_ BITS - PADS_
BANK0_ GPIO19_ IE_ LSB - PADS_
BANK0_ GPIO19_ IE_ MSB - PADS_
BANK0_ GPIO19_ IE_ RESET - PADS_
BANK0_ GPIO19_ OD_ ACCESS - PADS_
BANK0_ GPIO19_ OD_ BITS - PADS_
BANK0_ GPIO19_ OD_ LSB - PADS_
BANK0_ GPIO19_ OD_ MSB - PADS_
BANK0_ GPIO19_ OD_ RESET - PADS_
BANK0_ GPIO19_ OFFSET - PADS_
BANK0_ GPIO19_ PDE_ ACCESS - PADS_
BANK0_ GPIO19_ PDE_ BITS - PADS_
BANK0_ GPIO19_ PDE_ LSB - PADS_
BANK0_ GPIO19_ PDE_ MSB - PADS_
BANK0_ GPIO19_ PDE_ RESET - PADS_
BANK0_ GPIO19_ PUE_ ACCESS - PADS_
BANK0_ GPIO19_ PUE_ BITS - PADS_
BANK0_ GPIO19_ PUE_ LSB - PADS_
BANK0_ GPIO19_ PUE_ MSB - PADS_
BANK0_ GPIO19_ PUE_ RESET - PADS_
BANK0_ GPIO19_ RESET - PADS_
BANK0_ GPIO19_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO19_ SCHMITT_ BITS - PADS_
BANK0_ GPIO19_ SCHMITT_ LSB - PADS_
BANK0_ GPIO19_ SCHMITT_ MSB - PADS_
BANK0_ GPIO19_ SCHMITT_ RESET - PADS_
BANK0_ GPIO19_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO19_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO19_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO19_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO19_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO20_ BITS - PADS_
BANK0_ GPIO20_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO20_ DRIVE_ BITS - PADS_
BANK0_ GPIO20_ DRIVE_ LSB - PADS_
BANK0_ GPIO20_ DRIVE_ MSB - PADS_
BANK0_ GPIO20_ DRIVE_ RESET - PADS_
BANK0_ GPIO20_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO20_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO20_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO20_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO20_ IE_ ACCESS - PADS_
BANK0_ GPIO20_ IE_ BITS - PADS_
BANK0_ GPIO20_ IE_ LSB - PADS_
BANK0_ GPIO20_ IE_ MSB - PADS_
BANK0_ GPIO20_ IE_ RESET - PADS_
BANK0_ GPIO20_ OD_ ACCESS - PADS_
BANK0_ GPIO20_ OD_ BITS - PADS_
BANK0_ GPIO20_ OD_ LSB - PADS_
BANK0_ GPIO20_ OD_ MSB - PADS_
BANK0_ GPIO20_ OD_ RESET - PADS_
BANK0_ GPIO20_ OFFSET - PADS_
BANK0_ GPIO20_ PDE_ ACCESS - PADS_
BANK0_ GPIO20_ PDE_ BITS - PADS_
BANK0_ GPIO20_ PDE_ LSB - PADS_
BANK0_ GPIO20_ PDE_ MSB - PADS_
BANK0_ GPIO20_ PDE_ RESET - PADS_
BANK0_ GPIO20_ PUE_ ACCESS - PADS_
BANK0_ GPIO20_ PUE_ BITS - PADS_
BANK0_ GPIO20_ PUE_ LSB - PADS_
BANK0_ GPIO20_ PUE_ MSB - PADS_
BANK0_ GPIO20_ PUE_ RESET - PADS_
BANK0_ GPIO20_ RESET - PADS_
BANK0_ GPIO20_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO20_ SCHMITT_ BITS - PADS_
BANK0_ GPIO20_ SCHMITT_ LSB - PADS_
BANK0_ GPIO20_ SCHMITT_ MSB - PADS_
BANK0_ GPIO20_ SCHMITT_ RESET - PADS_
BANK0_ GPIO20_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO20_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO20_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO20_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO20_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO21_ BITS - PADS_
BANK0_ GPIO21_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO21_ DRIVE_ BITS - PADS_
BANK0_ GPIO21_ DRIVE_ LSB - PADS_
BANK0_ GPIO21_ DRIVE_ MSB - PADS_
BANK0_ GPIO21_ DRIVE_ RESET - PADS_
BANK0_ GPIO21_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO21_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO21_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO21_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO21_ IE_ ACCESS - PADS_
BANK0_ GPIO21_ IE_ BITS - PADS_
BANK0_ GPIO21_ IE_ LSB - PADS_
BANK0_ GPIO21_ IE_ MSB - PADS_
BANK0_ GPIO21_ IE_ RESET - PADS_
BANK0_ GPIO21_ OD_ ACCESS - PADS_
BANK0_ GPIO21_ OD_ BITS - PADS_
BANK0_ GPIO21_ OD_ LSB - PADS_
BANK0_ GPIO21_ OD_ MSB - PADS_
BANK0_ GPIO21_ OD_ RESET - PADS_
BANK0_ GPIO21_ OFFSET - PADS_
BANK0_ GPIO21_ PDE_ ACCESS - PADS_
BANK0_ GPIO21_ PDE_ BITS - PADS_
BANK0_ GPIO21_ PDE_ LSB - PADS_
BANK0_ GPIO21_ PDE_ MSB - PADS_
BANK0_ GPIO21_ PDE_ RESET - PADS_
BANK0_ GPIO21_ PUE_ ACCESS - PADS_
BANK0_ GPIO21_ PUE_ BITS - PADS_
BANK0_ GPIO21_ PUE_ LSB - PADS_
BANK0_ GPIO21_ PUE_ MSB - PADS_
BANK0_ GPIO21_ PUE_ RESET - PADS_
BANK0_ GPIO21_ RESET - PADS_
BANK0_ GPIO21_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO21_ SCHMITT_ BITS - PADS_
BANK0_ GPIO21_ SCHMITT_ LSB - PADS_
BANK0_ GPIO21_ SCHMITT_ MSB - PADS_
BANK0_ GPIO21_ SCHMITT_ RESET - PADS_
BANK0_ GPIO21_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO21_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO21_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO21_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO21_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO22_ BITS - PADS_
BANK0_ GPIO22_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO22_ DRIVE_ BITS - PADS_
BANK0_ GPIO22_ DRIVE_ LSB - PADS_
BANK0_ GPIO22_ DRIVE_ MSB - PADS_
BANK0_ GPIO22_ DRIVE_ RESET - PADS_
BANK0_ GPIO22_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO22_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO22_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO22_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO22_ IE_ ACCESS - PADS_
BANK0_ GPIO22_ IE_ BITS - PADS_
BANK0_ GPIO22_ IE_ LSB - PADS_
BANK0_ GPIO22_ IE_ MSB - PADS_
BANK0_ GPIO22_ IE_ RESET - PADS_
BANK0_ GPIO22_ OD_ ACCESS - PADS_
BANK0_ GPIO22_ OD_ BITS - PADS_
BANK0_ GPIO22_ OD_ LSB - PADS_
BANK0_ GPIO22_ OD_ MSB - PADS_
BANK0_ GPIO22_ OD_ RESET - PADS_
BANK0_ GPIO22_ OFFSET - PADS_
BANK0_ GPIO22_ PDE_ ACCESS - PADS_
BANK0_ GPIO22_ PDE_ BITS - PADS_
BANK0_ GPIO22_ PDE_ LSB - PADS_
BANK0_ GPIO22_ PDE_ MSB - PADS_
BANK0_ GPIO22_ PDE_ RESET - PADS_
BANK0_ GPIO22_ PUE_ ACCESS - PADS_
BANK0_ GPIO22_ PUE_ BITS - PADS_
BANK0_ GPIO22_ PUE_ LSB - PADS_
BANK0_ GPIO22_ PUE_ MSB - PADS_
BANK0_ GPIO22_ PUE_ RESET - PADS_
BANK0_ GPIO22_ RESET - PADS_
BANK0_ GPIO22_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO22_ SCHMITT_ BITS - PADS_
BANK0_ GPIO22_ SCHMITT_ LSB - PADS_
BANK0_ GPIO22_ SCHMITT_ MSB - PADS_
BANK0_ GPIO22_ SCHMITT_ RESET - PADS_
BANK0_ GPIO22_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO22_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO22_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO22_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO22_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO23_ BITS - PADS_
BANK0_ GPIO23_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO23_ DRIVE_ BITS - PADS_
BANK0_ GPIO23_ DRIVE_ LSB - PADS_
BANK0_ GPIO23_ DRIVE_ MSB - PADS_
BANK0_ GPIO23_ DRIVE_ RESET - PADS_
BANK0_ GPIO23_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO23_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO23_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO23_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO23_ IE_ ACCESS - PADS_
BANK0_ GPIO23_ IE_ BITS - PADS_
BANK0_ GPIO23_ IE_ LSB - PADS_
BANK0_ GPIO23_ IE_ MSB - PADS_
BANK0_ GPIO23_ IE_ RESET - PADS_
BANK0_ GPIO23_ OD_ ACCESS - PADS_
BANK0_ GPIO23_ OD_ BITS - PADS_
BANK0_ GPIO23_ OD_ LSB - PADS_
BANK0_ GPIO23_ OD_ MSB - PADS_
BANK0_ GPIO23_ OD_ RESET - PADS_
BANK0_ GPIO23_ OFFSET - PADS_
BANK0_ GPIO23_ PDE_ ACCESS - PADS_
BANK0_ GPIO23_ PDE_ BITS - PADS_
BANK0_ GPIO23_ PDE_ LSB - PADS_
BANK0_ GPIO23_ PDE_ MSB - PADS_
BANK0_ GPIO23_ PDE_ RESET - PADS_
BANK0_ GPIO23_ PUE_ ACCESS - PADS_
BANK0_ GPIO23_ PUE_ BITS - PADS_
BANK0_ GPIO23_ PUE_ LSB - PADS_
BANK0_ GPIO23_ PUE_ MSB - PADS_
BANK0_ GPIO23_ PUE_ RESET - PADS_
BANK0_ GPIO23_ RESET - PADS_
BANK0_ GPIO23_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO23_ SCHMITT_ BITS - PADS_
BANK0_ GPIO23_ SCHMITT_ LSB - PADS_
BANK0_ GPIO23_ SCHMITT_ MSB - PADS_
BANK0_ GPIO23_ SCHMITT_ RESET - PADS_
BANK0_ GPIO23_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO23_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO23_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO23_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO23_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO24_ BITS - PADS_
BANK0_ GPIO24_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO24_ DRIVE_ BITS - PADS_
BANK0_ GPIO24_ DRIVE_ LSB - PADS_
BANK0_ GPIO24_ DRIVE_ MSB - PADS_
BANK0_ GPIO24_ DRIVE_ RESET - PADS_
BANK0_ GPIO24_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO24_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO24_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO24_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO24_ IE_ ACCESS - PADS_
BANK0_ GPIO24_ IE_ BITS - PADS_
BANK0_ GPIO24_ IE_ LSB - PADS_
BANK0_ GPIO24_ IE_ MSB - PADS_
BANK0_ GPIO24_ IE_ RESET - PADS_
BANK0_ GPIO24_ OD_ ACCESS - PADS_
BANK0_ GPIO24_ OD_ BITS - PADS_
BANK0_ GPIO24_ OD_ LSB - PADS_
BANK0_ GPIO24_ OD_ MSB - PADS_
BANK0_ GPIO24_ OD_ RESET - PADS_
BANK0_ GPIO24_ OFFSET - PADS_
BANK0_ GPIO24_ PDE_ ACCESS - PADS_
BANK0_ GPIO24_ PDE_ BITS - PADS_
BANK0_ GPIO24_ PDE_ LSB - PADS_
BANK0_ GPIO24_ PDE_ MSB - PADS_
BANK0_ GPIO24_ PDE_ RESET - PADS_
BANK0_ GPIO24_ PUE_ ACCESS - PADS_
BANK0_ GPIO24_ PUE_ BITS - PADS_
BANK0_ GPIO24_ PUE_ LSB - PADS_
BANK0_ GPIO24_ PUE_ MSB - PADS_
BANK0_ GPIO24_ PUE_ RESET - PADS_
BANK0_ GPIO24_ RESET - PADS_
BANK0_ GPIO24_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO24_ SCHMITT_ BITS - PADS_
BANK0_ GPIO24_ SCHMITT_ LSB - PADS_
BANK0_ GPIO24_ SCHMITT_ MSB - PADS_
BANK0_ GPIO24_ SCHMITT_ RESET - PADS_
BANK0_ GPIO24_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO24_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO24_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO24_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO24_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO25_ BITS - PADS_
BANK0_ GPIO25_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO25_ DRIVE_ BITS - PADS_
BANK0_ GPIO25_ DRIVE_ LSB - PADS_
BANK0_ GPIO25_ DRIVE_ MSB - PADS_
BANK0_ GPIO25_ DRIVE_ RESET - PADS_
BANK0_ GPIO25_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO25_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO25_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO25_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO25_ IE_ ACCESS - PADS_
BANK0_ GPIO25_ IE_ BITS - PADS_
BANK0_ GPIO25_ IE_ LSB - PADS_
BANK0_ GPIO25_ IE_ MSB - PADS_
BANK0_ GPIO25_ IE_ RESET - PADS_
BANK0_ GPIO25_ OD_ ACCESS - PADS_
BANK0_ GPIO25_ OD_ BITS - PADS_
BANK0_ GPIO25_ OD_ LSB - PADS_
BANK0_ GPIO25_ OD_ MSB - PADS_
BANK0_ GPIO25_ OD_ RESET - PADS_
BANK0_ GPIO25_ OFFSET - PADS_
BANK0_ GPIO25_ PDE_ ACCESS - PADS_
BANK0_ GPIO25_ PDE_ BITS - PADS_
BANK0_ GPIO25_ PDE_ LSB - PADS_
BANK0_ GPIO25_ PDE_ MSB - PADS_
BANK0_ GPIO25_ PDE_ RESET - PADS_
BANK0_ GPIO25_ PUE_ ACCESS - PADS_
BANK0_ GPIO25_ PUE_ BITS - PADS_
BANK0_ GPIO25_ PUE_ LSB - PADS_
BANK0_ GPIO25_ PUE_ MSB - PADS_
BANK0_ GPIO25_ PUE_ RESET - PADS_
BANK0_ GPIO25_ RESET - PADS_
BANK0_ GPIO25_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO25_ SCHMITT_ BITS - PADS_
BANK0_ GPIO25_ SCHMITT_ LSB - PADS_
BANK0_ GPIO25_ SCHMITT_ MSB - PADS_
BANK0_ GPIO25_ SCHMITT_ RESET - PADS_
BANK0_ GPIO25_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO25_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO25_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO25_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO25_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO26_ BITS - PADS_
BANK0_ GPIO26_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO26_ DRIVE_ BITS - PADS_
BANK0_ GPIO26_ DRIVE_ LSB - PADS_
BANK0_ GPIO26_ DRIVE_ MSB - PADS_
BANK0_ GPIO26_ DRIVE_ RESET - PADS_
BANK0_ GPIO26_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO26_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO26_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO26_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO26_ IE_ ACCESS - PADS_
BANK0_ GPIO26_ IE_ BITS - PADS_
BANK0_ GPIO26_ IE_ LSB - PADS_
BANK0_ GPIO26_ IE_ MSB - PADS_
BANK0_ GPIO26_ IE_ RESET - PADS_
BANK0_ GPIO26_ OD_ ACCESS - PADS_
BANK0_ GPIO26_ OD_ BITS - PADS_
BANK0_ GPIO26_ OD_ LSB - PADS_
BANK0_ GPIO26_ OD_ MSB - PADS_
BANK0_ GPIO26_ OD_ RESET - PADS_
BANK0_ GPIO26_ OFFSET - PADS_
BANK0_ GPIO26_ PDE_ ACCESS - PADS_
BANK0_ GPIO26_ PDE_ BITS - PADS_
BANK0_ GPIO26_ PDE_ LSB - PADS_
BANK0_ GPIO26_ PDE_ MSB - PADS_
BANK0_ GPIO26_ PDE_ RESET - PADS_
BANK0_ GPIO26_ PUE_ ACCESS - PADS_
BANK0_ GPIO26_ PUE_ BITS - PADS_
BANK0_ GPIO26_ PUE_ LSB - PADS_
BANK0_ GPIO26_ PUE_ MSB - PADS_
BANK0_ GPIO26_ PUE_ RESET - PADS_
BANK0_ GPIO26_ RESET - PADS_
BANK0_ GPIO26_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO26_ SCHMITT_ BITS - PADS_
BANK0_ GPIO26_ SCHMITT_ LSB - PADS_
BANK0_ GPIO26_ SCHMITT_ MSB - PADS_
BANK0_ GPIO26_ SCHMITT_ RESET - PADS_
BANK0_ GPIO26_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO26_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO26_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO26_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO26_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO27_ BITS - PADS_
BANK0_ GPIO27_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO27_ DRIVE_ BITS - PADS_
BANK0_ GPIO27_ DRIVE_ LSB - PADS_
BANK0_ GPIO27_ DRIVE_ MSB - PADS_
BANK0_ GPIO27_ DRIVE_ RESET - PADS_
BANK0_ GPIO27_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO27_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO27_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO27_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO27_ IE_ ACCESS - PADS_
BANK0_ GPIO27_ IE_ BITS - PADS_
BANK0_ GPIO27_ IE_ LSB - PADS_
BANK0_ GPIO27_ IE_ MSB - PADS_
BANK0_ GPIO27_ IE_ RESET - PADS_
BANK0_ GPIO27_ OD_ ACCESS - PADS_
BANK0_ GPIO27_ OD_ BITS - PADS_
BANK0_ GPIO27_ OD_ LSB - PADS_
BANK0_ GPIO27_ OD_ MSB - PADS_
BANK0_ GPIO27_ OD_ RESET - PADS_
BANK0_ GPIO27_ OFFSET - PADS_
BANK0_ GPIO27_ PDE_ ACCESS - PADS_
BANK0_ GPIO27_ PDE_ BITS - PADS_
BANK0_ GPIO27_ PDE_ LSB - PADS_
BANK0_ GPIO27_ PDE_ MSB - PADS_
BANK0_ GPIO27_ PDE_ RESET - PADS_
BANK0_ GPIO27_ PUE_ ACCESS - PADS_
BANK0_ GPIO27_ PUE_ BITS - PADS_
BANK0_ GPIO27_ PUE_ LSB - PADS_
BANK0_ GPIO27_ PUE_ MSB - PADS_
BANK0_ GPIO27_ PUE_ RESET - PADS_
BANK0_ GPIO27_ RESET - PADS_
BANK0_ GPIO27_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO27_ SCHMITT_ BITS - PADS_
BANK0_ GPIO27_ SCHMITT_ LSB - PADS_
BANK0_ GPIO27_ SCHMITT_ MSB - PADS_
BANK0_ GPIO27_ SCHMITT_ RESET - PADS_
BANK0_ GPIO27_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO27_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO27_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO27_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO27_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO28_ BITS - PADS_
BANK0_ GPIO28_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO28_ DRIVE_ BITS - PADS_
BANK0_ GPIO28_ DRIVE_ LSB - PADS_
BANK0_ GPIO28_ DRIVE_ MSB - PADS_
BANK0_ GPIO28_ DRIVE_ RESET - PADS_
BANK0_ GPIO28_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO28_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO28_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO28_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO28_ IE_ ACCESS - PADS_
BANK0_ GPIO28_ IE_ BITS - PADS_
BANK0_ GPIO28_ IE_ LSB - PADS_
BANK0_ GPIO28_ IE_ MSB - PADS_
BANK0_ GPIO28_ IE_ RESET - PADS_
BANK0_ GPIO28_ OD_ ACCESS - PADS_
BANK0_ GPIO28_ OD_ BITS - PADS_
BANK0_ GPIO28_ OD_ LSB - PADS_
BANK0_ GPIO28_ OD_ MSB - PADS_
BANK0_ GPIO28_ OD_ RESET - PADS_
BANK0_ GPIO28_ OFFSET - PADS_
BANK0_ GPIO28_ PDE_ ACCESS - PADS_
BANK0_ GPIO28_ PDE_ BITS - PADS_
BANK0_ GPIO28_ PDE_ LSB - PADS_
BANK0_ GPIO28_ PDE_ MSB - PADS_
BANK0_ GPIO28_ PDE_ RESET - PADS_
BANK0_ GPIO28_ PUE_ ACCESS - PADS_
BANK0_ GPIO28_ PUE_ BITS - PADS_
BANK0_ GPIO28_ PUE_ LSB - PADS_
BANK0_ GPIO28_ PUE_ MSB - PADS_
BANK0_ GPIO28_ PUE_ RESET - PADS_
BANK0_ GPIO28_ RESET - PADS_
BANK0_ GPIO28_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO28_ SCHMITT_ BITS - PADS_
BANK0_ GPIO28_ SCHMITT_ LSB - PADS_
BANK0_ GPIO28_ SCHMITT_ MSB - PADS_
BANK0_ GPIO28_ SCHMITT_ RESET - PADS_
BANK0_ GPIO28_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO28_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO28_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO28_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO28_ SLEWFAST_ RESET - PADS_
BANK0_ GPIO29_ BITS - PADS_
BANK0_ GPIO29_ DRIVE_ ACCESS - PADS_
BANK0_ GPIO29_ DRIVE_ BITS - PADS_
BANK0_ GPIO29_ DRIVE_ LSB - PADS_
BANK0_ GPIO29_ DRIVE_ MSB - PADS_
BANK0_ GPIO29_ DRIVE_ RESET - PADS_
BANK0_ GPIO29_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ GPIO29_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ GPIO29_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ GPIO29_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ GPIO29_ IE_ ACCESS - PADS_
BANK0_ GPIO29_ IE_ BITS - PADS_
BANK0_ GPIO29_ IE_ LSB - PADS_
BANK0_ GPIO29_ IE_ MSB - PADS_
BANK0_ GPIO29_ IE_ RESET - PADS_
BANK0_ GPIO29_ OD_ ACCESS - PADS_
BANK0_ GPIO29_ OD_ BITS - PADS_
BANK0_ GPIO29_ OD_ LSB - PADS_
BANK0_ GPIO29_ OD_ MSB - PADS_
BANK0_ GPIO29_ OD_ RESET - PADS_
BANK0_ GPIO29_ OFFSET - PADS_
BANK0_ GPIO29_ PDE_ ACCESS - PADS_
BANK0_ GPIO29_ PDE_ BITS - PADS_
BANK0_ GPIO29_ PDE_ LSB - PADS_
BANK0_ GPIO29_ PDE_ MSB - PADS_
BANK0_ GPIO29_ PDE_ RESET - PADS_
BANK0_ GPIO29_ PUE_ ACCESS - PADS_
BANK0_ GPIO29_ PUE_ BITS - PADS_
BANK0_ GPIO29_ PUE_ LSB - PADS_
BANK0_ GPIO29_ PUE_ MSB - PADS_
BANK0_ GPIO29_ PUE_ RESET - PADS_
BANK0_ GPIO29_ RESET - PADS_
BANK0_ GPIO29_ SCHMITT_ ACCESS - PADS_
BANK0_ GPIO29_ SCHMITT_ BITS - PADS_
BANK0_ GPIO29_ SCHMITT_ LSB - PADS_
BANK0_ GPIO29_ SCHMITT_ MSB - PADS_
BANK0_ GPIO29_ SCHMITT_ RESET - PADS_
BANK0_ GPIO29_ SLEWFAST_ ACCESS - PADS_
BANK0_ GPIO29_ SLEWFAST_ BITS - PADS_
BANK0_ GPIO29_ SLEWFAST_ LSB - PADS_
BANK0_ GPIO29_ SLEWFAST_ MSB - PADS_
BANK0_ GPIO29_ SLEWFAST_ RESET - PADS_
BANK0_ SWCLK_ BITS - PADS_
BANK0_ SWCLK_ DRIVE_ ACCESS - PADS_
BANK0_ SWCLK_ DRIVE_ BITS - PADS_
BANK0_ SWCLK_ DRIVE_ LSB - PADS_
BANK0_ SWCLK_ DRIVE_ MSB - PADS_
BANK0_ SWCLK_ DRIVE_ RESET - PADS_
BANK0_ SWCLK_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ SWCLK_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ SWCLK_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ SWCLK_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ SWCLK_ IE_ ACCESS - PADS_
BANK0_ SWCLK_ IE_ BITS - PADS_
BANK0_ SWCLK_ IE_ LSB - PADS_
BANK0_ SWCLK_ IE_ MSB - PADS_
BANK0_ SWCLK_ IE_ RESET - PADS_
BANK0_ SWCLK_ OD_ ACCESS - PADS_
BANK0_ SWCLK_ OD_ BITS - PADS_
BANK0_ SWCLK_ OD_ LSB - PADS_
BANK0_ SWCLK_ OD_ MSB - PADS_
BANK0_ SWCLK_ OD_ RESET - PADS_
BANK0_ SWCLK_ OFFSET - PADS_
BANK0_ SWCLK_ PDE_ ACCESS - PADS_
BANK0_ SWCLK_ PDE_ BITS - PADS_
BANK0_ SWCLK_ PDE_ LSB - PADS_
BANK0_ SWCLK_ PDE_ MSB - PADS_
BANK0_ SWCLK_ PDE_ RESET - PADS_
BANK0_ SWCLK_ PUE_ ACCESS - PADS_
BANK0_ SWCLK_ PUE_ BITS - PADS_
BANK0_ SWCLK_ PUE_ LSB - PADS_
BANK0_ SWCLK_ PUE_ MSB - PADS_
BANK0_ SWCLK_ PUE_ RESET - PADS_
BANK0_ SWCLK_ RESET - PADS_
BANK0_ SWCLK_ SCHMITT_ ACCESS - PADS_
BANK0_ SWCLK_ SCHMITT_ BITS - PADS_
BANK0_ SWCLK_ SCHMITT_ LSB - PADS_
BANK0_ SWCLK_ SCHMITT_ MSB - PADS_
BANK0_ SWCLK_ SCHMITT_ RESET - PADS_
BANK0_ SWCLK_ SLEWFAST_ ACCESS - PADS_
BANK0_ SWCLK_ SLEWFAST_ BITS - PADS_
BANK0_ SWCLK_ SLEWFAST_ LSB - PADS_
BANK0_ SWCLK_ SLEWFAST_ MSB - PADS_
BANK0_ SWCLK_ SLEWFAST_ RESET - PADS_
BANK0_ SWD_ BITS - PADS_
BANK0_ SWD_ DRIVE_ ACCESS - PADS_
BANK0_ SWD_ DRIVE_ BITS - PADS_
BANK0_ SWD_ DRIVE_ LSB - PADS_
BANK0_ SWD_ DRIVE_ MSB - PADS_
BANK0_ SWD_ DRIVE_ RESET - PADS_
BANK0_ SWD_ DRIVE_ VALUE_ 2MA - PADS_
BANK0_ SWD_ DRIVE_ VALUE_ 4MA - PADS_
BANK0_ SWD_ DRIVE_ VALUE_ 8MA - PADS_
BANK0_ SWD_ DRIVE_ VALUE_ 12MA - PADS_
BANK0_ SWD_ IE_ ACCESS - PADS_
BANK0_ SWD_ IE_ BITS - PADS_
BANK0_ SWD_ IE_ LSB - PADS_
BANK0_ SWD_ IE_ MSB - PADS_
BANK0_ SWD_ IE_ RESET - PADS_
BANK0_ SWD_ OD_ ACCESS - PADS_
BANK0_ SWD_ OD_ BITS - PADS_
BANK0_ SWD_ OD_ LSB - PADS_
BANK0_ SWD_ OD_ MSB - PADS_
BANK0_ SWD_ OD_ RESET - PADS_
BANK0_ SWD_ OFFSET - PADS_
BANK0_ SWD_ PDE_ ACCESS - PADS_
BANK0_ SWD_ PDE_ BITS - PADS_
BANK0_ SWD_ PDE_ LSB - PADS_
BANK0_ SWD_ PDE_ MSB - PADS_
BANK0_ SWD_ PDE_ RESET - PADS_
BANK0_ SWD_ PUE_ ACCESS - PADS_
BANK0_ SWD_ PUE_ BITS - PADS_
BANK0_ SWD_ PUE_ LSB - PADS_
BANK0_ SWD_ PUE_ MSB - PADS_
BANK0_ SWD_ PUE_ RESET - PADS_
BANK0_ SWD_ RESET - PADS_
BANK0_ SWD_ SCHMITT_ ACCESS - PADS_
BANK0_ SWD_ SCHMITT_ BITS - PADS_
BANK0_ SWD_ SCHMITT_ LSB - PADS_
BANK0_ SWD_ SCHMITT_ MSB - PADS_
BANK0_ SWD_ SCHMITT_ RESET - PADS_
BANK0_ SWD_ SLEWFAST_ ACCESS - PADS_
BANK0_ SWD_ SLEWFAST_ BITS - PADS_
BANK0_ SWD_ SLEWFAST_ LSB - PADS_
BANK0_ SWD_ SLEWFAST_ MSB - PADS_
BANK0_ SWD_ SLEWFAST_ RESET - PADS_
BANK0_ VOLTAGE_ SELECT_ ACCESS - PADS_
BANK0_ VOLTAGE_ SELECT_ BITS - PADS_
BANK0_ VOLTAGE_ SELECT_ LSB - PADS_
BANK0_ VOLTAGE_ SELECT_ MSB - PADS_
BANK0_ VOLTAGE_ SELECT_ OFFSET - PADS_
BANK0_ VOLTAGE_ SELECT_ RESET - PADS_
BANK0_ VOLTAGE_ SELECT_ VALUE_ 1V8 - PADS_
BANK0_ VOLTAGE_ SELECT_ VALUE_ 3V3 - PADS_
QSPI_ BASE - PARAM_
ASSERTIONS_ DISABLE_ ALL - PARAM_
ASSERTIONS_ ENABLED_ GPIO - PARAM_
ASSERTIONS_ ENABLED_ TIME - PARAM_
ASSERTIONS_ ENABLED_ TIMER - PARAM_
ASSERTIONS_ ENABLED_ UART - PARAM_
ASSERTIONS_ ENABLE_ ALL - PICO_
DEBUG_ PIN_ BASE - PICO_
DEBUG_ PIN_ COUNT - PICO_
DEFAULT_ LED_ PIN - PICO_
DEFAULT_ UART - PICO_
DEFAULT_ UART_ BAUD_ RATE - PICO_
DEFAULT_ UART_ RX_ PIN - PICO_
DEFAULT_ UART_ TX_ PIN - PICO_
DOUBLE_ SUPPORT_ ROM_ V1 - PICO_
ERROR_ GENERIC - PICO_
ERROR_ NONE - PICO_
ERROR_ NO_ DATA - PICO_
ERROR_ TIMEOUT - PICO_
FLASH_ SIZE_ BYTES - PICO_
FLASH_ SPI_ CLKDIV - PICO_
FLOAT_ SUPPORT_ ROM_ V1 - PICO_
HEAP_ SIZE - PICO_
NO_ RAM_ VECTOR_ TABLE - PICO_OK
- PICO_
SDK_ VERSION_ MAJOR - PICO_
SDK_ VERSION_ MINOR - PICO_
SDK_ VERSION_ REVISION - PICO_
SDK_ VERSION_ STRING - PICO_
SMPS_ MODE_ PIN - PICO_
STACK_ SIZE - PICO_
STDIO_ DEFAULT_ CRLF - PICO_
STDIO_ ENABLE_ CRLF_ SUPPORT - PICO_
STDIO_ STACK_ BUFFER_ SIZE - PICO_
STDOUT_ MUTEX - PICO_
TIME_ DEFAULT_ ALARM_ POOL_ DISABLED - PICO_
TIME_ DEFAULT_ ALARM_ POOL_ HARDWARE_ ALARM_ NUM - PICO_
TIME_ DEFAULT_ ALARM_ POOL_ MAX_ TIMERS - PICO_
TIME_ SLEEP_ OVERHEAD_ ADJUST_ US - PICO_
UART_ DEFAULT_ CRLF - PICO_
UART_ ENABLE_ CRLF_ SUPPORT - PIO0_
BASE - PIO1_
BASE - PIO_
INSTRUCTION_ COUNT - PLL_
SYS_ BASE - PLL_
USB_ BASE - PPB_
BASE - PSM_
BASE - PWM_
BASE - REG_
ALIAS_ CLR_ BITS - REG_
ALIAS_ RW_ BITS - REG_
ALIAS_ SET_ BITS - REG_
ALIAS_ XOR_ BITS - RESETS_
BASE - ROM_
BASE - ROSC_
BASE - RSIZE_
MAX - RTC_
BASE - SIG_
ATOMIC_ MAX - SIG_
ATOMIC_ MIN - SIO_
BASE - SIO_
CPUID_ ACCESS - SIO_
CPUID_ BITS - SIO_
CPUID_ LSB - SIO_
CPUID_ MSB - SIO_
CPUID_ OFFSET - SIO_
CPUID_ RESET - SIO_
DIV_ CSR_ BITS - SIO_
DIV_ CSR_ DIRTY_ ACCESS - SIO_
DIV_ CSR_ DIRTY_ BITS - SIO_
DIV_ CSR_ DIRTY_ LSB - SIO_
DIV_ CSR_ DIRTY_ MSB - SIO_
DIV_ CSR_ DIRTY_ RESET - SIO_
DIV_ CSR_ OFFSET - SIO_
DIV_ CSR_ READY_ ACCESS - SIO_
DIV_ CSR_ READY_ BITS - SIO_
DIV_ CSR_ READY_ LSB - SIO_
DIV_ CSR_ READY_ MSB - SIO_
DIV_ CSR_ READY_ RESET - SIO_
DIV_ CSR_ RESET - SIO_
DIV_ QUOTIENT_ ACCESS - SIO_
DIV_ QUOTIENT_ BITS - SIO_
DIV_ QUOTIENT_ LSB - SIO_
DIV_ QUOTIENT_ MSB - SIO_
DIV_ QUOTIENT_ OFFSET - SIO_
DIV_ QUOTIENT_ RESET - SIO_
DIV_ REMAINDER_ ACCESS - SIO_
DIV_ REMAINDER_ BITS - SIO_
DIV_ REMAINDER_ LSB - SIO_
DIV_ REMAINDER_ MSB - SIO_
DIV_ REMAINDER_ OFFSET - SIO_
DIV_ REMAINDER_ RESET - SIO_
DIV_ SDIVIDEND_ ACCESS - SIO_
DIV_ SDIVIDEND_ BITS - SIO_
DIV_ SDIVIDEND_ LSB - SIO_
DIV_ SDIVIDEND_ MSB - SIO_
DIV_ SDIVIDEND_ OFFSET - SIO_
DIV_ SDIVIDEND_ RESET - SIO_
DIV_ SDIVISOR_ ACCESS - SIO_
DIV_ SDIVISOR_ BITS - SIO_
DIV_ SDIVISOR_ LSB - SIO_
DIV_ SDIVISOR_ MSB - SIO_
DIV_ SDIVISOR_ OFFSET - SIO_
DIV_ SDIVISOR_ RESET - SIO_
DIV_ UDIVIDEND_ ACCESS - SIO_
DIV_ UDIVIDEND_ BITS - SIO_
DIV_ UDIVIDEND_ LSB - SIO_
DIV_ UDIVIDEND_ MSB - SIO_
DIV_ UDIVIDEND_ OFFSET - SIO_
DIV_ UDIVIDEND_ RESET - SIO_
DIV_ UDIVISOR_ ACCESS - SIO_
DIV_ UDIVISOR_ BITS - SIO_
DIV_ UDIVISOR_ LSB - SIO_
DIV_ UDIVISOR_ MSB - SIO_
DIV_ UDIVISOR_ OFFSET - SIO_
DIV_ UDIVISOR_ RESET - SIO_
FIFO_ RD_ ACCESS - SIO_
FIFO_ RD_ BITS - SIO_
FIFO_ RD_ LSB - SIO_
FIFO_ RD_ MSB - SIO_
FIFO_ RD_ OFFSET - SIO_
FIFO_ RD_ RESET - SIO_
FIFO_ ST_ BITS - SIO_
FIFO_ ST_ OFFSET - SIO_
FIFO_ ST_ RDY_ ACCESS - SIO_
FIFO_ ST_ RDY_ BITS - SIO_
FIFO_ ST_ RDY_ LSB - SIO_
FIFO_ ST_ RDY_ MSB - SIO_
FIFO_ ST_ RDY_ RESET - SIO_
FIFO_ ST_ RESET - SIO_
FIFO_ ST_ ROE_ ACCESS - SIO_
FIFO_ ST_ ROE_ BITS - SIO_
FIFO_ ST_ ROE_ LSB - SIO_
FIFO_ ST_ ROE_ MSB - SIO_
FIFO_ ST_ ROE_ RESET - SIO_
FIFO_ ST_ VLD_ ACCESS - SIO_
FIFO_ ST_ VLD_ BITS - SIO_
FIFO_ ST_ VLD_ LSB - SIO_
FIFO_ ST_ VLD_ MSB - SIO_
FIFO_ ST_ VLD_ RESET - SIO_
FIFO_ ST_ WOF_ ACCESS - SIO_
FIFO_ ST_ WOF_ BITS - SIO_
FIFO_ ST_ WOF_ LSB - SIO_
FIFO_ ST_ WOF_ MSB - SIO_
FIFO_ ST_ WOF_ RESET - SIO_
FIFO_ WR_ ACCESS - SIO_
FIFO_ WR_ BITS - SIO_
FIFO_ WR_ LSB - SIO_
FIFO_ WR_ MSB - SIO_
FIFO_ WR_ OFFSET - SIO_
FIFO_ WR_ RESET - SIO_
GPIO_ HI_ IN_ ACCESS - SIO_
GPIO_ HI_ IN_ BITS - SIO_
GPIO_ HI_ IN_ LSB - SIO_
GPIO_ HI_ IN_ MSB - SIO_
GPIO_ HI_ IN_ OFFSET - SIO_
GPIO_ HI_ IN_ RESET - SIO_
GPIO_ HI_ OE_ ACCESS - SIO_
GPIO_ HI_ OE_ BITS - SIO_
GPIO_ HI_ OE_ CLR_ ACCESS - SIO_
GPIO_ HI_ OE_ CLR_ BITS - SIO_
GPIO_ HI_ OE_ CLR_ LSB - SIO_
GPIO_ HI_ OE_ CLR_ MSB - SIO_
GPIO_ HI_ OE_ CLR_ OFFSET - SIO_
GPIO_ HI_ OE_ CLR_ RESET - SIO_
GPIO_ HI_ OE_ LSB - SIO_
GPIO_ HI_ OE_ MSB - SIO_
GPIO_ HI_ OE_ OFFSET - SIO_
GPIO_ HI_ OE_ RESET - SIO_
GPIO_ HI_ OE_ SET_ ACCESS - SIO_
GPIO_ HI_ OE_ SET_ BITS - SIO_
GPIO_ HI_ OE_ SET_ LSB - SIO_
GPIO_ HI_ OE_ SET_ MSB - SIO_
GPIO_ HI_ OE_ SET_ OFFSET - SIO_
GPIO_ HI_ OE_ SET_ RESET - SIO_
GPIO_ HI_ OE_ XOR_ ACCESS - SIO_
GPIO_ HI_ OE_ XOR_ BITS - SIO_
GPIO_ HI_ OE_ XOR_ LSB - SIO_
GPIO_ HI_ OE_ XOR_ MSB - SIO_
GPIO_ HI_ OE_ XOR_ OFFSET - SIO_
GPIO_ HI_ OE_ XOR_ RESET - SIO_
GPIO_ HI_ OUT_ ACCESS - SIO_
GPIO_ HI_ OUT_ BITS - SIO_
GPIO_ HI_ OUT_ CLR_ ACCESS - SIO_
GPIO_ HI_ OUT_ CLR_ BITS - SIO_
GPIO_ HI_ OUT_ CLR_ LSB - SIO_
GPIO_ HI_ OUT_ CLR_ MSB - SIO_
GPIO_ HI_ OUT_ CLR_ OFFSET - SIO_
GPIO_ HI_ OUT_ CLR_ RESET - SIO_
GPIO_ HI_ OUT_ LSB - SIO_
GPIO_ HI_ OUT_ MSB - SIO_
GPIO_ HI_ OUT_ OFFSET - SIO_
GPIO_ HI_ OUT_ RESET - SIO_
GPIO_ HI_ OUT_ SET_ ACCESS - SIO_
GPIO_ HI_ OUT_ SET_ BITS - SIO_
GPIO_ HI_ OUT_ SET_ LSB - SIO_
GPIO_ HI_ OUT_ SET_ MSB - SIO_
GPIO_ HI_ OUT_ SET_ OFFSET - SIO_
GPIO_ HI_ OUT_ SET_ RESET - SIO_
GPIO_ HI_ OUT_ XOR_ ACCESS - SIO_
GPIO_ HI_ OUT_ XOR_ BITS - SIO_
GPIO_ HI_ OUT_ XOR_ LSB - SIO_
GPIO_ HI_ OUT_ XOR_ MSB - SIO_
GPIO_ HI_ OUT_ XOR_ OFFSET - SIO_
GPIO_ HI_ OUT_ XOR_ RESET - SIO_
GPIO_ IN_ ACCESS - SIO_
GPIO_ IN_ BITS - SIO_
GPIO_ IN_ LSB - SIO_
GPIO_ IN_ MSB - SIO_
GPIO_ IN_ OFFSET - SIO_
GPIO_ IN_ RESET - SIO_
GPIO_ OE_ ACCESS - SIO_
GPIO_ OE_ BITS - SIO_
GPIO_ OE_ CLR_ ACCESS - SIO_
GPIO_ OE_ CLR_ BITS - SIO_
GPIO_ OE_ CLR_ LSB - SIO_
GPIO_ OE_ CLR_ MSB - SIO_
GPIO_ OE_ CLR_ OFFSET - SIO_
GPIO_ OE_ CLR_ RESET - SIO_
GPIO_ OE_ LSB - SIO_
GPIO_ OE_ MSB - SIO_
GPIO_ OE_ OFFSET - SIO_
GPIO_ OE_ RESET - SIO_
GPIO_ OE_ SET_ ACCESS - SIO_
GPIO_ OE_ SET_ BITS - SIO_
GPIO_ OE_ SET_ LSB - SIO_
GPIO_ OE_ SET_ MSB - SIO_
GPIO_ OE_ SET_ OFFSET - SIO_
GPIO_ OE_ SET_ RESET - SIO_
GPIO_ OE_ XOR_ ACCESS - SIO_
GPIO_ OE_ XOR_ BITS - SIO_
GPIO_ OE_ XOR_ LSB - SIO_
GPIO_ OE_ XOR_ MSB - SIO_
GPIO_ OE_ XOR_ OFFSET - SIO_
GPIO_ OE_ XOR_ RESET - SIO_
GPIO_ OUT_ ACCESS - SIO_
GPIO_ OUT_ BITS - SIO_
GPIO_ OUT_ CLR_ ACCESS - SIO_
GPIO_ OUT_ CLR_ BITS - SIO_
GPIO_ OUT_ CLR_ LSB - SIO_
GPIO_ OUT_ CLR_ MSB - SIO_
GPIO_ OUT_ CLR_ OFFSET - SIO_
GPIO_ OUT_ CLR_ RESET - SIO_
GPIO_ OUT_ LSB - SIO_
GPIO_ OUT_ MSB - SIO_
GPIO_ OUT_ OFFSET - SIO_
GPIO_ OUT_ RESET - SIO_
GPIO_ OUT_ SET_ ACCESS - SIO_
GPIO_ OUT_ SET_ BITS - SIO_
GPIO_ OUT_ SET_ LSB - SIO_
GPIO_ OUT_ SET_ MSB - SIO_
GPIO_ OUT_ SET_ OFFSET - SIO_
GPIO_ OUT_ SET_ RESET - SIO_
GPIO_ OUT_ XOR_ ACCESS - SIO_
GPIO_ OUT_ XOR_ BITS - SIO_
GPIO_ OUT_ XOR_ LSB - SIO_
GPIO_ OUT_ XOR_ MSB - SIO_
GPIO_ OUT_ XOR_ OFFSET - SIO_
GPIO_ OUT_ XOR_ RESET - SIO_
INTER P0_ ACCU M0_ ACCESS - SIO_
INTER P0_ ACCU M0_ ADD_ ACCESS - SIO_
INTER P0_ ACCU M0_ ADD_ BITS - SIO_
INTER P0_ ACCU M0_ ADD_ LSB - SIO_
INTER P0_ ACCU M0_ ADD_ MSB - SIO_
INTER P0_ ACCU M0_ ADD_ OFFSET - SIO_
INTER P0_ ACCU M0_ ADD_ RESET - SIO_
INTER P0_ ACCU M0_ BITS - SIO_
INTER P0_ ACCU M0_ LSB - SIO_
INTER P0_ ACCU M0_ MSB - SIO_
INTER P0_ ACCU M0_ OFFSET - SIO_
INTER P0_ ACCU M0_ RESET - SIO_
INTER P0_ ACCU M1_ ACCESS - SIO_
INTER P0_ ACCU M1_ ADD_ ACCESS - SIO_
INTER P0_ ACCU M1_ ADD_ BITS - SIO_
INTER P0_ ACCU M1_ ADD_ LSB - SIO_
INTER P0_ ACCU M1_ ADD_ MSB - SIO_
INTER P0_ ACCU M1_ ADD_ OFFSET - SIO_
INTER P0_ ACCU M1_ ADD_ RESET - SIO_
INTER P0_ ACCU M1_ BITS - SIO_
INTER P0_ ACCU M1_ LSB - SIO_
INTER P0_ ACCU M1_ MSB - SIO_
INTER P0_ ACCU M1_ OFFSET - SIO_
INTER P0_ ACCU M1_ RESET - SIO_
INTER P0_ BASE0_ ACCESS - SIO_
INTER P0_ BASE0_ BITS - SIO_
INTER P0_ BASE0_ LSB - SIO_
INTER P0_ BASE0_ MSB - SIO_
INTER P0_ BASE0_ OFFSET - SIO_
INTER P0_ BASE0_ RESET - SIO_
INTER P0_ BASE1_ ACCESS - SIO_
INTER P0_ BASE1_ BITS - SIO_
INTER P0_ BASE1_ LSB - SIO_
INTER P0_ BASE1_ MSB - SIO_
INTER P0_ BASE1_ OFFSET - SIO_
INTER P0_ BASE1_ RESET - SIO_
INTER P0_ BASE2_ ACCESS - SIO_
INTER P0_ BASE2_ BITS - SIO_
INTER P0_ BASE2_ LSB - SIO_
INTER P0_ BASE2_ MSB - SIO_
INTER P0_ BASE2_ OFFSET - SIO_
INTER P0_ BASE2_ RESET - SIO_
INTER P0_ BASE_ 1AND0_ ACCESS - SIO_
INTER P0_ BASE_ 1AND0_ BITS - SIO_
INTER P0_ BASE_ 1AND0_ LSB - SIO_
INTER P0_ BASE_ 1AND0_ MSB - SIO_
INTER P0_ BASE_ 1AND0_ OFFSET - SIO_
INTER P0_ BASE_ 1AND0_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ ADD_ RAW_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ ADD_ RAW_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ ADD_ RAW_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ ADD_ RAW_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ ADD_ RAW_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ BLEND_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ BLEND_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ BLEND_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ BLEND_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ BLEND_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ INPUT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ INPUT_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ INPUT_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ INPUT_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ INPUT_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ RESULT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ RESULT_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ RESULT_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ RESULT_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ CROSS_ RESULT_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ FORCE_ MSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ FORCE_ MSB_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ FORCE_ MSB_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ FORCE_ MSB_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ FORCE_ MSB_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ LSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ LSB_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ LSB_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ LSB_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ LSB_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ MSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ MSB_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ MSB_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ MSB_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ MASK_ MSB_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ OFFSET - SIO_
INTER P0_ CTRL_ LANE0_ OVER F0_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ OVER F0_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ OVER F0_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ OVER F0_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ OVER F0_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ OVER F1_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ OVER F1_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ OVER F1_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ OVER F1_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ OVER F1_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ OVERF_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ OVERF_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ OVERF_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ OVERF_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ OVERF_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ SHIFT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ SHIFT_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ SHIFT_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ SHIFT_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ SHIFT_ RESET - SIO_
INTER P0_ CTRL_ LANE0_ SIGNED_ ACCESS - SIO_
INTER P0_ CTRL_ LANE0_ SIGNED_ BITS - SIO_
INTER P0_ CTRL_ LANE0_ SIGNED_ LSB - SIO_
INTER P0_ CTRL_ LANE0_ SIGNED_ MSB - SIO_
INTER P0_ CTRL_ LANE0_ SIGNED_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ ADD_ RAW_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ ADD_ RAW_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ ADD_ RAW_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ ADD_ RAW_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ ADD_ RAW_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ INPUT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ INPUT_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ INPUT_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ INPUT_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ INPUT_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ RESULT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ RESULT_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ RESULT_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ RESULT_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ CROSS_ RESULT_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ FORCE_ MSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ FORCE_ MSB_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ FORCE_ MSB_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ FORCE_ MSB_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ FORCE_ MSB_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ LSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ LSB_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ LSB_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ LSB_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ LSB_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ MSB_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ MSB_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ MSB_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ MSB_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ MASK_ MSB_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ OFFSET - SIO_
INTER P0_ CTRL_ LANE1_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ SHIFT_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ SHIFT_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ SHIFT_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ SHIFT_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ SHIFT_ RESET - SIO_
INTER P0_ CTRL_ LANE1_ SIGNED_ ACCESS - SIO_
INTER P0_ CTRL_ LANE1_ SIGNED_ BITS - SIO_
INTER P0_ CTRL_ LANE1_ SIGNED_ LSB - SIO_
INTER P0_ CTRL_ LANE1_ SIGNED_ MSB - SIO_
INTER P0_ CTRL_ LANE1_ SIGNED_ RESET - SIO_
INTER P0_ PEEK_ FULL_ ACCESS - SIO_
INTER P0_ PEEK_ FULL_ BITS - SIO_
INTER P0_ PEEK_ FULL_ LSB - SIO_
INTER P0_ PEEK_ FULL_ MSB - SIO_
INTER P0_ PEEK_ FULL_ OFFSET - SIO_
INTER P0_ PEEK_ FULL_ RESET - SIO_
INTER P0_ PEEK_ LANE0_ ACCESS - SIO_
INTER P0_ PEEK_ LANE0_ BITS - SIO_
INTER P0_ PEEK_ LANE0_ LSB - SIO_
INTER P0_ PEEK_ LANE0_ MSB - SIO_
INTER P0_ PEEK_ LANE0_ OFFSET - SIO_
INTER P0_ PEEK_ LANE0_ RESET - SIO_
INTER P0_ PEEK_ LANE1_ ACCESS - SIO_
INTER P0_ PEEK_ LANE1_ BITS - SIO_
INTER P0_ PEEK_ LANE1_ LSB - SIO_
INTER P0_ PEEK_ LANE1_ MSB - SIO_
INTER P0_ PEEK_ LANE1_ OFFSET - SIO_
INTER P0_ PEEK_ LANE1_ RESET - SIO_
INTER P0_ POP_ FULL_ ACCESS - SIO_
INTER P0_ POP_ FULL_ BITS - SIO_
INTER P0_ POP_ FULL_ LSB - SIO_
INTER P0_ POP_ FULL_ MSB - SIO_
INTER P0_ POP_ FULL_ OFFSET - SIO_
INTER P0_ POP_ FULL_ RESET - SIO_
INTER P0_ POP_ LANE0_ ACCESS - SIO_
INTER P0_ POP_ LANE0_ BITS - SIO_
INTER P0_ POP_ LANE0_ LSB - SIO_
INTER P0_ POP_ LANE0_ MSB - SIO_
INTER P0_ POP_ LANE0_ OFFSET - SIO_
INTER P0_ POP_ LANE0_ RESET - SIO_
INTER P0_ POP_ LANE1_ ACCESS - SIO_
INTER P0_ POP_ LANE1_ BITS - SIO_
INTER P0_ POP_ LANE1_ LSB - SIO_
INTER P0_ POP_ LANE1_ MSB - SIO_
INTER P0_ POP_ LANE1_ OFFSET - SIO_
INTER P0_ POP_ LANE1_ RESET - SIO_
INTER P1_ ACCU M0_ ACCESS - SIO_
INTER P1_ ACCU M0_ ADD_ ACCESS - SIO_
INTER P1_ ACCU M0_ ADD_ BITS - SIO_
INTER P1_ ACCU M0_ ADD_ LSB - SIO_
INTER P1_ ACCU M0_ ADD_ MSB - SIO_
INTER P1_ ACCU M0_ ADD_ OFFSET - SIO_
INTER P1_ ACCU M0_ ADD_ RESET - SIO_
INTER P1_ ACCU M0_ BITS - SIO_
INTER P1_ ACCU M0_ LSB - SIO_
INTER P1_ ACCU M0_ MSB - SIO_
INTER P1_ ACCU M0_ OFFSET - SIO_
INTER P1_ ACCU M0_ RESET - SIO_
INTER P1_ ACCU M1_ ACCESS - SIO_
INTER P1_ ACCU M1_ ADD_ ACCESS - SIO_
INTER P1_ ACCU M1_ ADD_ BITS - SIO_
INTER P1_ ACCU M1_ ADD_ LSB - SIO_
INTER P1_ ACCU M1_ ADD_ MSB - SIO_
INTER P1_ ACCU M1_ ADD_ OFFSET - SIO_
INTER P1_ ACCU M1_ ADD_ RESET - SIO_
INTER P1_ ACCU M1_ BITS - SIO_
INTER P1_ ACCU M1_ LSB - SIO_
INTER P1_ ACCU M1_ MSB - SIO_
INTER P1_ ACCU M1_ OFFSET - SIO_
INTER P1_ ACCU M1_ RESET - SIO_
INTER P1_ BASE0_ ACCESS - SIO_
INTER P1_ BASE0_ BITS - SIO_
INTER P1_ BASE0_ LSB - SIO_
INTER P1_ BASE0_ MSB - SIO_
INTER P1_ BASE0_ OFFSET - SIO_
INTER P1_ BASE0_ RESET - SIO_
INTER P1_ BASE1_ ACCESS - SIO_
INTER P1_ BASE1_ BITS - SIO_
INTER P1_ BASE1_ LSB - SIO_
INTER P1_ BASE1_ MSB - SIO_
INTER P1_ BASE1_ OFFSET - SIO_
INTER P1_ BASE1_ RESET - SIO_
INTER P1_ BASE2_ ACCESS - SIO_
INTER P1_ BASE2_ BITS - SIO_
INTER P1_ BASE2_ LSB - SIO_
INTER P1_ BASE2_ MSB - SIO_
INTER P1_ BASE2_ OFFSET - SIO_
INTER P1_ BASE2_ RESET - SIO_
INTER P1_ BASE_ 1AND0_ ACCESS - SIO_
INTER P1_ BASE_ 1AND0_ BITS - SIO_
INTER P1_ BASE_ 1AND0_ LSB - SIO_
INTER P1_ BASE_ 1AND0_ MSB - SIO_
INTER P1_ BASE_ 1AND0_ OFFSET - SIO_
INTER P1_ BASE_ 1AND0_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ ADD_ RAW_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ ADD_ RAW_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ ADD_ RAW_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ ADD_ RAW_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ ADD_ RAW_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ CLAMP_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ CLAMP_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ CLAMP_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ CLAMP_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ CLAMP_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ INPUT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ INPUT_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ INPUT_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ INPUT_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ INPUT_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ RESULT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ RESULT_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ RESULT_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ RESULT_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ CROSS_ RESULT_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ FORCE_ MSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ FORCE_ MSB_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ FORCE_ MSB_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ FORCE_ MSB_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ FORCE_ MSB_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ LSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ LSB_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ LSB_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ LSB_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ LSB_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ MSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ MSB_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ MSB_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ MSB_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ MASK_ MSB_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ OFFSET - SIO_
INTER P1_ CTRL_ LANE0_ OVER F0_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ OVER F0_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ OVER F0_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ OVER F0_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ OVER F0_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ OVER F1_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ OVER F1_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ OVER F1_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ OVER F1_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ OVER F1_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ OVERF_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ OVERF_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ OVERF_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ OVERF_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ OVERF_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ SHIFT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ SHIFT_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ SHIFT_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ SHIFT_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ SHIFT_ RESET - SIO_
INTER P1_ CTRL_ LANE0_ SIGNED_ ACCESS - SIO_
INTER P1_ CTRL_ LANE0_ SIGNED_ BITS - SIO_
INTER P1_ CTRL_ LANE0_ SIGNED_ LSB - SIO_
INTER P1_ CTRL_ LANE0_ SIGNED_ MSB - SIO_
INTER P1_ CTRL_ LANE0_ SIGNED_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ ADD_ RAW_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ ADD_ RAW_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ ADD_ RAW_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ ADD_ RAW_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ ADD_ RAW_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ INPUT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ INPUT_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ INPUT_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ INPUT_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ INPUT_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ RESULT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ RESULT_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ RESULT_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ RESULT_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ CROSS_ RESULT_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ FORCE_ MSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ FORCE_ MSB_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ FORCE_ MSB_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ FORCE_ MSB_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ FORCE_ MSB_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ LSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ LSB_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ LSB_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ LSB_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ LSB_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ MSB_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ MSB_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ MSB_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ MSB_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ MASK_ MSB_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ OFFSET - SIO_
INTER P1_ CTRL_ LANE1_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ SHIFT_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ SHIFT_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ SHIFT_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ SHIFT_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ SHIFT_ RESET - SIO_
INTER P1_ CTRL_ LANE1_ SIGNED_ ACCESS - SIO_
INTER P1_ CTRL_ LANE1_ SIGNED_ BITS - SIO_
INTER P1_ CTRL_ LANE1_ SIGNED_ LSB - SIO_
INTER P1_ CTRL_ LANE1_ SIGNED_ MSB - SIO_
INTER P1_ CTRL_ LANE1_ SIGNED_ RESET - SIO_
INTER P1_ PEEK_ FULL_ ACCESS - SIO_
INTER P1_ PEEK_ FULL_ BITS - SIO_
INTER P1_ PEEK_ FULL_ LSB - SIO_
INTER P1_ PEEK_ FULL_ MSB - SIO_
INTER P1_ PEEK_ FULL_ OFFSET - SIO_
INTER P1_ PEEK_ FULL_ RESET - SIO_
INTER P1_ PEEK_ LANE0_ ACCESS - SIO_
INTER P1_ PEEK_ LANE0_ BITS - SIO_
INTER P1_ PEEK_ LANE0_ LSB - SIO_
INTER P1_ PEEK_ LANE0_ MSB - SIO_
INTER P1_ PEEK_ LANE0_ OFFSET - SIO_
INTER P1_ PEEK_ LANE0_ RESET - SIO_
INTER P1_ PEEK_ LANE1_ ACCESS - SIO_
INTER P1_ PEEK_ LANE1_ BITS - SIO_
INTER P1_ PEEK_ LANE1_ LSB - SIO_
INTER P1_ PEEK_ LANE1_ MSB - SIO_
INTER P1_ PEEK_ LANE1_ OFFSET - SIO_
INTER P1_ PEEK_ LANE1_ RESET - SIO_
INTER P1_ POP_ FULL_ ACCESS - SIO_
INTER P1_ POP_ FULL_ BITS - SIO_
INTER P1_ POP_ FULL_ LSB - SIO_
INTER P1_ POP_ FULL_ MSB - SIO_
INTER P1_ POP_ FULL_ OFFSET - SIO_
INTER P1_ POP_ FULL_ RESET - SIO_
INTER P1_ POP_ LANE0_ ACCESS - SIO_
INTER P1_ POP_ LANE0_ BITS - SIO_
INTER P1_ POP_ LANE0_ LSB - SIO_
INTER P1_ POP_ LANE0_ MSB - SIO_
INTER P1_ POP_ LANE0_ OFFSET - SIO_
INTER P1_ POP_ LANE0_ RESET - SIO_
INTER P1_ POP_ LANE1_ ACCESS - SIO_
INTER P1_ POP_ LANE1_ BITS - SIO_
INTER P1_ POP_ LANE1_ LSB - SIO_
INTER P1_ POP_ LANE1_ MSB - SIO_
INTER P1_ POP_ LANE1_ OFFSET - SIO_
INTER P1_ POP_ LANE1_ RESET - SIO_
SPINLOC K0_ ACCESS - SIO_
SPINLOC K0_ BITS - SIO_
SPINLOC K0_ LSB - SIO_
SPINLOC K0_ MSB - SIO_
SPINLOC K0_ OFFSET - SIO_
SPINLOC K0_ RESET - SIO_
SPINLOC K1_ ACCESS - SIO_
SPINLOC K1_ BITS - SIO_
SPINLOC K1_ LSB - SIO_
SPINLOC K1_ MSB - SIO_
SPINLOC K1_ OFFSET - SIO_
SPINLOC K1_ RESET - SIO_
SPINLOC K2_ ACCESS - SIO_
SPINLOC K2_ BITS - SIO_
SPINLOC K2_ LSB - SIO_
SPINLOC K2_ MSB - SIO_
SPINLOC K2_ OFFSET - SIO_
SPINLOC K2_ RESET - SIO_
SPINLOC K3_ ACCESS - SIO_
SPINLOC K3_ BITS - SIO_
SPINLOC K3_ LSB - SIO_
SPINLOC K3_ MSB - SIO_
SPINLOC K3_ OFFSET - SIO_
SPINLOC K3_ RESET - SIO_
SPINLOC K4_ ACCESS - SIO_
SPINLOC K4_ BITS - SIO_
SPINLOC K4_ LSB - SIO_
SPINLOC K4_ MSB - SIO_
SPINLOC K4_ OFFSET - SIO_
SPINLOC K4_ RESET - SIO_
SPINLOC K5_ ACCESS - SIO_
SPINLOC K5_ BITS - SIO_
SPINLOC K5_ LSB - SIO_
SPINLOC K5_ MSB - SIO_
SPINLOC K5_ OFFSET - SIO_
SPINLOC K5_ RESET - SIO_
SPINLOC K6_ ACCESS - SIO_
SPINLOC K6_ BITS - SIO_
SPINLOC K6_ LSB - SIO_
SPINLOC K6_ MSB - SIO_
SPINLOC K6_ OFFSET - SIO_
SPINLOC K6_ RESET - SIO_
SPINLOC K7_ ACCESS - SIO_
SPINLOC K7_ BITS - SIO_
SPINLOC K7_ LSB - SIO_
SPINLOC K7_ MSB - SIO_
SPINLOC K7_ OFFSET - SIO_
SPINLOC K7_ RESET - SIO_
SPINLOC K8_ ACCESS - SIO_
SPINLOC K8_ BITS - SIO_
SPINLOC K8_ LSB - SIO_
SPINLOC K8_ MSB - SIO_
SPINLOC K8_ OFFSET - SIO_
SPINLOC K8_ RESET - SIO_
SPINLOC K9_ ACCESS - SIO_
SPINLOC K9_ BITS - SIO_
SPINLOC K9_ LSB - SIO_
SPINLOC K9_ MSB - SIO_
SPINLOC K9_ OFFSET - SIO_
SPINLOC K9_ RESET - SIO_
SPINLOC K10_ ACCESS - SIO_
SPINLOC K10_ BITS - SIO_
SPINLOC K10_ LSB - SIO_
SPINLOC K10_ MSB - SIO_
SPINLOC K10_ OFFSET - SIO_
SPINLOC K10_ RESET - SIO_
SPINLOC K11_ ACCESS - SIO_
SPINLOC K11_ BITS - SIO_
SPINLOC K11_ LSB - SIO_
SPINLOC K11_ MSB - SIO_
SPINLOC K11_ OFFSET - SIO_
SPINLOC K11_ RESET - SIO_
SPINLOC K12_ ACCESS - SIO_
SPINLOC K12_ BITS - SIO_
SPINLOC K12_ LSB - SIO_
SPINLOC K12_ MSB - SIO_
SPINLOC K12_ OFFSET - SIO_
SPINLOC K12_ RESET - SIO_
SPINLOC K13_ ACCESS - SIO_
SPINLOC K13_ BITS - SIO_
SPINLOC K13_ LSB - SIO_
SPINLOC K13_ MSB - SIO_
SPINLOC K13_ OFFSET - SIO_
SPINLOC K13_ RESET - SIO_
SPINLOC K14_ ACCESS - SIO_
SPINLOC K14_ BITS - SIO_
SPINLOC K14_ LSB - SIO_
SPINLOC K14_ MSB - SIO_
SPINLOC K14_ OFFSET - SIO_
SPINLOC K14_ RESET - SIO_
SPINLOC K15_ ACCESS - SIO_
SPINLOC K15_ BITS - SIO_
SPINLOC K15_ LSB - SIO_
SPINLOC K15_ MSB - SIO_
SPINLOC K15_ OFFSET - SIO_
SPINLOC K15_ RESET - SIO_
SPINLOC K16_ ACCESS - SIO_
SPINLOC K16_ BITS - SIO_
SPINLOC K16_ LSB - SIO_
SPINLOC K16_ MSB - SIO_
SPINLOC K16_ OFFSET - SIO_
SPINLOC K16_ RESET - SIO_
SPINLOC K17_ ACCESS - SIO_
SPINLOC K17_ BITS - SIO_
SPINLOC K17_ LSB - SIO_
SPINLOC K17_ MSB - SIO_
SPINLOC K17_ OFFSET - SIO_
SPINLOC K17_ RESET - SIO_
SPINLOC K18_ ACCESS - SIO_
SPINLOC K18_ BITS - SIO_
SPINLOC K18_ LSB - SIO_
SPINLOC K18_ MSB - SIO_
SPINLOC K18_ OFFSET - SIO_
SPINLOC K18_ RESET - SIO_
SPINLOC K19_ ACCESS - SIO_
SPINLOC K19_ BITS - SIO_
SPINLOC K19_ LSB - SIO_
SPINLOC K19_ MSB - SIO_
SPINLOC K19_ OFFSET - SIO_
SPINLOC K19_ RESET - SIO_
SPINLOC K20_ ACCESS - SIO_
SPINLOC K20_ BITS - SIO_
SPINLOC K20_ LSB - SIO_
SPINLOC K20_ MSB - SIO_
SPINLOC K20_ OFFSET - SIO_
SPINLOC K20_ RESET - SIO_
SPINLOC K21_ ACCESS - SIO_
SPINLOC K21_ BITS - SIO_
SPINLOC K21_ LSB - SIO_
SPINLOC K21_ MSB - SIO_
SPINLOC K21_ OFFSET - SIO_
SPINLOC K21_ RESET - SIO_
SPINLOC K22_ ACCESS - SIO_
SPINLOC K22_ BITS - SIO_
SPINLOC K22_ LSB - SIO_
SPINLOC K22_ MSB - SIO_
SPINLOC K22_ OFFSET - SIO_
SPINLOC K22_ RESET - SIO_
SPINLOC K23_ ACCESS - SIO_
SPINLOC K23_ BITS - SIO_
SPINLOC K23_ LSB - SIO_
SPINLOC K23_ MSB - SIO_
SPINLOC K23_ OFFSET - SIO_
SPINLOC K23_ RESET - SIO_
SPINLOC K24_ ACCESS - SIO_
SPINLOC K24_ BITS - SIO_
SPINLOC K24_ LSB - SIO_
SPINLOC K24_ MSB - SIO_
SPINLOC K24_ OFFSET - SIO_
SPINLOC K24_ RESET - SIO_
SPINLOC K25_ ACCESS - SIO_
SPINLOC K25_ BITS - SIO_
SPINLOC K25_ LSB - SIO_
SPINLOC K25_ MSB - SIO_
SPINLOC K25_ OFFSET - SIO_
SPINLOC K25_ RESET - SIO_
SPINLOC K26_ ACCESS - SIO_
SPINLOC K26_ BITS - SIO_
SPINLOC K26_ LSB - SIO_
SPINLOC K26_ MSB - SIO_
SPINLOC K26_ OFFSET - SIO_
SPINLOC K26_ RESET - SIO_
SPINLOC K27_ ACCESS - SIO_
SPINLOC K27_ BITS - SIO_
SPINLOC K27_ LSB - SIO_
SPINLOC K27_ MSB - SIO_
SPINLOC K27_ OFFSET - SIO_
SPINLOC K27_ RESET - SIO_
SPINLOC K28_ ACCESS - SIO_
SPINLOC K28_ BITS - SIO_
SPINLOC K28_ LSB - SIO_
SPINLOC K28_ MSB - SIO_
SPINLOC K28_ OFFSET - SIO_
SPINLOC K28_ RESET - SIO_
SPINLOC K29_ ACCESS - SIO_
SPINLOC K29_ BITS - SIO_
SPINLOC K29_ LSB - SIO_
SPINLOC K29_ MSB - SIO_
SPINLOC K29_ OFFSET - SIO_
SPINLOC K29_ RESET - SIO_
SPINLOC K30_ ACCESS - SIO_
SPINLOC K30_ BITS - SIO_
SPINLOC K30_ LSB - SIO_
SPINLOC K30_ MSB - SIO_
SPINLOC K30_ OFFSET - SIO_
SPINLOC K30_ RESET - SIO_
SPINLOC K31_ ACCESS - SIO_
SPINLOC K31_ BITS - SIO_
SPINLOC K31_ LSB - SIO_
SPINLOC K31_ MSB - SIO_
SPINLOC K31_ OFFSET - SIO_
SPINLOC K31_ RESET - SIO_
SPINLOCK_ ST_ ACCESS - SIO_
SPINLOCK_ ST_ BITS - SIO_
SPINLOCK_ ST_ LSB - SIO_
SPINLOCK_ ST_ MSB - SIO_
SPINLOCK_ ST_ OFFSET - SIO_
SPINLOCK_ ST_ RESET - SIZE_
MAX - SPI0_
BASE - SPI1_
BASE - SRAM0_
BASE - SRAM1_
BASE - SRAM2_
BASE - SRAM3_
BASE - SRAM4_
BASE - SRAM5_
BASE - SRAM_
BASE - SRAM_
END - SRAM_
STRIPED_ BASE - SRAM_
STRIPED_ END - SYSCFG_
BASE - SYSINFO_
BASE - TBMAN_
BASE - TIMER_
ALAR M0_ ACCESS - TIMER_
ALAR M0_ BITS - TIMER_
ALAR M0_ LSB - TIMER_
ALAR M0_ MSB - TIMER_
ALAR M0_ OFFSET - TIMER_
ALAR M0_ RESET - TIMER_
ALAR M1_ ACCESS - TIMER_
ALAR M1_ BITS - TIMER_
ALAR M1_ LSB - TIMER_
ALAR M1_ MSB - TIMER_
ALAR M1_ OFFSET - TIMER_
ALAR M1_ RESET - TIMER_
ALAR M2_ ACCESS - TIMER_
ALAR M2_ BITS - TIMER_
ALAR M2_ LSB - TIMER_
ALAR M2_ MSB - TIMER_
ALAR M2_ OFFSET - TIMER_
ALAR M2_ RESET - TIMER_
ALAR M3_ ACCESS - TIMER_
ALAR M3_ BITS - TIMER_
ALAR M3_ LSB - TIMER_
ALAR M3_ MSB - TIMER_
ALAR M3_ OFFSET - TIMER_
ALAR M3_ RESET - TIMER_
ARMED_ ACCESS - TIMER_
ARMED_ BITS - TIMER_
ARMED_ LSB - TIMER_
ARMED_ MSB - TIMER_
ARMED_ OFFSET - TIMER_
ARMED_ RESET - TIMER_
BASE - TIMER_
DBGPAUSE_ BITS - TIMER_
DBGPAUSE_ DBG0_ ACCESS - TIMER_
DBGPAUSE_ DBG0_ BITS - TIMER_
DBGPAUSE_ DBG0_ LSB - TIMER_
DBGPAUSE_ DBG0_ MSB - TIMER_
DBGPAUSE_ DBG0_ RESET - TIMER_
DBGPAUSE_ DBG1_ ACCESS - TIMER_
DBGPAUSE_ DBG1_ BITS - TIMER_
DBGPAUSE_ DBG1_ LSB - TIMER_
DBGPAUSE_ DBG1_ MSB - TIMER_
DBGPAUSE_ DBG1_ RESET - TIMER_
DBGPAUSE_ OFFSET - TIMER_
DBGPAUSE_ RESET - TIMER_
INTE_ ALARM_ 0_ ACCESS - TIMER_
INTE_ ALARM_ 0_ BITS - TIMER_
INTE_ ALARM_ 0_ LSB - TIMER_
INTE_ ALARM_ 0_ MSB - TIMER_
INTE_ ALARM_ 0_ RESET - TIMER_
INTE_ ALARM_ 1_ ACCESS - TIMER_
INTE_ ALARM_ 1_ BITS - TIMER_
INTE_ ALARM_ 1_ LSB - TIMER_
INTE_ ALARM_ 1_ MSB - TIMER_
INTE_ ALARM_ 1_ RESET - TIMER_
INTE_ ALARM_ 2_ ACCESS - TIMER_
INTE_ ALARM_ 2_ BITS - TIMER_
INTE_ ALARM_ 2_ LSB - TIMER_
INTE_ ALARM_ 2_ MSB - TIMER_
INTE_ ALARM_ 2_ RESET - TIMER_
INTE_ ALARM_ 3_ ACCESS - TIMER_
INTE_ ALARM_ 3_ BITS - TIMER_
INTE_ ALARM_ 3_ LSB - TIMER_
INTE_ ALARM_ 3_ MSB - TIMER_
INTE_ ALARM_ 3_ RESET - TIMER_
INTE_ BITS - TIMER_
INTE_ OFFSET - TIMER_
INTE_ RESET - TIMER_
INTF_ ALARM_ 0_ ACCESS - TIMER_
INTF_ ALARM_ 0_ BITS - TIMER_
INTF_ ALARM_ 0_ LSB - TIMER_
INTF_ ALARM_ 0_ MSB - TIMER_
INTF_ ALARM_ 0_ RESET - TIMER_
INTF_ ALARM_ 1_ ACCESS - TIMER_
INTF_ ALARM_ 1_ BITS - TIMER_
INTF_ ALARM_ 1_ LSB - TIMER_
INTF_ ALARM_ 1_ MSB - TIMER_
INTF_ ALARM_ 1_ RESET - TIMER_
INTF_ ALARM_ 2_ ACCESS - TIMER_
INTF_ ALARM_ 2_ BITS - TIMER_
INTF_ ALARM_ 2_ LSB - TIMER_
INTF_ ALARM_ 2_ MSB - TIMER_
INTF_ ALARM_ 2_ RESET - TIMER_
INTF_ ALARM_ 3_ ACCESS - TIMER_
INTF_ ALARM_ 3_ BITS - TIMER_
INTF_ ALARM_ 3_ LSB - TIMER_
INTF_ ALARM_ 3_ MSB - TIMER_
INTF_ ALARM_ 3_ RESET - TIMER_
INTF_ BITS - TIMER_
INTF_ OFFSET - TIMER_
INTF_ RESET - TIMER_
INTR_ ALARM_ 0_ ACCESS - TIMER_
INTR_ ALARM_ 0_ BITS - TIMER_
INTR_ ALARM_ 0_ LSB - TIMER_
INTR_ ALARM_ 0_ MSB - TIMER_
INTR_ ALARM_ 0_ RESET - TIMER_
INTR_ ALARM_ 1_ ACCESS - TIMER_
INTR_ ALARM_ 1_ BITS - TIMER_
INTR_ ALARM_ 1_ LSB - TIMER_
INTR_ ALARM_ 1_ MSB - TIMER_
INTR_ ALARM_ 1_ RESET - TIMER_
INTR_ ALARM_ 2_ ACCESS - TIMER_
INTR_ ALARM_ 2_ BITS - TIMER_
INTR_ ALARM_ 2_ LSB - TIMER_
INTR_ ALARM_ 2_ MSB - TIMER_
INTR_ ALARM_ 2_ RESET - TIMER_
INTR_ ALARM_ 3_ ACCESS - TIMER_
INTR_ ALARM_ 3_ BITS - TIMER_
INTR_ ALARM_ 3_ LSB - TIMER_
INTR_ ALARM_ 3_ MSB - TIMER_
INTR_ ALARM_ 3_ RESET - TIMER_
INTR_ BITS - TIMER_
INTR_ OFFSET - TIMER_
INTR_ RESET - TIMER_
INTS_ ALARM_ 0_ ACCESS - TIMER_
INTS_ ALARM_ 0_ BITS - TIMER_
INTS_ ALARM_ 0_ LSB - TIMER_
INTS_ ALARM_ 0_ MSB - TIMER_
INTS_ ALARM_ 0_ RESET - TIMER_
INTS_ ALARM_ 1_ ACCESS - TIMER_
INTS_ ALARM_ 1_ BITS - TIMER_
INTS_ ALARM_ 1_ LSB - TIMER_
INTS_ ALARM_ 1_ MSB - TIMER_
INTS_ ALARM_ 1_ RESET - TIMER_
INTS_ ALARM_ 2_ ACCESS - TIMER_
INTS_ ALARM_ 2_ BITS - TIMER_
INTS_ ALARM_ 2_ LSB - TIMER_
INTS_ ALARM_ 2_ MSB - TIMER_
INTS_ ALARM_ 2_ RESET - TIMER_
INTS_ ALARM_ 3_ ACCESS - TIMER_
INTS_ ALARM_ 3_ BITS - TIMER_
INTS_ ALARM_ 3_ LSB - TIMER_
INTS_ ALARM_ 3_ MSB - TIMER_
INTS_ ALARM_ 3_ RESET - TIMER_
INTS_ BITS - TIMER_
INTS_ OFFSET - TIMER_
INTS_ RESET - TIMER_
PAUSE_ ACCESS - TIMER_
PAUSE_ BITS - TIMER_
PAUSE_ LSB - TIMER_
PAUSE_ MSB - TIMER_
PAUSE_ OFFSET - TIMER_
PAUSE_ RESET - TIMER_
TIMEHR_ ACCESS - TIMER_
TIMEHR_ BITS - TIMER_
TIMEHR_ LSB - TIMER_
TIMEHR_ MSB - TIMER_
TIMEHR_ OFFSET - TIMER_
TIMEHR_ RESET - TIMER_
TIMEHW_ ACCESS - TIMER_
TIMEHW_ BITS - TIMER_
TIMEHW_ LSB - TIMER_
TIMEHW_ MSB - TIMER_
TIMEHW_ OFFSET - TIMER_
TIMEHW_ RESET - TIMER_
TIMELR_ ACCESS - TIMER_
TIMELR_ BITS - TIMER_
TIMELR_ LSB - TIMER_
TIMELR_ MSB - TIMER_
TIMELR_ OFFSET - TIMER_
TIMELR_ RESET - TIMER_
TIMELW_ ACCESS - TIMER_
TIMELW_ BITS - TIMER_
TIMELW_ LSB - TIMER_
TIMELW_ MSB - TIMER_
TIMELW_ OFFSET - TIMER_
TIMELW_ RESET - TIMER_
TIMERAWH_ ACCESS - TIMER_
TIMERAWH_ BITS - TIMER_
TIMERAWH_ LSB - TIMER_
TIMERAWH_ MSB - TIMER_
TIMERAWH_ OFFSET - TIMER_
TIMERAWH_ RESET - TIMER_
TIMERAWL_ ACCESS - TIMER_
TIMERAWL_ BITS - TIMER_
TIMERAWL_ LSB - TIMER_
TIMERAWL_ MSB - TIMER_
TIMERAWL_ OFFSET - TIMER_
TIMERAWL_ RESET - UART0_
BASE - UART1_
BASE - UART_
UARTCR_ BITS - UART_
UARTCR_ CTSEN_ ACCESS - UART_
UARTCR_ CTSEN_ BITS - UART_
UARTCR_ CTSEN_ LSB - UART_
UARTCR_ CTSEN_ MSB - UART_
UARTCR_ CTSEN_ RESET - UART_
UARTCR_ DTR_ ACCESS - UART_
UARTCR_ DTR_ BITS - UART_
UARTCR_ DTR_ LSB - UART_
UARTCR_ DTR_ MSB - UART_
UARTCR_ DTR_ RESET - UART_
UARTCR_ LBE_ ACCESS - UART_
UARTCR_ LBE_ BITS - UART_
UARTCR_ LBE_ LSB - UART_
UARTCR_ LBE_ MSB - UART_
UARTCR_ LBE_ RESET - UART_
UARTCR_ OFFSET - UART_
UARTCR_ OUT1_ ACCESS - UART_
UARTCR_ OUT1_ BITS - UART_
UARTCR_ OUT1_ LSB - UART_
UARTCR_ OUT1_ MSB - UART_
UARTCR_ OUT1_ RESET - UART_
UARTCR_ OUT2_ ACCESS - UART_
UARTCR_ OUT2_ BITS - UART_
UARTCR_ OUT2_ LSB - UART_
UARTCR_ OUT2_ MSB - UART_
UARTCR_ OUT2_ RESET - UART_
UARTCR_ RESET - UART_
UARTCR_ RTSEN_ ACCESS - UART_
UARTCR_ RTSEN_ BITS - UART_
UARTCR_ RTSEN_ LSB - UART_
UARTCR_ RTSEN_ MSB - UART_
UARTCR_ RTSEN_ RESET - UART_
UARTCR_ RTS_ ACCESS - UART_
UARTCR_ RTS_ BITS - UART_
UARTCR_ RTS_ LSB - UART_
UARTCR_ RTS_ MSB - UART_
UARTCR_ RTS_ RESET - UART_
UARTCR_ RXE_ ACCESS - UART_
UARTCR_ RXE_ BITS - UART_
UARTCR_ RXE_ LSB - UART_
UARTCR_ RXE_ MSB - UART_
UARTCR_ RXE_ RESET - UART_
UARTCR_ SIREN_ ACCESS - UART_
UARTCR_ SIREN_ BITS - UART_
UARTCR_ SIREN_ LSB - UART_
UARTCR_ SIREN_ MSB - UART_
UARTCR_ SIREN_ RESET - UART_
UARTCR_ SIRLP_ ACCESS - UART_
UARTCR_ SIRLP_ BITS - UART_
UARTCR_ SIRLP_ LSB - UART_
UARTCR_ SIRLP_ MSB - UART_
UARTCR_ SIRLP_ RESET - UART_
UARTCR_ TXE_ ACCESS - UART_
UARTCR_ TXE_ BITS - UART_
UARTCR_ TXE_ LSB - UART_
UARTCR_ TXE_ MSB - UART_
UARTCR_ TXE_ RESET - UART_
UARTCR_ UARTEN_ ACCESS - UART_
UARTCR_ UARTEN_ BITS - UART_
UARTCR_ UARTEN_ LSB - UART_
UARTCR_ UARTEN_ MSB - UART_
UARTCR_ UARTEN_ RESET - UART_
UARTDMACR_ BITS - UART_
UARTDMACR_ DMAONERR_ ACCESS - UART_
UARTDMACR_ DMAONERR_ BITS - UART_
UARTDMACR_ DMAONERR_ LSB - UART_
UARTDMACR_ DMAONERR_ MSB - UART_
UARTDMACR_ DMAONERR_ RESET - UART_
UARTDMACR_ OFFSET - UART_
UARTDMACR_ RESET - UART_
UARTDMACR_ RXDMAE_ ACCESS - UART_
UARTDMACR_ RXDMAE_ BITS - UART_
UARTDMACR_ RXDMAE_ LSB - UART_
UARTDMACR_ RXDMAE_ MSB - UART_
UARTDMACR_ RXDMAE_ RESET - UART_
UARTDMACR_ TXDMAE_ ACCESS - UART_
UARTDMACR_ TXDMAE_ BITS - UART_
UARTDMACR_ TXDMAE_ LSB - UART_
UARTDMACR_ TXDMAE_ MSB - UART_
UARTDMACR_ TXDMAE_ RESET - UART_
UARTDR_ BE_ ACCESS - UART_
UARTDR_ BE_ BITS - UART_
UARTDR_ BE_ LSB - UART_
UARTDR_ BE_ MSB - UART_
UARTDR_ BE_ RESET - UART_
UARTDR_ BITS - UART_
UARTDR_ DATA_ ACCESS - UART_
UARTDR_ DATA_ BITS - UART_
UARTDR_ DATA_ LSB - UART_
UARTDR_ DATA_ MSB - UART_
UARTDR_ DATA_ RESET - UART_
UARTDR_ FE_ ACCESS - UART_
UARTDR_ FE_ BITS - UART_
UARTDR_ FE_ LSB - UART_
UARTDR_ FE_ MSB - UART_
UARTDR_ FE_ RESET - UART_
UARTDR_ OE_ ACCESS - UART_
UARTDR_ OE_ BITS - UART_
UARTDR_ OE_ LSB - UART_
UARTDR_ OE_ MSB - UART_
UARTDR_ OE_ RESET - UART_
UARTDR_ OFFSET - UART_
UARTDR_ PE_ ACCESS - UART_
UARTDR_ PE_ BITS - UART_
UARTDR_ PE_ LSB - UART_
UARTDR_ PE_ MSB - UART_
UARTDR_ PE_ RESET - UART_
UARTDR_ RESET - UART_
UARTFBRD_ BAUD_ DIVFRAC_ ACCESS - UART_
UARTFBRD_ BAUD_ DIVFRAC_ BITS - UART_
UARTFBRD_ BAUD_ DIVFRAC_ LSB - UART_
UARTFBRD_ BAUD_ DIVFRAC_ MSB - UART_
UARTFBRD_ BAUD_ DIVFRAC_ RESET - UART_
UARTFBRD_ BITS - UART_
UARTFBRD_ OFFSET - UART_
UARTFBRD_ RESET - UART_
UARTFR_ BITS - UART_
UARTFR_ BUSY_ ACCESS - UART_
UARTFR_ BUSY_ BITS - UART_
UARTFR_ BUSY_ LSB - UART_
UARTFR_ BUSY_ MSB - UART_
UARTFR_ BUSY_ RESET - UART_
UARTFR_ CTS_ ACCESS - UART_
UARTFR_ CTS_ BITS - UART_
UARTFR_ CTS_ LSB - UART_
UARTFR_ CTS_ MSB - UART_
UARTFR_ CTS_ RESET - UART_
UARTFR_ DCD_ ACCESS - UART_
UARTFR_ DCD_ BITS - UART_
UARTFR_ DCD_ LSB - UART_
UARTFR_ DCD_ MSB - UART_
UARTFR_ DCD_ RESET - UART_
UARTFR_ DSR_ ACCESS - UART_
UARTFR_ DSR_ BITS - UART_
UARTFR_ DSR_ LSB - UART_
UARTFR_ DSR_ MSB - UART_
UARTFR_ DSR_ RESET - UART_
UARTFR_ OFFSET - UART_
UARTFR_ RESET - UART_
UARTFR_ RI_ ACCESS - UART_
UARTFR_ RI_ BITS - UART_
UARTFR_ RI_ LSB - UART_
UARTFR_ RI_ MSB - UART_
UARTFR_ RI_ RESET - UART_
UARTFR_ RXFE_ ACCESS - UART_
UARTFR_ RXFE_ BITS - UART_
UARTFR_ RXFE_ LSB - UART_
UARTFR_ RXFE_ MSB - UART_
UARTFR_ RXFE_ RESET - UART_
UARTFR_ RXFF_ ACCESS - UART_
UARTFR_ RXFF_ BITS - UART_
UARTFR_ RXFF_ LSB - UART_
UARTFR_ RXFF_ MSB - UART_
UARTFR_ RXFF_ RESET - UART_
UARTFR_ TXFE_ ACCESS - UART_
UARTFR_ TXFE_ BITS - UART_
UARTFR_ TXFE_ LSB - UART_
UARTFR_ TXFE_ MSB - UART_
UARTFR_ TXFE_ RESET - UART_
UARTFR_ TXFF_ ACCESS - UART_
UARTFR_ TXFF_ BITS - UART_
UARTFR_ TXFF_ LSB - UART_
UARTFR_ TXFF_ MSB - UART_
UARTFR_ TXFF_ RESET - UART_
UARTIBRD_ BAUD_ DIVINT_ ACCESS - UART_
UARTIBRD_ BAUD_ DIVINT_ BITS - UART_
UARTIBRD_ BAUD_ DIVINT_ LSB - UART_
UARTIBRD_ BAUD_ DIVINT_ MSB - UART_
UARTIBRD_ BAUD_ DIVINT_ RESET - UART_
UARTIBRD_ BITS - UART_
UARTIBRD_ OFFSET - UART_
UARTIBRD_ RESET - UART_
UARTICR_ BEIC_ ACCESS - UART_
UARTICR_ BEIC_ BITS - UART_
UARTICR_ BEIC_ LSB - UART_
UARTICR_ BEIC_ MSB - UART_
UARTICR_ BEIC_ RESET - UART_
UARTICR_ BITS - UART_
UARTICR_ CTSMIC_ ACCESS - UART_
UARTICR_ CTSMIC_ BITS - UART_
UARTICR_ CTSMIC_ LSB - UART_
UARTICR_ CTSMIC_ MSB - UART_
UARTICR_ CTSMIC_ RESET - UART_
UARTICR_ DCDMIC_ ACCESS - UART_
UARTICR_ DCDMIC_ BITS - UART_
UARTICR_ DCDMIC_ LSB - UART_
UARTICR_ DCDMIC_ MSB - UART_
UARTICR_ DCDMIC_ RESET - UART_
UARTICR_ DSRMIC_ ACCESS - UART_
UARTICR_ DSRMIC_ BITS - UART_
UARTICR_ DSRMIC_ LSB - UART_
UARTICR_ DSRMIC_ MSB - UART_
UARTICR_ DSRMIC_ RESET - UART_
UARTICR_ FEIC_ ACCESS - UART_
UARTICR_ FEIC_ BITS - UART_
UARTICR_ FEIC_ LSB - UART_
UARTICR_ FEIC_ MSB - UART_
UARTICR_ FEIC_ RESET - UART_
UARTICR_ OEIC_ ACCESS - UART_
UARTICR_ OEIC_ BITS - UART_
UARTICR_ OEIC_ LSB - UART_
UARTICR_ OEIC_ MSB - UART_
UARTICR_ OEIC_ RESET - UART_
UARTICR_ OFFSET - UART_
UARTICR_ PEIC_ ACCESS - UART_
UARTICR_ PEIC_ BITS - UART_
UARTICR_ PEIC_ LSB - UART_
UARTICR_ PEIC_ MSB - UART_
UARTICR_ PEIC_ RESET - UART_
UARTICR_ RESET - UART_
UARTICR_ RIMIC_ ACCESS - UART_
UARTICR_ RIMIC_ BITS - UART_
UARTICR_ RIMIC_ LSB - UART_
UARTICR_ RIMIC_ MSB - UART_
UARTICR_ RIMIC_ RESET - UART_
UARTICR_ RTIC_ ACCESS - UART_
UARTICR_ RTIC_ BITS - UART_
UARTICR_ RTIC_ LSB - UART_
UARTICR_ RTIC_ MSB - UART_
UARTICR_ RTIC_ RESET - UART_
UARTICR_ RXIC_ ACCESS - UART_
UARTICR_ RXIC_ BITS - UART_
UARTICR_ RXIC_ LSB - UART_
UARTICR_ RXIC_ MSB - UART_
UARTICR_ RXIC_ RESET - UART_
UARTICR_ TXIC_ ACCESS - UART_
UARTICR_ TXIC_ BITS - UART_
UARTICR_ TXIC_ LSB - UART_
UARTICR_ TXIC_ MSB - UART_
UARTICR_ TXIC_ RESET - UART_
UARTIFLS_ BITS - UART_
UARTIFLS_ OFFSET - UART_
UARTIFLS_ RESET - UART_
UARTIFLS_ RXIFLSEL_ ACCESS - UART_
UARTIFLS_ RXIFLSEL_ BITS - UART_
UARTIFLS_ RXIFLSEL_ LSB - UART_
UARTIFLS_ RXIFLSEL_ MSB - UART_
UARTIFLS_ RXIFLSEL_ RESET - UART_
UARTIFLS_ TXIFLSEL_ ACCESS - UART_
UARTIFLS_ TXIFLSEL_ BITS - UART_
UARTIFLS_ TXIFLSEL_ LSB - UART_
UARTIFLS_ TXIFLSEL_ MSB - UART_
UARTIFLS_ TXIFLSEL_ RESET - UART_
UARTILPR_ BITS - UART_
UARTILPR_ ILPDVSR_ ACCESS - UART_
UARTILPR_ ILPDVSR_ BITS - UART_
UARTILPR_ ILPDVSR_ LSB - UART_
UARTILPR_ ILPDVSR_ MSB - UART_
UARTILPR_ ILPDVSR_ RESET - UART_
UARTILPR_ OFFSET - UART_
UARTILPR_ RESET - UART_
UARTIMSC_ BEIM_ ACCESS - UART_
UARTIMSC_ BEIM_ BITS - UART_
UARTIMSC_ BEIM_ LSB - UART_
UARTIMSC_ BEIM_ MSB - UART_
UARTIMSC_ BEIM_ RESET - UART_
UARTIMSC_ BITS - UART_
UARTIMSC_ CTSMIM_ ACCESS - UART_
UARTIMSC_ CTSMIM_ BITS - UART_
UARTIMSC_ CTSMIM_ LSB - UART_
UARTIMSC_ CTSMIM_ MSB - UART_
UARTIMSC_ CTSMIM_ RESET - UART_
UARTIMSC_ DCDMIM_ ACCESS - UART_
UARTIMSC_ DCDMIM_ BITS - UART_
UARTIMSC_ DCDMIM_ LSB - UART_
UARTIMSC_ DCDMIM_ MSB - UART_
UARTIMSC_ DCDMIM_ RESET - UART_
UARTIMSC_ DSRMIM_ ACCESS - UART_
UARTIMSC_ DSRMIM_ BITS - UART_
UARTIMSC_ DSRMIM_ LSB - UART_
UARTIMSC_ DSRMIM_ MSB - UART_
UARTIMSC_ DSRMIM_ RESET - UART_
UARTIMSC_ FEIM_ ACCESS - UART_
UARTIMSC_ FEIM_ BITS - UART_
UARTIMSC_ FEIM_ LSB - UART_
UARTIMSC_ FEIM_ MSB - UART_
UARTIMSC_ FEIM_ RESET - UART_
UARTIMSC_ OEIM_ ACCESS - UART_
UARTIMSC_ OEIM_ BITS - UART_
UARTIMSC_ OEIM_ LSB - UART_
UARTIMSC_ OEIM_ MSB - UART_
UARTIMSC_ OEIM_ RESET - UART_
UARTIMSC_ OFFSET - UART_
UARTIMSC_ PEIM_ ACCESS - UART_
UARTIMSC_ PEIM_ BITS - UART_
UARTIMSC_ PEIM_ LSB - UART_
UARTIMSC_ PEIM_ MSB - UART_
UARTIMSC_ PEIM_ RESET - UART_
UARTIMSC_ RESET - UART_
UARTIMSC_ RIMIM_ ACCESS - UART_
UARTIMSC_ RIMIM_ BITS - UART_
UARTIMSC_ RIMIM_ LSB - UART_
UARTIMSC_ RIMIM_ MSB - UART_
UARTIMSC_ RIMIM_ RESET - UART_
UARTIMSC_ RTIM_ ACCESS - UART_
UARTIMSC_ RTIM_ BITS - UART_
UARTIMSC_ RTIM_ LSB - UART_
UARTIMSC_ RTIM_ MSB - UART_
UARTIMSC_ RTIM_ RESET - UART_
UARTIMSC_ RXIM_ ACCESS - UART_
UARTIMSC_ RXIM_ BITS - UART_
UARTIMSC_ RXIM_ LSB - UART_
UARTIMSC_ RXIM_ MSB - UART_
UARTIMSC_ RXIM_ RESET - UART_
UARTIMSC_ TXIM_ ACCESS - UART_
UARTIMSC_ TXIM_ BITS - UART_
UARTIMSC_ TXIM_ LSB - UART_
UARTIMSC_ TXIM_ MSB - UART_
UARTIMSC_ TXIM_ RESET - UART_
UARTLCR_ H_ BITS - UART_
UARTLCR_ H_ BRK_ ACCESS - UART_
UARTLCR_ H_ BRK_ BITS - UART_
UARTLCR_ H_ BRK_ LSB - UART_
UARTLCR_ H_ BRK_ MSB - UART_
UARTLCR_ H_ BRK_ RESET - UART_
UARTLCR_ H_ EPS_ ACCESS - UART_
UARTLCR_ H_ EPS_ BITS - UART_
UARTLCR_ H_ EPS_ LSB - UART_
UARTLCR_ H_ EPS_ MSB - UART_
UARTLCR_ H_ EPS_ RESET - UART_
UARTLCR_ H_ FEN_ ACCESS - UART_
UARTLCR_ H_ FEN_ BITS - UART_
UARTLCR_ H_ FEN_ LSB - UART_
UARTLCR_ H_ FEN_ MSB - UART_
UARTLCR_ H_ FEN_ RESET - UART_
UARTLCR_ H_ OFFSET - UART_
UARTLCR_ H_ PEN_ ACCESS - UART_
UARTLCR_ H_ PEN_ BITS - UART_
UARTLCR_ H_ PEN_ LSB - UART_
UARTLCR_ H_ PEN_ MSB - UART_
UARTLCR_ H_ PEN_ RESET - UART_
UARTLCR_ H_ RESET - UART_
UARTLCR_ H_ SPS_ ACCESS - UART_
UARTLCR_ H_ SPS_ BITS - UART_
UARTLCR_ H_ SPS_ LSB - UART_
UARTLCR_ H_ SPS_ MSB - UART_
UARTLCR_ H_ SPS_ RESET - UART_
UARTLCR_ H_ STP2_ ACCESS - UART_
UARTLCR_ H_ STP2_ BITS - UART_
UARTLCR_ H_ STP2_ LSB - UART_
UARTLCR_ H_ STP2_ MSB - UART_
UARTLCR_ H_ STP2_ RESET - UART_
UARTLCR_ H_ WLEN_ ACCESS - UART_
UARTLCR_ H_ WLEN_ BITS - UART_
UARTLCR_ H_ WLEN_ LSB - UART_
UARTLCR_ H_ WLEN_ MSB - UART_
UARTLCR_ H_ WLEN_ RESET - UART_
UARTMIS_ BEMIS_ ACCESS - UART_
UARTMIS_ BEMIS_ BITS - UART_
UARTMIS_ BEMIS_ LSB - UART_
UARTMIS_ BEMIS_ MSB - UART_
UARTMIS_ BEMIS_ RESET - UART_
UARTMIS_ BITS - UART_
UARTMIS_ CTSMMIS_ ACCESS - UART_
UARTMIS_ CTSMMIS_ BITS - UART_
UARTMIS_ CTSMMIS_ LSB - UART_
UARTMIS_ CTSMMIS_ MSB - UART_
UARTMIS_ CTSMMIS_ RESET - UART_
UARTMIS_ DCDMMIS_ ACCESS - UART_
UARTMIS_ DCDMMIS_ BITS - UART_
UARTMIS_ DCDMMIS_ LSB - UART_
UARTMIS_ DCDMMIS_ MSB - UART_
UARTMIS_ DCDMMIS_ RESET - UART_
UARTMIS_ DSRMMIS_ ACCESS - UART_
UARTMIS_ DSRMMIS_ BITS - UART_
UARTMIS_ DSRMMIS_ LSB - UART_
UARTMIS_ DSRMMIS_ MSB - UART_
UARTMIS_ DSRMMIS_ RESET - UART_
UARTMIS_ FEMIS_ ACCESS - UART_
UARTMIS_ FEMIS_ BITS - UART_
UARTMIS_ FEMIS_ LSB - UART_
UARTMIS_ FEMIS_ MSB - UART_
UARTMIS_ FEMIS_ RESET - UART_
UARTMIS_ OEMIS_ ACCESS - UART_
UARTMIS_ OEMIS_ BITS - UART_
UARTMIS_ OEMIS_ LSB - UART_
UARTMIS_ OEMIS_ MSB - UART_
UARTMIS_ OEMIS_ RESET - UART_
UARTMIS_ OFFSET - UART_
UARTMIS_ PEMIS_ ACCESS - UART_
UARTMIS_ PEMIS_ BITS - UART_
UARTMIS_ PEMIS_ LSB - UART_
UARTMIS_ PEMIS_ MSB - UART_
UARTMIS_ PEMIS_ RESET - UART_
UARTMIS_ RESET - UART_
UARTMIS_ RIMMIS_ ACCESS - UART_
UARTMIS_ RIMMIS_ BITS - UART_
UARTMIS_ RIMMIS_ LSB - UART_
UARTMIS_ RIMMIS_ MSB - UART_
UARTMIS_ RIMMIS_ RESET - UART_
UARTMIS_ RTMIS_ ACCESS - UART_
UARTMIS_ RTMIS_ BITS - UART_
UARTMIS_ RTMIS_ LSB - UART_
UARTMIS_ RTMIS_ MSB - UART_
UARTMIS_ RTMIS_ RESET - UART_
UARTMIS_ RXMIS_ ACCESS - UART_
UARTMIS_ RXMIS_ BITS - UART_
UARTMIS_ RXMIS_ LSB - UART_
UARTMIS_ RXMIS_ MSB - UART_
UARTMIS_ RXMIS_ RESET - UART_
UARTMIS_ TXMIS_ ACCESS - UART_
UARTMIS_ TXMIS_ BITS - UART_
UARTMIS_ TXMIS_ LSB - UART_
UARTMIS_ TXMIS_ MSB - UART_
UARTMIS_ TXMIS_ RESET - UART_
UARTPCELLI D0_ BITS - UART_
UARTPCELLI D0_ OFFSET - UART_
UARTPCELLI D0_ RESET - UART_
UARTPCELLI D0_ UARTPCELLI D0_ ACCESS - UART_
UARTPCELLI D0_ UARTPCELLI D0_ BITS - UART_
UARTPCELLI D0_ UARTPCELLI D0_ LSB - UART_
UARTPCELLI D0_ UARTPCELLI D0_ MSB - UART_
UARTPCELLI D0_ UARTPCELLI D0_ RESET - UART_
UARTPCELLI D1_ BITS - UART_
UARTPCELLI D1_ OFFSET - UART_
UARTPCELLI D1_ RESET - UART_
UARTPCELLI D1_ UARTPCELLI D1_ ACCESS - UART_
UARTPCELLI D1_ UARTPCELLI D1_ BITS - UART_
UARTPCELLI D1_ UARTPCELLI D1_ LSB - UART_
UARTPCELLI D1_ UARTPCELLI D1_ MSB - UART_
UARTPCELLI D1_ UARTPCELLI D1_ RESET - UART_
UARTPCELLI D2_ BITS - UART_
UARTPCELLI D2_ OFFSET - UART_
UARTPCELLI D2_ RESET - UART_
UARTPCELLI D2_ UARTPCELLI D2_ ACCESS - UART_
UARTPCELLI D2_ UARTPCELLI D2_ BITS - UART_
UARTPCELLI D2_ UARTPCELLI D2_ LSB - UART_
UARTPCELLI D2_ UARTPCELLI D2_ MSB - UART_
UARTPCELLI D2_ UARTPCELLI D2_ RESET - UART_
UARTPCELLI D3_ BITS - UART_
UARTPCELLI D3_ OFFSET - UART_
UARTPCELLI D3_ RESET - UART_
UARTPCELLI D3_ UARTPCELLI D3_ ACCESS - UART_
UARTPCELLI D3_ UARTPCELLI D3_ BITS - UART_
UARTPCELLI D3_ UARTPCELLI D3_ LSB - UART_
UARTPCELLI D3_ UARTPCELLI D3_ MSB - UART_
UARTPCELLI D3_ UARTPCELLI D3_ RESET - UART_
UARTPERIPHI D0_ BITS - UART_
UARTPERIPHI D0_ OFFSET - UART_
UARTPERIPHI D0_ PARTNUMBE R0_ ACCESS - UART_
UARTPERIPHI D0_ PARTNUMBE R0_ BITS - UART_
UARTPERIPHI D0_ PARTNUMBE R0_ LSB - UART_
UARTPERIPHI D0_ PARTNUMBE R0_ MSB - UART_
UARTPERIPHI D0_ PARTNUMBE R0_ RESET - UART_
UARTPERIPHI D0_ RESET - UART_
UARTPERIPHI D1_ BITS - UART_
UARTPERIPHI D1_ DESIGNE R0_ ACCESS - UART_
UARTPERIPHI D1_ DESIGNE R0_ BITS - UART_
UARTPERIPHI D1_ DESIGNE R0_ LSB - UART_
UARTPERIPHI D1_ DESIGNE R0_ MSB - UART_
UARTPERIPHI D1_ DESIGNE R0_ RESET - UART_
UARTPERIPHI D1_ OFFSET - UART_
UARTPERIPHI D1_ PARTNUMBE R1_ ACCESS - UART_
UARTPERIPHI D1_ PARTNUMBE R1_ BITS - UART_
UARTPERIPHI D1_ PARTNUMBE R1_ LSB - UART_
UARTPERIPHI D1_ PARTNUMBE R1_ MSB - UART_
UARTPERIPHI D1_ PARTNUMBE R1_ RESET - UART_
UARTPERIPHI D1_ RESET - UART_
UARTPERIPHI D2_ BITS - UART_
UARTPERIPHI D2_ DESIGNE R1_ ACCESS - UART_
UARTPERIPHI D2_ DESIGNE R1_ BITS - UART_
UARTPERIPHI D2_ DESIGNE R1_ LSB - UART_
UARTPERIPHI D2_ DESIGNE R1_ MSB - UART_
UARTPERIPHI D2_ DESIGNE R1_ RESET - UART_
UARTPERIPHI D2_ OFFSET - UART_
UARTPERIPHI D2_ RESET - UART_
UARTPERIPHI D2_ REVISION_ ACCESS - UART_
UARTPERIPHI D2_ REVISION_ BITS - UART_
UARTPERIPHI D2_ REVISION_ LSB - UART_
UARTPERIPHI D2_ REVISION_ MSB - UART_
UARTPERIPHI D2_ REVISION_ RESET - UART_
UARTPERIPHI D3_ BITS - UART_
UARTPERIPHI D3_ CONFIGURATION_ ACCESS - UART_
UARTPERIPHI D3_ CONFIGURATION_ BITS - UART_
UARTPERIPHI D3_ CONFIGURATION_ LSB - UART_
UARTPERIPHI D3_ CONFIGURATION_ MSB - UART_
UARTPERIPHI D3_ CONFIGURATION_ RESET - UART_
UARTPERIPHI D3_ OFFSET - UART_
UARTPERIPHI D3_ RESET - UART_
UARTRIS_ BERIS_ ACCESS - UART_
UARTRIS_ BERIS_ BITS - UART_
UARTRIS_ BERIS_ LSB - UART_
UARTRIS_ BERIS_ MSB - UART_
UARTRIS_ BERIS_ RESET - UART_
UARTRIS_ BITS - UART_
UARTRIS_ CTSRMIS_ ACCESS - UART_
UARTRIS_ CTSRMIS_ BITS - UART_
UARTRIS_ CTSRMIS_ LSB - UART_
UARTRIS_ CTSRMIS_ MSB - UART_
UARTRIS_ CTSRMIS_ RESET - UART_
UARTRIS_ DCDRMIS_ ACCESS - UART_
UARTRIS_ DCDRMIS_ BITS - UART_
UARTRIS_ DCDRMIS_ LSB - UART_
UARTRIS_ DCDRMIS_ MSB - UART_
UARTRIS_ DCDRMIS_ RESET - UART_
UARTRIS_ DSRRMIS_ ACCESS - UART_
UARTRIS_ DSRRMIS_ BITS - UART_
UARTRIS_ DSRRMIS_ LSB - UART_
UARTRIS_ DSRRMIS_ MSB - UART_
UARTRIS_ DSRRMIS_ RESET - UART_
UARTRIS_ FERIS_ ACCESS - UART_
UARTRIS_ FERIS_ BITS - UART_
UARTRIS_ FERIS_ LSB - UART_
UARTRIS_ FERIS_ MSB - UART_
UARTRIS_ FERIS_ RESET - UART_
UARTRIS_ OERIS_ ACCESS - UART_
UARTRIS_ OERIS_ BITS - UART_
UARTRIS_ OERIS_ LSB - UART_
UARTRIS_ OERIS_ MSB - UART_
UARTRIS_ OERIS_ RESET - UART_
UARTRIS_ OFFSET - UART_
UARTRIS_ PERIS_ ACCESS - UART_
UARTRIS_ PERIS_ BITS - UART_
UARTRIS_ PERIS_ LSB - UART_
UARTRIS_ PERIS_ MSB - UART_
UARTRIS_ PERIS_ RESET - UART_
UARTRIS_ RESET - UART_
UARTRIS_ RIRMIS_ ACCESS - UART_
UARTRIS_ RIRMIS_ BITS - UART_
UARTRIS_ RIRMIS_ LSB - UART_
UARTRIS_ RIRMIS_ MSB - UART_
UARTRIS_ RIRMIS_ RESET - UART_
UARTRIS_ RTRIS_ ACCESS - UART_
UARTRIS_ RTRIS_ BITS - UART_
UARTRIS_ RTRIS_ LSB - UART_
UARTRIS_ RTRIS_ MSB - UART_
UARTRIS_ RTRIS_ RESET - UART_
UARTRIS_ RXRIS_ ACCESS - UART_
UARTRIS_ RXRIS_ BITS - UART_
UARTRIS_ RXRIS_ LSB - UART_
UARTRIS_ RXRIS_ MSB - UART_
UARTRIS_ RXRIS_ RESET - UART_
UARTRIS_ TXRIS_ ACCESS - UART_
UARTRIS_ TXRIS_ BITS - UART_
UARTRIS_ TXRIS_ LSB - UART_
UARTRIS_ TXRIS_ MSB - UART_
UARTRIS_ TXRIS_ RESET - UART_
UARTRSR_ BE_ ACCESS - UART_
UARTRSR_ BE_ BITS - UART_
UARTRSR_ BE_ LSB - UART_
UARTRSR_ BE_ MSB - UART_
UARTRSR_ BE_ RESET - UART_
UARTRSR_ BITS - UART_
UARTRSR_ FE_ ACCESS - UART_
UARTRSR_ FE_ BITS - UART_
UARTRSR_ FE_ LSB - UART_
UARTRSR_ FE_ MSB - UART_
UARTRSR_ FE_ RESET - UART_
UARTRSR_ OE_ ACCESS - UART_
UARTRSR_ OE_ BITS - UART_
UARTRSR_ OE_ LSB - UART_
UARTRSR_ OE_ MSB - UART_
UARTRSR_ OE_ RESET - UART_
UARTRSR_ OFFSET - UART_
UARTRSR_ PE_ ACCESS - UART_
UARTRSR_ PE_ BITS - UART_
UARTRSR_ PE_ LSB - UART_
UARTRSR_ PE_ MSB - UART_
UARTRSR_ PE_ RESET - UART_
UARTRSR_ RESET - UINT8_
MAX - UINT16_
MAX - UINT32_
MAX - UINT64_
MAX - UINTPTR_
MAX - UINT_
FAST8_ MAX - UINT_
FAST16_ MAX - UINT_
FAST32_ MAX - UINT_
FAST64_ MAX - UINT_
LEAS T8_ MAX - UINT_
LEAS T16_ MAX - UINT_
LEAS T32_ MAX - UINT_
LEAS T64_ MAX - USBCTRL_
BASE - USBCTRL_
DPRAM_ BASE - USBCTRL_
REGS_ BASE - VREG_
AND_ CHIP_ RESET_ BASE - WATCHDOG_
BASE - WINT_
MAX - WINT_
MIN - XIP_
AUX_ BASE - XIP_
BASE - XIP_
CTRL_ BASE - XIP_
MAIN_ BASE - XIP_
NOALLOC_ BASE - XIP_
NOCACHE_ BASE - XIP_
NOCACHE_ NOALLOC_ BASE - XIP_
SRAM_ BASE - XIP_
SRAM_ END - XIP_
SSI_ BASE - XOSC_
BASE - XOSC_
MHZ - _DARWIN_
FEATURE_ 64_ BIT_ INODE - _DARWIN_
FEATURE_ ONLY_ UNIX_ CONFORMANCE - _DARWIN_
FEATURE_ UNIX_ CONFORMANCE - __
DARWIN_ 64_ BIT_ INO_ T - __
DARWIN_ C_ ANSI - __
DARWIN_ C_ FULL - __
DARWIN_ C_ LEVEL - __
DARWIN_ NON_ CANCELABLE - __
DARWIN_ NO_ LONG_ LONG - __
DARWIN_ ONLY_ 64_ BIT_ INO_ T - __
DARWIN_ ONLY_ UNIX_ CONFORMANCE - __
DARWIN_ ONLY_ VERS_ 1050 - __
DARWIN_ SUF_ 64_ BIT_ INO_ T - __
DARWIN_ SUF_ 1050 - __
DARWIN_ SUF_ EXTSN - __
DARWIN_ UNIX03 - __
DARWIN_ VERS_ 1050 - __
PTHREAD_ ATTR_ SIZE__ - __
PTHREAD_ CONDATTR_ SIZE__ - __
PTHREAD_ COND_ SIZE__ - __
PTHREAD_ MUTEXATTR_ SIZE__ - __
PTHREAD_ MUTEX_ SIZE__ - __
PTHREAD_ ONCE_ SIZE__ - __
PTHREAD_ RWLOCKATTR_ SIZE__ - __
PTHREAD_ RWLOCK_ SIZE__ - __
PTHREAD_ SIZE__ - __
STDC_ WANT_ LIB_ EXT1__ - __
WORDSIZE - __
bool_ true_ false_ are_ defined - false_
- gpio_
function_ GPIO_ FUNC_ GPCK - gpio_
function_ GPIO_ FUNC_ I2C - gpio_
function_ GPIO_ FUNC_ NULL - gpio_
function_ GPIO_ FUNC_ PIO0 - gpio_
function_ GPIO_ FUNC_ PIO1 - gpio_
function_ GPIO_ FUNC_ PWM - gpio_
function_ GPIO_ FUNC_ SIO - gpio_
function_ GPIO_ FUNC_ SPI - gpio_
function_ GPIO_ FUNC_ UART - gpio_
function_ GPIO_ FUNC_ USB - gpio_
function_ GPIO_ FUNC_ XIP - gpio_
irq_ level_ GPIO_ IRQ_ EDGE_ FALL - gpio_
irq_ level_ GPIO_ IRQ_ EDGE_ RISE - gpio_
irq_ level_ GPIO_ IRQ_ LEVEL_ HIGH - gpio_
irq_ level_ GPIO_ IRQ_ LEVEL_ LOW - gpio_
override_ GPIO_ OVERRIDE_ HIGH - < drive high/enable output
- gpio_
override_ GPIO_ OVERRIDE_ INVERT - < invert peripheral signal selected via \ref gpio_set_function
- gpio_
override_ GPIO_ OVERRIDE_ LOW - < drive low/disable output
- gpio_
override_ GPIO_ OVERRIDE_ NORMAL - < peripheral signal selected via \ref gpio_set_function
- true_
- uart_
parity_ t_ UART_ PARITY_ EVEN - uart_
parity_ t_ UART_ PARITY_ NONE - uart_
parity_ t_ UART_ PARITY_ ODD
Statics§
Functions§
- __
assert_ ⚠rtn - alarm_
pool_ ⚠add_ alarm_ at - \brief Add an alarm callback to be called at a specific time \ingroup alarm
- alarm_
pool_ ⚠add_ repeating_ timer_ us - \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds \ingroup repeating_timer
- alarm_
pool_ ⚠cancel_ alarm - \brief Cancel an alarm \ingroup alarm \param pool the alarm_pool containing the alarm \param alarm_id the alarm \return true if the alarm was cancelled, false if it didn’t exist \sa alarm_id_t for a note on reuse of IDs
- alarm_
pool_ ⚠create - \brief Create an alarm pool
- alarm_
pool_ ⚠destroy - \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm \ingroup alarm \param pool the pool \return the hardware alarm used by the pool
- alarm_
pool_ ⚠get_ default - \brief The default alarm pool used when alarms are added without specifying an alarm pool, and also used by the Pico SDK to support lower power sleeps and timeouts.
- alarm_
pool_ ⚠hardware_ alarm_ num - \brief Return the hardware alarm used by an alarm pool \ingroup alarm \param pool the pool \return the hardware alarm used by the pool
- alarm_
pool_ ⚠init_ default - \brief Create the default alarm pool (if not already created or disabled) \ingroup alarm
- best_
effort_ ⚠wfe_ or_ timeout - \brief Helper method for blocking on a timeout \ingroup sleep
- busy_
wait_ ⚠until - \brief Busy wait wasting cycles until after the specified timestamp \ingroup hardware_timer
- busy_
wait_ ⚠us - \brief Busy wait wasting cycles for the given (64 bit) number of microseconds \ingroup hardware_timer
- busy_
wait_ ⚠us_ 32 - \brief Busy wait wasting cycles for the given (32 bit) number of microseconds \ingroup hardware_timer
- cancel_
repeating_ ⚠timer - \brief Cancel a repeating timer \ingroup repeating_timer \param timer the repeating timer to cancel \return true if the repeating timer was cancelled, false if it didn’t exist \sa alarm_id_t for a note on reuse of IDs
- check_
sys_ ⚠clock_ khz - \brief Check if a given system clock frequency is valid/attainable \ingroup pico_stdlib
- getchar_
timeout_ ⚠us - \brief Return a character from stdin if there is one available within a timeout \ingroup pico_stdio
- gpio_
acknowledge_ ⚠irq - \brief Acknowledge a GPIO interrupt \ingroup hardware_gpio
- gpio_
clr_ ⚠mask - gpio_
debug_ ⚠pins_ init - gpio_
get_ ⚠function - gpio_
init ⚠ - \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) \ingroup hardware_gpio
- gpio_
init_ ⚠mask - \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO) \ingroup hardware_gpio
- gpio_
pull_ ⚠up - gpio_
put ⚠ - gpio_
set_ ⚠dir - gpio_
set_ ⚠dir_ in_ masked - gpio_
set_ ⚠dir_ masked - gpio_
set_ ⚠dir_ out_ masked - gpio_
set_ ⚠dormant_ irq_ enabled - \brief Enable dormant wake up interrupt for specified GPIO \ingroup hardware_gpio
- gpio_
set_ ⚠function - \brief Select GPIO function \ingroup hardware_gpio
- gpio_
set_ ⚠inover - \brief Select GPIO input override \ingroup hardware_gpio
- gpio_
set_ ⚠input_ enabled - \brief Enable GPIO input \ingroup hardware_gpio
- gpio_
set_ ⚠irq_ enabled - \brief Enable or disable interrupts for specified GPIO \ingroup hardware_gpio
- gpio_
set_ ⚠irq_ enabled_ with_ callback - \brief Enable interrupts for specified GPIO \ingroup hardware_gpio
- gpio_
set_ ⚠mask - gpio_
set_ ⚠oeover - \brief Select GPIO output enable override \ingroup hardware_gpio
- gpio_
set_ ⚠outover - \brief Set GPIO output override \ingroup hardware_gpio
- gpio_
set_ ⚠pulls - \brief Select up and down pulls on specific GPIO \ingroup hardware_gpio
- gpio_
xor_ ⚠mask - hardware_
alarm_ ⚠cancel - \brief Cancel an existing target (if any) for a given hardware_alarm
- hardware_
alarm_ ⚠claim - \brief cooperatively claim the use of this hardware alarm_num \ingroup hardware_timer
- hardware_
alarm_ ⚠set_ callback - \brief Enable/Disable a callback for a hardware timer on this core \ingroup hardware_timer
- hardware_
alarm_ ⚠set_ target - \brief Set the current target for the specified hardware alarm
- hardware_
alarm_ ⚠unclaim - \brief cooperatively release the claim on use of this hardware alarm_num \ingroup hardware_timer
- panic⚠
- panic_
unsupported ⚠ - rp2040_
chip_ ⚠version - running_
on_ ⚠fpga - set_
sys_ ⚠clock_ 48mhz - \brief Initialise the system clock to 48MHz \ingroup pico_stdlib
- set_
sys_ ⚠clock_ pll - \brief Initialise the system clock \ingroup pico_stdlib
- setup_
default_ ⚠uart - \brief Set up the default UART and assign it to the default GPIO’s \ingroup pico_stdlib
- sleep_
ms ⚠ - \brief Wait for the given number of milliseconds before returning \ingroup sleep
- sleep_
until ⚠ - \brief Wait until after the given timestamp to return \ingroup sleep
- sleep_
us ⚠ - \brief Wait for the given number of microseconds before returning \ingroup sleep
- stdio_
filter_ ⚠driver - \brief Control limiting of output to a single driver \ingroup pico_stdio
- stdio_
flush ⚠ - \brief Initialize all of the present standard stdio types that are linked into the binary. \ingroup pico_stdio
- stdio_
init_ ⚠all - \brief Initialize all of the present standard stdio types that are linked into the binary. \ingroup pico_stdio
- stdio_
set_ ⚠driver_ enabled - \brief Adds or removes a driver from the list of active drivers used for input/output \ingroup pico_stdio
- stdio_
set_ ⚠translate_ crlf - \brief control conversion of line feeds to carriage return on transmissions \ingroup pico_stdio
- time_
us_ ⚠64 - \brief Return the current 64 bit timestamp value in microseconds \ingroup hardware_timer
- uart_
deinit ⚠ - \brief DeInitialise a UART \ingroup hardware_uart
- uart_
init ⚠ - \brief Initialise a UART \ingroup hardware_uart
- uart_
is_ ⚠readable_ within_ us - \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty \ingroup hardware_uart
- uart_
set_ ⚠baudrate - \brief Set UART baud rate \ingroup hardware_uart
- uart_
set_ ⚠translate_ crlf - \brief Set CR/LF conversion on UART \ingroup hardware_uart
Type Aliases§
- __
builtin_ va_ list - __
darwin_ blkcnt_ t - __
darwin_ blksize_ t - __
darwin_ clock_ t - __
darwin_ ct_ rune_ t - __
darwin_ dev_ t - __
darwin_ fsblkcnt_ t - __
darwin_ fsfilcnt_ t - __
darwin_ gid_ t - __
darwin_ id_ t - __
darwin_ ino64_ t - __
darwin_ ino_ t - __
darwin_ intptr_ t - __
darwin_ mach_ port_ name_ t - __
darwin_ mach_ port_ t - __
darwin_ mbstate_ t - __
darwin_ mode_ t - __
darwin_ natural_ t - __
darwin_ off_ t - __
darwin_ pid_ t - __
darwin_ pthread_ attr_ t - __
darwin_ pthread_ cond_ t - __
darwin_ pthread_ condattr_ t - __
darwin_ pthread_ key_ t - __
darwin_ pthread_ mutex_ t - __
darwin_ pthread_ mutexattr_ t - __
darwin_ pthread_ once_ t - __
darwin_ pthread_ rwlock_ t - __
darwin_ pthread_ rwlockattr_ t - __
darwin_ pthread_ t - __
darwin_ ptrdiff_ t - __
darwin_ rune_ t - __
darwin_ sigset_ t - __
darwin_ size_ t - __
darwin_ socklen_ t - __
darwin_ ssize_ t - __
darwin_ suseconds_ t - __
darwin_ time_ t - __
darwin_ uid_ t - __
darwin_ useconds_ t - __
darwin_ uuid_ string_ t - __
darwin_ uuid_ t - __
darwin_ va_ list - __
darwin_ wchar_ t - __
darwin_ wint_ t - __
int8_ t - __
int16_ t - __
int32_ t - __
int64_ t - __
uint8_ t - __
uint16_ t - __
uint32_ t - __
uint64_ t - _bindgen_
ty_ 1 - Common return codes from pico_sdk methods that return a status
- alarm_
callback_ t - \brief User alarm callback \ingroup alarm \param id the alarm_id as returned when the alarm was added \param user_data the user data passed when the alarm was added \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire \return >0 to reschedule the same alarm this many us from the time this method returns \return 0 to not reschedule the alarm
- alarm_
id_ t - \brief The identifier for an alarm
- alarm_
pool_ t - const_
ioptr - gpio_
function - \brief GPIO function definitions for use with function select \ingroup hardware_gpio \brief GPIO function selectors
- gpio_
irq_ callback_ t - gpio_
irq_ level - \brief GPIO Interrupt level definitions \ingroup hardware_gpio \brief GPIO Interrupt levels
- gpio_
override - hardware_
alarm_ callback_ t - Callback function type for hardware alarms \ingroup hardware_timer
- int_
fast8_ t - int_
fast16_ t - int_
fast32_ t - int_
fast64_ t - int_
least8_ t - int_
least16_ t - int_
least32_ t - int_
least64_ t - io_ro_8
- io_
ro_ 16 - io_
ro_ 32 - io_rw_8
- io_
rw_ 16 - io_
rw_ 32 - io_wo_8
- io_
wo_ 16 - io_
wo_ 32 - ioptr
- max_
align_ t - register_
t - repeating_
timer_ callback_ t - \brief Callback for a repeating timer \ingroup repeating_timer \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user \return true to continue repeating, false to stop.
- repeating_
timer_ t - \defgroup repeating_timer repeating_timer \ingroup pico_time \brief Repeating Timer functions for simple scheduling of repeated execution
- rsize_t
- stdio_
driver_ t - syscall_
arg_ t - u_
int8_ t - u_
int16_ t - u_
int32_ t - u_
int64_ t - uart_
inst_ t - \file hardware/uart.h \defgroup hardware_uart hardware_uart
- uart_
parity_ t - \brief UART Parity enumeration \ingroup hardware_uart
- uint
- uint_
fast8_ t - uint_
fast16_ t - uint_
fast32_ t - uint_
fast64_ t - uint_
least8_ t - uint_
least16_ t - uint_
least32_ t - uint_
least64_ t - user_
addr_ t - user_
long_ t - user_
off_ t - user_
size_ t - user_
ssize_ t - user_
time_ t - user_
ulong_ t - wchar_t