rp235x_hal/uart/
utils.rs

1use crate::pac::dma::ch::ch_ctrl_trig::TREQ_SEL_A;
2use crate::pac::{uart0::RegisterBlock, UART0, UART1};
3use crate::resets::SubsystemReset;
4use crate::typelevel::Sealed;
5use core::ops::Deref;
6
7#[doc(inline)]
8pub use rp_hal_common::uart::{DataBits, Parity, StopBits, UartConfig};
9
10/// Error type for UART operations.
11#[derive(Debug)]
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13pub enum Error {
14    /// Bad argument : when things overflow, ...
15    BadArgument,
16}
17
18/// State of the UART Peripheral.
19pub trait State: Sealed {}
20
21/// Trait to handle both underlying devices (UART0 & UART1)
22pub trait UartDevice: Deref<Target = RegisterBlock> + SubsystemReset + Sealed + 'static {
23    /// Index of the Uart.
24    const ID: usize;
25
26    /// The DREQ number for which TX DMA requests are triggered.
27    fn tx_dreq() -> u8
28    where
29        Self: Sized;
30    /// The DREQ number for which RX DMA requests are triggered.
31    fn rx_dreq() -> u8
32    where
33        Self: Sized;
34}
35
36impl UartDevice for UART0 {
37    const ID: usize = 0;
38
39    /// The DREQ number for which TX DMA requests are triggered.
40    fn tx_dreq() -> u8 {
41        TREQ_SEL_A::UART0_TX.into()
42    }
43    /// The DREQ number for which RX DMA requests are triggered.
44    fn rx_dreq() -> u8 {
45        TREQ_SEL_A::UART0_RX.into()
46    }
47}
48impl Sealed for UART0 {}
49impl UartDevice for UART1 {
50    const ID: usize = 1;
51
52    /// The DREQ number for which TX DMA requests are triggered.
53    fn tx_dreq() -> u8 {
54        TREQ_SEL_A::UART1_TX.into()
55    }
56    /// The DREQ number for which RX DMA requests are triggered.
57    fn rx_dreq() -> u8 {
58        TREQ_SEL_A::UART1_RX.into()
59    }
60}
61impl Sealed for UART1 {}
62
63/// UART is enabled.
64pub struct Enabled;
65
66/// UART is disabled.
67pub struct Disabled;
68
69impl State for Enabled {}
70impl Sealed for Enabled {}
71impl State for Disabled {}
72impl Sealed for Disabled {}
73
74/// Rx/Tx FIFO Watermark
75///
76/// Determine the FIFO level that trigger DMA/Interrupt
77/// Default is Bytes16, see DS Table 423 and UARTIFLS Register
78/// Example of use:
79///     uart0.set_fifos(true); // Default is false
80///     uart0.set_rx_watermark(hal::uart::FifoWatermark::Bytes8);
81///     uart0.enable_rx_interrupt();
82pub enum FifoWatermark {
83    /// Trigger when 4 bytes are (Rx: filled / Tx: available)
84    Bytes4,
85    /// Trigger when 8 bytes are (Rx: filled / Tx: available)
86    Bytes8,
87    /// Trigger when 16 bytes are (Rx: filled / Tx: available)
88    Bytes16,
89    /// Trigger when 24 bytes are (Rx: filled / Tx: available)
90    Bytes24,
91    /// Trigger when 28 bytes are (Rx: filled / Tx: available)
92    Bytes28,
93}
rp235x_hal/uart/utils.rs

rp235x_hal/uart/
utils.rs
