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Crate rp2350_emu

Crate rp2350_emu 

Source

Re-exports§

pub use self::bus::Bus;
pub use self::core::CoreCounters;
pub use self::core::CortexM33;
pub use self::core_riscv::Hazard3;
pub use self::sio::Sio;

Modules§

bootrom_hooks
RP2350 bootrom mask-ROM hook resolution (HLD V5 §“Component 3”).
bus
core
core_riscv
dma
RP2350 DMA controller — Phase 3 (HLD V5 §5.6).
dreq
RP2350 DREQ (data request) constants — Phase 3.
irq
RP2350 interrupt-number constants (NVIC input line numbers, 0..=51).
memory
RP2350-specific memory bank topology.
peripherals
RP2350 on-chip peripheral models.
pio
Chip-side PIO re-exports.
sio
threaded
Threaded primitives for Phase 2 of the dual-core emulation effort.

Structs§

Clock
Master cycle counter. All timing in the emulator derives from this.
Config
Emulator configuration.
Emulator
Top-level RP2350 emulator. Owns dual cores (Arm or RISC-V), bus fabric, memory, and clock. SIO is owned by Bus. Peripherals and PIO are injected via builder.
EmulatorBuilder
Builder for assembling the emulator with optional peripherals.
Memory
Unified memory backing stores. Owns the actual byte arrays for ROM, SRAM, and flash (XIP). No bus fabric or timing — just raw storage.
Pacer
Real-time pacer that spin-waits to keep emulation at the target clock rate.
PacerSnapshot
Point-in-time snapshot of pacer stats. All values are plain integers copied from the atomic counters. Derived metrics are computed here to keep the hot path (atomic updates) minimal.
PacerStats
Shared monitoring state. Atomic counters updated on the hot path, safe to read from any thread without locking.

Enums§

Arch
Architecture selector. RP2350 ships both an Arm and a RISC-V complex; OTP/POWMAN picks one at power-up. V1 only constructs the Arm path with a real ISA — see wrk_docs/2026.04.17 - HLD - RP2350 RISC-V Hazard3 Core Support.md.
ConfigError
Errors returned by EmulatorBuilder::build. The only non-trivial variant today is ThreadingUnavailable, returned when the caller selects ExecutionModel::Threaded but the host platform or build configuration cannot satisfy it.
Cores
Per-arch core pair. expect_arm* / expect_riscv* panic on the wrong arm — documented programmer-error contract for call sites that the shimmed Emulator::core(id) path can’t cover.
EmulatorError
Errors returned by post-construction Emulator methods. Surface for runtime-model mismatches and worker panics (dual-execution HLD V1 §5.5).
ExecutionModel
Execution model for an Emulator. Selected at construction via EmulatorBuilder::execution; cannot be switched post-build.
StopReason
Stop reason when running until a condition.

Constants§

DEFAULT_STEP_QUANTUM
Default quantum size in cycles. Each Emulator::step() advances the system by exactly this many virtual cycles; both cores run atomically (instruction-at-a-time) until their per-core cycle count catches up with the target. 64 cycles @ 150 MHz is ~430 ns — well below any firmware-observable timing the emulator currently models.
ROSC_FREQ_HZ
ROSC nominal frequency (~6.5 MHz). The RP2350 boots on ROSC; PLL configuration (if any) happens later in firmware.

Functions§

load_pinned_silicon_bootrom
Loads the pinned silicon-derived RP2354 bootrom from the in-tree roms/rp2350/bootrom-combined.bin, verifies it against the sibling bootrom-combined.bin.sha256, and returns the raw bytes.