Top-level RP2350 emulator. Owns dual cores (Arm or RISC-V), bus
fabric, memory, and clock. SIO is owned by Bus. Peripherals and PIO
are injected via builder.
Point-in-time snapshot of pacer stats. All values are plain integers
copied from the atomic counters. Derived metrics are computed here
to keep the hot path (atomic updates) minimal.
Architecture selector. RP2350 ships both an Arm and a RISC-V
complex; OTP/POWMAN picks one at power-up. V1 only constructs the
Arm path with a real ISA — see
wrk_docs/2026.04.17 - HLD - RP2350 RISC-V Hazard3 Core Support.md.
Errors returned by EmulatorBuilder::build. The only non-trivial
variant today is ThreadingUnavailable, returned when the caller
selects ExecutionModel::Threaded but the host platform or build
configuration cannot satisfy it.
Per-arch core pair. expect_arm* / expect_riscv* panic on the
wrong arm — documented programmer-error contract for call sites
that the shimmed Emulator::core(id) path can’t cover.
Default quantum size in cycles. Each Emulator::step() advances the
system by exactly this many virtual cycles; both cores run atomically
(instruction-at-a-time) until their per-core cycle count catches up
with the target. 64 cycles @ 150 MHz is ~430 ns — well below any
firmware-observable timing the emulator currently models.
Loads the pinned silicon-derived RP2354 bootrom from the in-tree
roms/rp2350/bootrom-combined.bin, verifies it against the sibling
bootrom-combined.bin.sha256, and returns the raw bytes.