[][src]Type Definition rp2040::pio0::SM0_CLKDIV

type SM0_CLKDIV = Reg<u32, _SM0_CLKDIV>;

Clock divider register for state machine 0\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see sm0_clkdiv module

Trait Implementations

impl Readable for SM0_CLKDIV[src]

read() method returns sm0_clkdiv::R reader structure

impl ResetValue for SM0_CLKDIV[src]

Register SM0_CLKDIV reset()'s with value 0x0001_0000

type Type = u32

Register size

impl Writable for SM0_CLKDIV[src]

write(|w| ..) method takes sm0_clkdiv::W writer structure