[−][src]Struct rp2040::XIP_SSI
DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset.
Implementations
impl XIP_SSI
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pub const fn ptr() -> *const RegisterBlock
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Returns a pointer to the register block
Trait Implementations
impl Deref for XIP_SSI
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type Target = RegisterBlock
The resulting type after dereferencing.
pub fn deref(&self) -> &Self::Target
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impl Send for XIP_SSI
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,