Struct rp2040::pio0::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub fstat: FSTAT,
    pub fdebug: FDEBUG,
    pub flevel: FLEVEL,
    pub txf0: TXF0,
    pub txf1: TXF1,
    pub txf2: TXF2,
    pub txf3: TXF3,
    pub rxf0: RXF0,
    pub rxf1: RXF1,
    pub rxf2: RXF2,
    pub rxf3: RXF3,
    pub irq: IRQ,
    pub irq_force: IRQ_FORCE,
    pub input_sync_bypass: INPUT_SYNC_BYPASS,
    pub dbg_padout: DBG_PADOUT,
    pub dbg_padoe: DBG_PADOE,
    pub dbg_cfginfo: DBG_CFGINFO,
    pub instr_mem0: INSTR_MEM0,
    pub instr_mem1: INSTR_MEM1,
    pub instr_mem2: INSTR_MEM2,
    pub instr_mem3: INSTR_MEM3,
    pub instr_mem4: INSTR_MEM4,
    pub instr_mem5: INSTR_MEM5,
    pub instr_mem6: INSTR_MEM6,
    pub instr_mem7: INSTR_MEM7,
    pub instr_mem8: INSTR_MEM8,
    pub instr_mem9: INSTR_MEM9,
    pub instr_mem10: INSTR_MEM10,
    pub instr_mem11: INSTR_MEM11,
    pub instr_mem12: INSTR_MEM12,
    pub instr_mem13: INSTR_MEM13,
    pub instr_mem14: INSTR_MEM14,
    pub instr_mem15: INSTR_MEM15,
    pub instr_mem16: INSTR_MEM16,
    pub instr_mem17: INSTR_MEM17,
    pub instr_mem18: INSTR_MEM18,
    pub instr_mem19: INSTR_MEM19,
    pub instr_mem20: INSTR_MEM20,
    pub instr_mem21: INSTR_MEM21,
    pub instr_mem22: INSTR_MEM22,
    pub instr_mem23: INSTR_MEM23,
    pub instr_mem24: INSTR_MEM24,
    pub instr_mem25: INSTR_MEM25,
    pub instr_mem26: INSTR_MEM26,
    pub instr_mem27: INSTR_MEM27,
    pub instr_mem28: INSTR_MEM28,
    pub instr_mem29: INSTR_MEM29,
    pub instr_mem30: INSTR_MEM30,
    pub instr_mem31: INSTR_MEM31,
    pub sm0_clkdiv: SM0_CLKDIV,
    pub sm0_execctrl: SM0_EXECCTRL,
    pub sm0_shiftctrl: SM0_SHIFTCTRL,
    pub sm0_addr: SM0_ADDR,
    pub sm0_instr: SM0_INSTR,
    pub sm0_pinctrl: SM0_PINCTRL,
    pub sm1_clkdiv: SM1_CLKDIV,
    pub sm1_execctrl: SM1_EXECCTRL,
    pub sm1_shiftctrl: SM1_SHIFTCTRL,
    pub sm1_addr: SM1_ADDR,
    pub sm1_instr: SM1_INSTR,
    pub sm1_pinctrl: SM1_PINCTRL,
    pub sm2_clkdiv: SM2_CLKDIV,
    pub sm2_execctrl: SM2_EXECCTRL,
    pub sm2_shiftctrl: SM2_SHIFTCTRL,
    pub sm2_addr: SM2_ADDR,
    pub sm2_instr: SM2_INSTR,
    pub sm2_pinctrl: SM2_PINCTRL,
    pub sm3_clkdiv: SM3_CLKDIV,
    pub sm3_execctrl: SM3_EXECCTRL,
    pub sm3_shiftctrl: SM3_SHIFTCTRL,
    pub sm3_addr: SM3_ADDR,
    pub sm3_instr: SM3_INSTR,
    pub sm3_pinctrl: SM3_PINCTRL,
    pub intr: INTR,
    pub irq0_inte: IRQ0_INTE,
    pub irq0_intf: IRQ0_INTF,
    pub irq0_ints: IRQ0_INTS,
    pub irq1_inte: IRQ1_INTE,
    pub irq1_intf: IRQ1_INTF,
    pub irq1_ints: IRQ1_INTS,
}

Register block

Fields

ctrl: CTRL

0x00 - PIO control register

fstat: FSTAT

0x04 - FIFO status register

fdebug: FDEBUG

0x08 - FIFO debug register

flevel: FLEVEL

0x0c - FIFO levels

txf0: TXF0

0x10 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.

txf1: TXF1

0x14 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.

txf2: TXF2

0x18 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.

txf3: TXF3

0x1c - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.

rxf0: RXF0

0x20 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.

rxf1: RXF1

0x24 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.

rxf2: RXF2

0x28 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.

rxf3: RXF3

0x2c - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO.

irq: IRQ

0x30 - Interrupt request register. Write 1 to clear

irq_force: IRQ_FORCE

0x34 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.\n Note this is different to the INTF register: writing here affects PIO internal\n state. INTF just asserts the processor-facing IRQ signal for testing ISRs,\n and is not visible to the state machines.

input_sync_bypass: INPUT_SYNC_BYPASS

0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects\n PIO logic from metastabilities. This increases input delay, and for fast\n synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.\n Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes.

dbg_padout: DBG_PADOUT

0x3c - Read to sample the pad output values PIO is currently driving to the GPIOs.

dbg_padoe: DBG_PADOE

0x40 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs.

dbg_cfginfo: DBG_CFGINFO

0x44 - The PIO hardware has some free parameters that may vary between chip products.\n These should be provided in the chip datasheet, but are also exposed here.

instr_mem0: INSTR_MEM0

0x48 - Write-only access to instruction memory location 0

instr_mem1: INSTR_MEM1

0x4c - Write-only access to instruction memory location 1

instr_mem2: INSTR_MEM2

0x50 - Write-only access to instruction memory location 2

instr_mem3: INSTR_MEM3

0x54 - Write-only access to instruction memory location 3

instr_mem4: INSTR_MEM4

0x58 - Write-only access to instruction memory location 4

instr_mem5: INSTR_MEM5

0x5c - Write-only access to instruction memory location 5

instr_mem6: INSTR_MEM6

0x60 - Write-only access to instruction memory location 6

instr_mem7: INSTR_MEM7

0x64 - Write-only access to instruction memory location 7

instr_mem8: INSTR_MEM8

0x68 - Write-only access to instruction memory location 8

instr_mem9: INSTR_MEM9

0x6c - Write-only access to instruction memory location 9

instr_mem10: INSTR_MEM10

0x70 - Write-only access to instruction memory location 10

instr_mem11: INSTR_MEM11

0x74 - Write-only access to instruction memory location 11

instr_mem12: INSTR_MEM12

0x78 - Write-only access to instruction memory location 12

instr_mem13: INSTR_MEM13

0x7c - Write-only access to instruction memory location 13

instr_mem14: INSTR_MEM14

0x80 - Write-only access to instruction memory location 14

instr_mem15: INSTR_MEM15

0x84 - Write-only access to instruction memory location 15

instr_mem16: INSTR_MEM16

0x88 - Write-only access to instruction memory location 16

instr_mem17: INSTR_MEM17

0x8c - Write-only access to instruction memory location 17

instr_mem18: INSTR_MEM18

0x90 - Write-only access to instruction memory location 18

instr_mem19: INSTR_MEM19

0x94 - Write-only access to instruction memory location 19

instr_mem20: INSTR_MEM20

0x98 - Write-only access to instruction memory location 20

instr_mem21: INSTR_MEM21

0x9c - Write-only access to instruction memory location 21

instr_mem22: INSTR_MEM22

0xa0 - Write-only access to instruction memory location 22

instr_mem23: INSTR_MEM23

0xa4 - Write-only access to instruction memory location 23

instr_mem24: INSTR_MEM24

0xa8 - Write-only access to instruction memory location 24

instr_mem25: INSTR_MEM25

0xac - Write-only access to instruction memory location 25

instr_mem26: INSTR_MEM26

0xb0 - Write-only access to instruction memory location 26

instr_mem27: INSTR_MEM27

0xb4 - Write-only access to instruction memory location 27

instr_mem28: INSTR_MEM28

0xb8 - Write-only access to instruction memory location 28

instr_mem29: INSTR_MEM29

0xbc - Write-only access to instruction memory location 29

instr_mem30: INSTR_MEM30

0xc0 - Write-only access to instruction memory location 30

instr_mem31: INSTR_MEM31

0xc4 - Write-only access to instruction memory location 31

sm0_clkdiv: SM0_CLKDIV

0xc8 - Clock divider register for state machine 0\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

sm0_execctrl: SM0_EXECCTRL

0xcc - Execution/behavioural settings for state machine 0

sm0_shiftctrl: SM0_SHIFTCTRL

0xd0 - Control behaviour of the input/output shift registers for state machine 0

sm0_addr: SM0_ADDR

0xd4 - Current instruction address of state machine 0

sm0_instr: SM0_INSTR

0xd8 - Instruction currently being executed by state machine 0\n Write to execute an instruction immediately (including jumps) and then resume execution.

sm0_pinctrl: SM0_PINCTRL

0xdc - State machine pin control

sm1_clkdiv: SM1_CLKDIV

0xe0 - Clock divider register for state machine 1\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

sm1_execctrl: SM1_EXECCTRL

0xe4 - Execution/behavioural settings for state machine 1

sm1_shiftctrl: SM1_SHIFTCTRL

0xe8 - Control behaviour of the input/output shift registers for state machine 1

sm1_addr: SM1_ADDR

0xec - Current instruction address of state machine 1

sm1_instr: SM1_INSTR

0xf0 - Instruction currently being executed by state machine 1\n Write to execute an instruction immediately (including jumps) and then resume execution.

sm1_pinctrl: SM1_PINCTRL

0xf4 - State machine pin control

sm2_clkdiv: SM2_CLKDIV

0xf8 - Clock divider register for state machine 2\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

sm2_execctrl: SM2_EXECCTRL

0xfc - Execution/behavioural settings for state machine 2

sm2_shiftctrl: SM2_SHIFTCTRL

0x100 - Control behaviour of the input/output shift registers for state machine 2

sm2_addr: SM2_ADDR

0x104 - Current instruction address of state machine 2

sm2_instr: SM2_INSTR

0x108 - Instruction currently being executed by state machine 2\n Write to execute an instruction immediately (including jumps) and then resume execution.

sm2_pinctrl: SM2_PINCTRL

0x10c - State machine pin control

sm3_clkdiv: SM3_CLKDIV

0x110 - Clock divider register for state machine 3\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)

sm3_execctrl: SM3_EXECCTRL

0x114 - Execution/behavioural settings for state machine 3

sm3_shiftctrl: SM3_SHIFTCTRL

0x118 - Control behaviour of the input/output shift registers for state machine 3

sm3_addr: SM3_ADDR

0x11c - Current instruction address of state machine 3

sm3_instr: SM3_INSTR

0x120 - Instruction currently being executed by state machine 3\n Write to execute an instruction immediately (including jumps) and then resume execution.

sm3_pinctrl: SM3_PINCTRL

0x124 - State machine pin control

intr: INTR

0x128 - Raw Interrupts

irq0_inte: IRQ0_INTE

0x12c - Interrupt Enable for irq0

irq0_intf: IRQ0_INTF

0x130 - Interrupt Force for irq0

irq0_ints: IRQ0_INTS

0x134 - Interrupt status after masking & forcing for irq0

irq1_inte: IRQ1_INTE

0x138 - Interrupt Enable for irq1

irq1_intf: IRQ1_INTF

0x13c - Interrupt Force for irq1

irq1_ints: IRQ1_INTS

0x140 - Interrupt status after masking & forcing for irq1