[−][src]Module rp2040::adc
Control and data interface to SAR ADC
Modules
| cs | ADC Control and Status |
| div | Clock divider. If non-zero, CS_START_MANY will start conversions\n at regular intervals rather than back-to-back.\n The divider is reset when either of these fields are written.\n Total period is 1 + INT + FRAC / 256 |
| fcs | FIFO control and status |
| fifo | Conversion result FIFO |
| inte | Interrupt Enable |
| intf | Interrupt Force |
| intr | Raw Interrupts |
| ints | Interrupt status after masking & forcing |
| result | Result of most recent ADC conversion |
Structs
| RegisterBlock | Register block |
Type Definitions
| CS | ADC Control and Status |
| DIV | Clock divider. If non-zero, CS_START_MANY will start conversions\n at regular intervals rather than back-to-back.\n The divider is reset when either of these fields are written.\n Total period is 1 + INT + FRAC / 256 |
| FCS | FIFO control and status |
| FIFO | Conversion result FIFO |
| INTE | Interrupt Enable |
| INTF | Interrupt Force |
| INTR | Raw Interrupts |
| INTS | Interrupt status after masking & forcing |
| RESULT | Result of most recent ADC conversion |