Type Alias rp2040_pac::xip_ssi::ctrlr0::W

pub type W = W<CTRLR0_SPEC>;

Register CTRLR0 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn dfs(&mut self) -> DFS_W<'_, CTRLR0_SPEC>

Bits 0:3 - Data frame size

pub fn frf(&mut self) -> FRF_W<'_, CTRLR0_SPEC>

Bits 4:5 - Frame format

pub fn scph(&mut self) -> SCPH_W<'_, CTRLR0_SPEC>

Bit 6 - Serial clock phase

pub fn scpol(&mut self) -> SCPOL_W<'_, CTRLR0_SPEC>

Bit 7 - Serial clock polarity

pub fn tmod(&mut self) -> TMOD_W<'_, CTRLR0_SPEC>

Bits 8:9 - Transfer mode

pub fn slv_oe(&mut self) -> SLV_OE_W<'_, CTRLR0_SPEC>

Bit 10 - Slave output enable

pub fn srl(&mut self) -> SRL_W<'_, CTRLR0_SPEC>

Bit 11 - Shift register loop (test mode)

pub fn cfs(&mut self) -> CFS_W<'_, CTRLR0_SPEC>

Bits 12:15 - Control frame size
Value of n -> n+1 clocks per frame.

pub fn dfs_32(&mut self) -> DFS_32_W<'_, CTRLR0_SPEC>

Bits 16:20 - Data frame size in 32b transfer mode
Value of n -> n+1 clocks per frame.

pub fn spi_frf(&mut self) -> SPI_FRF_W<'_, CTRLR0_SPEC>

Bits 21:22 - SPI frame format

pub fn sste(&mut self) -> SSTE_W<'_, CTRLR0_SPEC>

Bit 24 - Slave select toggle enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual