Struct rp2040_pac::xip_ctrl::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn ctrl(&self) -> &CTRL

0x00 - Cache control

pub const fn flush(&self) -> &FLUSH

0x04 - Cache Flush control

pub const fn stat(&self) -> &STAT

0x08 - Cache Status

pub const fn ctr_hit(&self) -> &CTR_HIT

0x0c - Cache Hit counter
A 32 bit saturating counter that increments upon each cache hit,
i.e. when an XIP access is serviced directly from cached data.
Write any value to clear.

pub const fn ctr_acc(&self) -> &CTR_ACC

0x10 - Cache Access counter
A 32 bit saturating counter that increments upon each XIP access,
whether the cache is hit or not. This includes noncacheable accesses.
Write any value to clear.

pub const fn stream_addr(&self) -> &STREAM_ADDR

0x14 - FIFO stream address

pub const fn stream_ctr(&self) -> &STREAM_CTR

0x18 - FIFO stream control

pub const fn stream_fifo(&self) -> &STREAM_FIFO

0x1c - FIFO stream data
Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.