Struct rp2040_pac::syscfg::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn proc0_nmi_mask(&self) -> &PROC0_NMI_MASK

0x00 - Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ

pub const fn proc1_nmi_mask(&self) -> &PROC1_NMI_MASK

0x04 - Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ

pub const fn proc_config(&self) -> &PROC_CONFIG

0x08 - Configuration for processors

pub const fn proc_in_sync_bypass(&self) -> &PROC_IN_SYNC_BYPASS

0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.

pub const fn proc_in_sync_bypass_hi(&self) -> &PROC_IN_SYNC_BYPASS_HI

0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).

pub const fn dbgforce(&self) -> &DBGFORCE

0x14 - Directly control the SWD debug port of either processor

pub const fn mempowerdown(&self) -> &MEMPOWERDOWN

0x18 - Control power downs to memories. Set high to power down memories.
Use with extreme caution