Type Alias rp2040_pac::sio::interp0_ctrl_lane1::W

pub type W = W<INTERP0_CTRL_LANE1_SPEC>;

Register INTERP0_CTRL_LANE1 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn shift(&mut self) -> SHIFT_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bits 0:4 - Logical right-shift applied to accumulator before masking

pub fn mask_lsb(&mut self) -> MASK_LSB_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)

pub fn mask_msb(&mut self) -> MASK_MSB_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)
Setting MSB < LSB may cause chip to turn inside-out

pub fn signed(&mut self) -> SIGNED_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.

pub fn cross_input(&mut self) -> CROSS_INPUT_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bit 16 - If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

pub fn cross_result(&mut self) -> CROSS_RESULT_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bit 17 - If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

pub fn add_raw(&mut self) -> ADD_RAW_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.

pub fn force_msb(&mut self) -> FORCE_MSB_W<'_, INTERP0_CTRL_LANE1_SPEC>

Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.
No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
of pointers into flash or SRAM.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual