Struct rp2040_pac::sio::div_quotient::DIV_QUOTIENT_SPEC

pub struct DIV_QUOTIENT_SPEC;

Divider result quotient
The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
This register can be written to directly, for context save/restore purposes. This halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
REMAINDER, QUOTIENT if CSR_DIRTY is used.

You can read this register and get div_quotient::R. You can reset, write, write_with_zero this register using div_quotient::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for DIV_QUOTIENT_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for DIV_QUOTIENT_SPEC

reset() method sets DIV_QUOTIENT to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for DIV_QUOTIENT_SPEC

write(|w| ..) method takes div_quotient::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for DIV_QUOTIENT_SPEC

read() method returns div_quotient::R reader structure