Type Alias rp2040_pac::ppb::icsr::R

pub type R = R<ICSR_SPEC>;

Register ICSR reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn vectactive(&self) -> VECTACTIVE_R

Bits 0:8 - Active exception number field. Reset clears the VECTACTIVE field.

pub fn vectpending(&self) -> VECTPENDING_R

Bits 12:20 - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.

pub fn isrpending(&self) -> ISRPENDING_R

Bit 22 - External interrupt pending flag

pub fn isrpreempt(&self) -> ISRPREEMPT_R

Bit 23 - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.

pub fn pendstclr(&self) -> PENDSTCLR_R

Bit 25 - SysTick exception clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.

pub fn pendstset(&self) -> PENDSTSET_R

Bit 26 - SysTick exception set-pending bit.
Write:
0 = No effect.
1 = Changes SysTick exception state to pending.
Read:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.

pub fn pendsvclr(&self) -> PENDSVCLR_R

Bit 27 - PendSV clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the PendSV exception.

pub fn pendsvset(&self) -> PENDSVSET_R

Bit 28 - PendSV set-pending bit.
Write:
0 = No effect.
1 = Changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.

pub fn nmipendset(&self) -> NMIPENDSET_R

Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.
NMI set-pending bit.
Write:
0 = No effect.
1 = Changes NMI exception state to pending.
Read:
0 = NMI exception is not pending.
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally the processor enters the NMI
exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears
this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the
NMI signal is reasserted while the processor is executing that handler.