Type Alias rp2040_pac::pll_sys::cs::R

pub type R = R<CS_SPEC>;

Register CS reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn refdiv(&self) -> REFDIV_R

Bits 0:5 - Divides the PLL input reference clock.
Behaviour is undefined for div=0.
PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.

pub fn bypass(&self) -> BYPASS_R

Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.

pub fn lock(&self) -> LOCK_R

Bit 31 - PLL is locked