Type Alias rp2040_pac::dma::intr::R

pub type R = R<INTR_SPEC>;

Register INTR reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn intr(&self) -> INTR_R

Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.

Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.

This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.

It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.