Type Alias rp2040_pac::dma::ch::ch_ctrl_trig::TREQ_SEL_W

pub type TREQ_SEL_W<'a, REG> = FieldWriter<'a, REG, 6, TREQ_SEL_A>;

Field TREQ_SEL writer - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ

Aliased Type

struct TREQ_SEL_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> TREQ_SEL_W<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn pio0_tx0(self) -> &'a mut W<REG>

Select PIO0’s TX FIFO 0 as TREQ

pub fn pio0_tx1(self) -> &'a mut W<REG>

Select PIO0’s TX FIFO 1 as TREQ

pub fn pio0_tx2(self) -> &'a mut W<REG>

Select PIO0’s TX FIFO 2 as TREQ

pub fn pio0_tx3(self) -> &'a mut W<REG>

Select PIO0’s TX FIFO 3 as TREQ

pub fn pio0_rx0(self) -> &'a mut W<REG>

Select PIO0’s RX FIFO 0 as TREQ

pub fn pio0_rx1(self) -> &'a mut W<REG>

Select PIO0’s RX FIFO 1 as TREQ

pub fn pio0_rx2(self) -> &'a mut W<REG>

Select PIO0’s RX FIFO 2 as TREQ

pub fn pio0_rx3(self) -> &'a mut W<REG>

Select PIO0’s RX FIFO 3 as TREQ

pub fn pio1_tx0(self) -> &'a mut W<REG>

Select PIO1’s TX FIFO 0 as TREQ

pub fn pio1_tx1(self) -> &'a mut W<REG>

Select PIO1’s TX FIFO 1 as TREQ

pub fn pio1_tx2(self) -> &'a mut W<REG>

Select PIO1’s TX FIFO 2 as TREQ

pub fn pio1_tx3(self) -> &'a mut W<REG>

Select PIO1’s TX FIFO 3 as TREQ

pub fn pio1_rx0(self) -> &'a mut W<REG>

Select PIO1’s RX FIFO 0 as TREQ

pub fn pio1_rx1(self) -> &'a mut W<REG>

Select PIO1’s RX FIFO 1 as TREQ

pub fn pio1_rx2(self) -> &'a mut W<REG>

Select PIO1’s RX FIFO 2 as TREQ

pub fn pio1_rx3(self) -> &'a mut W<REG>

Select PIO1’s RX FIFO 3 as TREQ

pub fn spi0_tx(self) -> &'a mut W<REG>

Select SPI0’s TX FIFO as TREQ

pub fn spi0_rx(self) -> &'a mut W<REG>

Select SPI0’s RX FIFO as TREQ

pub fn spi1_tx(self) -> &'a mut W<REG>

Select SPI1’s TX FIFO as TREQ

pub fn spi1_rx(self) -> &'a mut W<REG>

Select SPI1’s RX FIFO as TREQ

pub fn uart0_tx(self) -> &'a mut W<REG>

Select UART0’s TX FIFO as TREQ

pub fn uart0_rx(self) -> &'a mut W<REG>

Select UART0’s RX FIFO as TREQ

pub fn uart1_tx(self) -> &'a mut W<REG>

Select UART1’s TX FIFO as TREQ

pub fn uart1_rx(self) -> &'a mut W<REG>

Select UART1’s RX FIFO as TREQ

pub fn pwm_wrap0(self) -> &'a mut W<REG>

Select PWM Counter 0’s Wrap Value as TREQ

pub fn pwm_wrap1(self) -> &'a mut W<REG>

Select PWM Counter 1’s Wrap Value as TREQ

pub fn pwm_wrap2(self) -> &'a mut W<REG>

Select PWM Counter 2’s Wrap Value as TREQ

pub fn pwm_wrap3(self) -> &'a mut W<REG>

Select PWM Counter 3’s Wrap Value as TREQ

pub fn pwm_wrap4(self) -> &'a mut W<REG>

Select PWM Counter 4’s Wrap Value as TREQ

pub fn pwm_wrap5(self) -> &'a mut W<REG>

Select PWM Counter 5’s Wrap Value as TREQ

pub fn pwm_wrap6(self) -> &'a mut W<REG>

Select PWM Counter 6’s Wrap Value as TREQ

pub fn pwm_wrap7(self) -> &'a mut W<REG>

Select PWM Counter 7’s Wrap Value as TREQ

pub fn i2c0_tx(self) -> &'a mut W<REG>

Select I2C0’s TX FIFO as TREQ

pub fn i2c0_rx(self) -> &'a mut W<REG>

Select I2C0’s RX FIFO as TREQ

pub fn i2c1_tx(self) -> &'a mut W<REG>

Select I2C1’s TX FIFO as TREQ

pub fn i2c1_rx(self) -> &'a mut W<REG>

Select I2C1’s RX FIFO as TREQ

pub fn adc(self) -> &'a mut W<REG>

Select the ADC as TREQ

pub fn xip_stream(self) -> &'a mut W<REG>

Select the XIP Streaming FIFO as TREQ

pub fn xip_ssitx(self) -> &'a mut W<REG>

Select the XIP SSI TX FIFO as TREQ

pub fn xip_ssirx(self) -> &'a mut W<REG>

Select the XIP SSI RX FIFO as TREQ

pub fn timer0(self) -> &'a mut W<REG>

Select Timer 0 as TREQ

pub fn timer1(self) -> &'a mut W<REG>

Select Timer 1 as TREQ

pub fn timer2(self) -> &'a mut W<REG>

Select Timer 2 as TREQ (Optional)

pub fn timer3(self) -> &'a mut W<REG>

Select Timer 3 as TREQ (Optional)

pub fn permanent(self) -> &'a mut W<REG>

Permanent request, for unpaced transfers.