Struct rp2040_pac::clocks::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn clk_gpout0_ctrl(&self) -> &CLK_GPOUT0_CTRL

0x00 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_gpout0_div(&self) -> &CLK_GPOUT0_DIV

0x04 - Clock divisor, can be changed on-the-fly

pub const fn clk_gpout0_selected(&self) -> &CLK_GPOUT0_SELECTED

0x08 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_gpout1_ctrl(&self) -> &CLK_GPOUT1_CTRL

0x0c - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_gpout1_div(&self) -> &CLK_GPOUT1_DIV

0x10 - Clock divisor, can be changed on-the-fly

pub const fn clk_gpout1_selected(&self) -> &CLK_GPOUT1_SELECTED

0x14 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_gpout2_ctrl(&self) -> &CLK_GPOUT2_CTRL

0x18 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_gpout2_div(&self) -> &CLK_GPOUT2_DIV

0x1c - Clock divisor, can be changed on-the-fly

pub const fn clk_gpout2_selected(&self) -> &CLK_GPOUT2_SELECTED

0x20 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_gpout3_ctrl(&self) -> &CLK_GPOUT3_CTRL

0x24 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_gpout3_div(&self) -> &CLK_GPOUT3_DIV

0x28 - Clock divisor, can be changed on-the-fly

pub const fn clk_gpout3_selected(&self) -> &CLK_GPOUT3_SELECTED

0x2c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_ref_ctrl(&self) -> &CLK_REF_CTRL

0x30 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_ref_div(&self) -> &CLK_REF_DIV

0x34 - Clock divisor, can be changed on-the-fly

pub const fn clk_ref_selected(&self) -> &CLK_REF_SELECTED

0x38 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub const fn clk_sys_ctrl(&self) -> &CLK_SYS_CTRL

0x3c - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_sys_div(&self) -> &CLK_SYS_DIV

0x40 - Clock divisor, can be changed on-the-fly

pub const fn clk_sys_selected(&self) -> &CLK_SYS_SELECTED

0x44 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub const fn clk_peri_ctrl(&self) -> &CLK_PERI_CTRL

0x48 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_peri_selected(&self) -> &CLK_PERI_SELECTED

0x50 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_usb_ctrl(&self) -> &CLK_USB_CTRL

0x54 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_usb_div(&self) -> &CLK_USB_DIV

0x58 - Clock divisor, can be changed on-the-fly

pub const fn clk_usb_selected(&self) -> &CLK_USB_SELECTED

0x5c - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_adc_ctrl(&self) -> &CLK_ADC_CTRL

0x60 - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_adc_div(&self) -> &CLK_ADC_DIV

0x64 - Clock divisor, can be changed on-the-fly

pub const fn clk_adc_selected(&self) -> &CLK_ADC_SELECTED

0x68 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_rtc_ctrl(&self) -> &CLK_RTC_CTRL

0x6c - Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_rtc_div(&self) -> &CLK_RTC_DIV

0x70 - Clock divisor, can be changed on-the-fly

pub const fn clk_rtc_selected(&self) -> &CLK_RTC_SELECTED

0x74 - Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_sys_resus_ctrl(&self) -> &CLK_SYS_RESUS_CTRL

0x78 -

pub const fn clk_sys_resus_status(&self) -> &CLK_SYS_RESUS_STATUS

0x7c -

pub const fn fc0_ref_khz(&self) -> &FC0_REF_KHZ

0x80 - Reference clock frequency in kHz

pub const fn fc0_min_khz(&self) -> &FC0_MIN_KHZ

0x84 - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags

pub const fn fc0_max_khz(&self) -> &FC0_MAX_KHZ

0x88 - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags

pub const fn fc0_delay(&self) -> &FC0_DELAY

0x8c - Delays the start of frequency counting to allow the mux to settle
Delay is measured in multiples of the reference clock period

pub const fn fc0_interval(&self) -> &FC0_INTERVAL

0x90 - The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval
The default gives a test interval of 250us

pub const fn fc0_src(&self) -> &FC0_SRC

0x94 - Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count

pub const fn fc0_status(&self) -> &FC0_STATUS

0x98 - Frequency counter status

pub const fn fc0_result(&self) -> &FC0_RESULT

0x9c - Result of frequency measurement, only valid when status_done=1

pub const fn wake_en0(&self) -> &WAKE_EN0

0xa0 - enable clock in wake mode

pub const fn wake_en1(&self) -> &WAKE_EN1

0xa4 - enable clock in wake mode

pub const fn sleep_en0(&self) -> &SLEEP_EN0

0xa8 - enable clock in sleep mode

pub const fn sleep_en1(&self) -> &SLEEP_EN1

0xac - enable clock in sleep mode

pub const fn enabled0(&self) -> &ENABLED0

0xb0 - indicates the state of the clock enable

pub const fn enabled1(&self) -> &ENABLED1

0xb4 - indicates the state of the clock enable

pub const fn intr(&self) -> &INTR

0xb8 - Raw Interrupts

pub const fn inte(&self) -> &INTE

0xbc - Interrupt Enable

pub const fn intf(&self) -> &INTF

0xc0 - Interrupt Force

pub const fn ints(&self) -> &INTS

0xc4 - Interrupt status after masking & forcing