Type Alias rp2040_pac::clocks::clk_gpout3_ctrl::R

pub type R = R<CLK_GPOUT3_CTRL_SPEC>;

Register CLK_GPOUT3_CTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn auxsrc(&self) -> AUXSRC_R

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

pub fn kill(&self) -> KILL_R

Bit 10 - Asynchronously kills the clock generator

pub fn enable(&self) -> ENABLE_R

Bit 11 - Starts and stops the clock generator cleanly

pub fn dc50(&self) -> DC50_R

Bit 12 - Enables duty cycle correction for odd divisors

pub fn phase(&self) -> PHASE_R

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect

pub fn nudge(&self) -> NUDGE_R

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time