Type Alias rp2040_pac::clocks::clk_gpout2_ctrl::W

pub type W = W<CLK_GPOUT2_CTRL_SPEC>;

Register CLK_GPOUT2_CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn auxsrc(&mut self) -> AUXSRC_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bits 5:8 - Selects the auxiliary clock source, will glitch when switching

pub fn kill(&mut self) -> KILL_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bit 10 - Asynchronously kills the clock generator

pub fn enable(&mut self) -> ENABLE_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bit 11 - Starts and stops the clock generator cleanly

pub fn dc50(&mut self) -> DC50_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bit 12 - Enables duty cycle correction for odd divisors

pub fn phase(&mut self) -> PHASE_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock
This must be set before the clock is enabled to have any effect

pub fn nudge(&mut self) -> NUDGE_W<'_, CLK_GPOUT2_CTRL_SPEC>

Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock
This can be done at any time

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual