Module rp2040_pac::xip_ssi

DW_apb_ssi has the following features:

• APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
• APB3 and APB4 protocol support.
• Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.
• Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.
• Programmable Dual/Quad/Octal SPI support in Master Mode.
• Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
• Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
• eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
• DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
• Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
• Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.
• Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
• Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
• Programmable features:

• Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
• Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
• Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.

• Configured features:

• FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.
• 1 slave select output.
• Hardware slave-select – Dedicated hardware slave-select line.
• Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
• Interrupt polarity – active high interrupt lines.
• Serial clock polarity – low serial-clock polarity directly after reset.
• Serial clock phase – capture on first edge of serial-clock directly after reset.

Modules

baudr

Baud rate

ctrlr0

Control register 0

ctrlr1

Master Control register 1

dmacr

DMA control

dmardlr

DMA RX data level

dmatdlr

DMA TX data level

dr0

Data Register 0 (of 36)

icr

Interrupt clear

idr

Identification register

imr

Interrupt mask

isr

Interrupt status

msticr

Multi-master interrupt clear

mwcr

Microwire Control

risr

Raw interrupt status

rx_sample_dly

RX sample delay

rxflr

RX FIFO level

rxftlr

RX FIFO threshold level

rxoicr

RX FIFO overflow interrupt clear

rxuicr

RX FIFO underflow interrupt clear

ser

Slave enable

spi_ctrlr0

SPI control

sr

Status register

ssi_version_id

Version ID

ssienr

SSI Enable

txd_drive_edge

TX drive edge

txflr

TX FIFO level

txftlr

TX FIFO threshold level

txoicr

TX FIFO overflow interrupt clear

Structs

RegisterBlock

Register block

Type Definitions

BAUDR

BAUDR register accessor: an alias for Reg<BAUDR_SPEC>

CTRLR0

CTRLR0 register accessor: an alias for Reg<CTRLR0_SPEC>

CTRLR1

CTRLR1 register accessor: an alias for Reg<CTRLR1_SPEC>

DMACR

DMACR register accessor: an alias for Reg<DMACR_SPEC>

DMARDLR

DMARDLR register accessor: an alias for Reg<DMARDLR_SPEC>

DMATDLR

DMATDLR register accessor: an alias for Reg<DMATDLR_SPEC>

DR0

DR0 register accessor: an alias for Reg<DR0_SPEC>

ICR

ICR register accessor: an alias for Reg<ICR_SPEC>

IDR

IDR register accessor: an alias for Reg<IDR_SPEC>

IMR

IMR register accessor: an alias for Reg<IMR_SPEC>

ISR

ISR register accessor: an alias for Reg<ISR_SPEC>

MSTICR

MSTICR register accessor: an alias for Reg<MSTICR_SPEC>

MWCR

MWCR register accessor: an alias for Reg<MWCR_SPEC>

RISR

RISR register accessor: an alias for Reg<RISR_SPEC>

RXFLR

RXFLR register accessor: an alias for Reg<RXFLR_SPEC>

RXFTLR

RXFTLR register accessor: an alias for Reg<RXFTLR_SPEC>

RXOICR

RXOICR register accessor: an alias for Reg<RXOICR_SPEC>

RXUICR

RXUICR register accessor: an alias for Reg<RXUICR_SPEC>

RX_SAMPLE_DLY

RX_SAMPLE_DLY register accessor: an alias for Reg<RX_SAMPLE_DLY_SPEC>

SER

SER register accessor: an alias for Reg<SER_SPEC>

SPI_CTRLR0

SPI_CTRLR0 register accessor: an alias for Reg<SPI_CTRLR0_SPEC>

SR

SR register accessor: an alias for Reg<SR_SPEC>

SSIENR

SSIENR register accessor: an alias for Reg<SSIENR_SPEC>

SSI_VERSION_ID

SSI_VERSION_ID register accessor: an alias for Reg<SSI_VERSION_ID_SPEC>

TXD_DRIVE_EDGE

TXD_DRIVE_EDGE register accessor: an alias for Reg<TXD_DRIVE_EDGE_SPEC>

TXFLR

TXFLR register accessor: an alias for Reg<TXFLR_SPEC>

TXFTLR

TXFTLR register accessor: an alias for Reg<TXFTLR_SPEC>

TXOICR

TXOICR register accessor: an alias for Reg<TXOICR_SPEC>