Module rp2040_pac::sio [−][src]
Expand description
Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.
Modules
Processor core identifier
Value is 0 when read from processor core 0, and 1 when read from processor core 1.
Control and status register for divider.
Divider result quotient
The result of DIVIDEND / DIVISOR (division). Contents undefined while CSR_READY is low.
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
This register can be written to directly, for context save/restore purposes. This halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
REMAINDER, QUOTIENT if CSR_DIRTY is used.
Divider result remainder
The result of DIVIDEND % DIVISOR (modulo). Contents undefined while CSR_READY is low.
For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
This register can be written to directly, for context save/restore purposes. This halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
Divider signed dividend
The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
Divider signed divisor
The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
Divider unsigned dividend
Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
unsigned calculation, and the S alias starts a signed calculation.
Divider unsigned divisor
Write to the DIVISOR operand of the divider, i.e. the q in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
unsigned calculation, and the S alias starts a signed calculation.
Read access to this core’s RX FIFO
Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
Write access to this core’s TX FIFO
Input value for QSPI pins
QSPI output enable
QSPI output enable clear
QSPI output enable set
QSPI output enable XOR
QSPI output value
QSPI output value clear
QSPI output value set
QSPI output value XOR
Input value for GPIO pins
GPIO output enable
GPIO output enable clear
GPIO output enable set
GPIO output enable XOR
GPIO output value
GPIO output value clear
GPIO output value set
GPIO output value XOR
Read/write access to accumulator 0
Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
Read/write access to accumulator 1
Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
Read/write access to BASE0 register.
Read/write access to BASE1 register.
Read/write access to BASE2 register.
On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
Control register for lane 0
Control register for lane 1
Read FULL result, without altering any internal state (PEEK).
Read LANE0 result, without altering any internal state (PEEK).
Read LANE1 result, without altering any internal state (PEEK).
Read FULL result, and simultaneously write lane results to both accumulators (POP).
Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
Read/write access to accumulator 0
Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
Read/write access to accumulator 1
Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
Read/write access to BASE0 register.
Read/write access to BASE1 register.
Read/write access to BASE2 register.
On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
Control register for lane 0
Control register for lane 1
Read FULL result, without altering any internal state (PEEK).
Read LANE0 result, without altering any internal state (PEEK).
Read LANE1 result, without altering any internal state (PEEK).
Read FULL result, and simultaneously write lane results to both accumulators (POP).
Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Reading from a spinlock address will:
Spinlock state
A bitmap containing the state of all 32 spinlocks (1=locked).
Mainly intended for debugging.
Structs
Register block
Type Definitions
CPUID register accessor: an alias for Reg<CPUID_SPEC>
DIV_CSR register accessor: an alias for Reg<DIV_CSR_SPEC>
DIV_QUOTIENT register accessor: an alias for Reg<DIV_QUOTIENT_SPEC>
DIV_REMAINDER register accessor: an alias for Reg<DIV_REMAINDER_SPEC>
DIV_SDIVIDEND register accessor: an alias for Reg<DIV_SDIVIDEND_SPEC>
DIV_SDIVISOR register accessor: an alias for Reg<DIV_SDIVISOR_SPEC>
DIV_UDIVIDEND register accessor: an alias for Reg<DIV_UDIVIDEND_SPEC>
DIV_UDIVISOR register accessor: an alias for Reg<DIV_UDIVISOR_SPEC>
FIFO_RD register accessor: an alias for Reg<FIFO_RD_SPEC>
FIFO_ST register accessor: an alias for Reg<FIFO_ST_SPEC>
FIFO_WR register accessor: an alias for Reg<FIFO_WR_SPEC>
GPIO_HI_IN register accessor: an alias for Reg<GPIO_HI_IN_SPEC>
GPIO_HI_OE register accessor: an alias for Reg<GPIO_HI_OE_SPEC>
GPIO_HI_OE_CLR register accessor: an alias for Reg<GPIO_HI_OE_CLR_SPEC>
GPIO_HI_OE_SET register accessor: an alias for Reg<GPIO_HI_OE_SET_SPEC>
GPIO_HI_OE_XOR register accessor: an alias for Reg<GPIO_HI_OE_XOR_SPEC>
GPIO_HI_OUT register accessor: an alias for Reg<GPIO_HI_OUT_SPEC>
GPIO_HI_OUT_CLR register accessor: an alias for Reg<GPIO_HI_OUT_CLR_SPEC>
GPIO_HI_OUT_SET register accessor: an alias for Reg<GPIO_HI_OUT_SET_SPEC>
GPIO_HI_OUT_XOR register accessor: an alias for Reg<GPIO_HI_OUT_XOR_SPEC>
GPIO_IN register accessor: an alias for Reg<GPIO_IN_SPEC>
GPIO_OE register accessor: an alias for Reg<GPIO_OE_SPEC>
GPIO_OE_CLR register accessor: an alias for Reg<GPIO_OE_CLR_SPEC>
GPIO_OE_SET register accessor: an alias for Reg<GPIO_OE_SET_SPEC>
GPIO_OE_XOR register accessor: an alias for Reg<GPIO_OE_XOR_SPEC>
GPIO_OUT register accessor: an alias for Reg<GPIO_OUT_SPEC>
GPIO_OUT_CLR register accessor: an alias for Reg<GPIO_OUT_CLR_SPEC>
GPIO_OUT_SET register accessor: an alias for Reg<GPIO_OUT_SET_SPEC>
GPIO_OUT_XOR register accessor: an alias for Reg<GPIO_OUT_XOR_SPEC>
INTERP0_ACCUM0 register accessor: an alias for Reg<INTERP0_ACCUM0_SPEC>
INTERP0_ACCUM0_ADD register accessor: an alias for Reg<INTERP0_ACCUM0_ADD_SPEC>
INTERP0_ACCUM1 register accessor: an alias for Reg<INTERP0_ACCUM1_SPEC>
INTERP0_ACCUM1_ADD register accessor: an alias for Reg<INTERP0_ACCUM1_ADD_SPEC>
INTERP0_BASE0 register accessor: an alias for Reg<INTERP0_BASE0_SPEC>
INTERP0_BASE1 register accessor: an alias for Reg<INTERP0_BASE1_SPEC>
INTERP0_BASE2 register accessor: an alias for Reg<INTERP0_BASE2_SPEC>
INTERP0_BASE_1AND0 register accessor: an alias for Reg<INTERP0_BASE_1AND0_SPEC>
INTERP0_CTRL_LANE0 register accessor: an alias for Reg<INTERP0_CTRL_LANE0_SPEC>
INTERP0_CTRL_LANE1 register accessor: an alias for Reg<INTERP0_CTRL_LANE1_SPEC>
INTERP0_PEEK_FULL register accessor: an alias for Reg<INTERP0_PEEK_FULL_SPEC>
INTERP0_PEEK_LANE0 register accessor: an alias for Reg<INTERP0_PEEK_LANE0_SPEC>
INTERP0_PEEK_LANE1 register accessor: an alias for Reg<INTERP0_PEEK_LANE1_SPEC>
INTERP0_POP_FULL register accessor: an alias for Reg<INTERP0_POP_FULL_SPEC>
INTERP0_POP_LANE0 register accessor: an alias for Reg<INTERP0_POP_LANE0_SPEC>
INTERP0_POP_LANE1 register accessor: an alias for Reg<INTERP0_POP_LANE1_SPEC>
INTERP1_ACCUM0 register accessor: an alias for Reg<INTERP1_ACCUM0_SPEC>
INTERP1_ACCUM0_ADD register accessor: an alias for Reg<INTERP1_ACCUM0_ADD_SPEC>
INTERP1_ACCUM1 register accessor: an alias for Reg<INTERP1_ACCUM1_SPEC>
INTERP1_ACCUM1_ADD register accessor: an alias for Reg<INTERP1_ACCUM1_ADD_SPEC>
INTERP1_BASE0 register accessor: an alias for Reg<INTERP1_BASE0_SPEC>
INTERP1_BASE1 register accessor: an alias for Reg<INTERP1_BASE1_SPEC>
INTERP1_BASE2 register accessor: an alias for Reg<INTERP1_BASE2_SPEC>
INTERP1_BASE_1AND0 register accessor: an alias for Reg<INTERP1_BASE_1AND0_SPEC>
INTERP1_CTRL_LANE0 register accessor: an alias for Reg<INTERP1_CTRL_LANE0_SPEC>
INTERP1_CTRL_LANE1 register accessor: an alias for Reg<INTERP1_CTRL_LANE1_SPEC>
INTERP1_PEEK_FULL register accessor: an alias for Reg<INTERP1_PEEK_FULL_SPEC>
INTERP1_PEEK_LANE0 register accessor: an alias for Reg<INTERP1_PEEK_LANE0_SPEC>
INTERP1_PEEK_LANE1 register accessor: an alias for Reg<INTERP1_PEEK_LANE1_SPEC>
INTERP1_POP_FULL register accessor: an alias for Reg<INTERP1_POP_FULL_SPEC>
INTERP1_POP_LANE0 register accessor: an alias for Reg<INTERP1_POP_LANE0_SPEC>
INTERP1_POP_LANE1 register accessor: an alias for Reg<INTERP1_POP_LANE1_SPEC>
SPINLOCK0 register accessor: an alias for Reg<SPINLOCK0_SPEC>
SPINLOCK1 register accessor: an alias for Reg<SPINLOCK1_SPEC>
SPINLOCK2 register accessor: an alias for Reg<SPINLOCK2_SPEC>
SPINLOCK3 register accessor: an alias for Reg<SPINLOCK3_SPEC>
SPINLOCK4 register accessor: an alias for Reg<SPINLOCK4_SPEC>
SPINLOCK5 register accessor: an alias for Reg<SPINLOCK5_SPEC>
SPINLOCK6 register accessor: an alias for Reg<SPINLOCK6_SPEC>
SPINLOCK7 register accessor: an alias for Reg<SPINLOCK7_SPEC>
SPINLOCK8 register accessor: an alias for Reg<SPINLOCK8_SPEC>
SPINLOCK9 register accessor: an alias for Reg<SPINLOCK9_SPEC>
SPINLOCK10 register accessor: an alias for Reg<SPINLOCK10_SPEC>
SPINLOCK11 register accessor: an alias for Reg<SPINLOCK11_SPEC>
SPINLOCK12 register accessor: an alias for Reg<SPINLOCK12_SPEC>
SPINLOCK13 register accessor: an alias for Reg<SPINLOCK13_SPEC>
SPINLOCK14 register accessor: an alias for Reg<SPINLOCK14_SPEC>
SPINLOCK15 register accessor: an alias for Reg<SPINLOCK15_SPEC>
SPINLOCK16 register accessor: an alias for Reg<SPINLOCK16_SPEC>
SPINLOCK17 register accessor: an alias for Reg<SPINLOCK17_SPEC>
SPINLOCK18 register accessor: an alias for Reg<SPINLOCK18_SPEC>
SPINLOCK19 register accessor: an alias for Reg<SPINLOCK19_SPEC>
SPINLOCK20 register accessor: an alias for Reg<SPINLOCK20_SPEC>
SPINLOCK21 register accessor: an alias for Reg<SPINLOCK21_SPEC>
SPINLOCK22 register accessor: an alias for Reg<SPINLOCK22_SPEC>
SPINLOCK23 register accessor: an alias for Reg<SPINLOCK23_SPEC>
SPINLOCK24 register accessor: an alias for Reg<SPINLOCK24_SPEC>
SPINLOCK25 register accessor: an alias for Reg<SPINLOCK25_SPEC>
SPINLOCK26 register accessor: an alias for Reg<SPINLOCK26_SPEC>
SPINLOCK27 register accessor: an alias for Reg<SPINLOCK27_SPEC>
SPINLOCK28 register accessor: an alias for Reg<SPINLOCK28_SPEC>
SPINLOCK29 register accessor: an alias for Reg<SPINLOCK29_SPEC>
SPINLOCK30 register accessor: an alias for Reg<SPINLOCK30_SPEC>
SPINLOCK31 register accessor: an alias for Reg<SPINLOCK31_SPEC>
SPINLOCK_ST register accessor: an alias for Reg<SPINLOCK_ST_SPEC>