Module rp2040_pac::dma [−][src]
Expand description
DMA with separate read and write masters
Modules
Register block Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
Abort an in-progress transfer sequence on one or more channels
Debug RAF, WAF, TDF levels
Interrupt Enables for IRQ 0
Interrupt Enables for IRQ 1
Force Interrupts
Force Interrupts for IRQ 1
Interrupt Status (raw)
Interrupt Status for IRQ 0
Interrupt Status (masked) for IRQ 1
Trigger one or more channels simultaneously
The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
Sniffer Control
Data accumulator for sniff hardware
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
Structs
Type Definitions
CH0_DBG_CTDREQ register accessor: an alias for Reg<CH0_DBG_CTDREQ_SPEC>
CH0_DBG_TCR register accessor: an alias for Reg<CH0_DBG_TCR_SPEC>
CH1_DBG_CTDREQ register accessor: an alias for Reg<CH1_DBG_CTDREQ_SPEC>
CH1_DBG_TCR register accessor: an alias for Reg<CH1_DBG_TCR_SPEC>
CH2_DBG_CTDREQ register accessor: an alias for Reg<CH2_DBG_CTDREQ_SPEC>
CH2_DBG_TCR register accessor: an alias for Reg<CH2_DBG_TCR_SPEC>
CH3_DBG_CTDREQ register accessor: an alias for Reg<CH3_DBG_CTDREQ_SPEC>
CH3_DBG_TCR register accessor: an alias for Reg<CH3_DBG_TCR_SPEC>
CH4_DBG_CTDREQ register accessor: an alias for Reg<CH4_DBG_CTDREQ_SPEC>
CH4_DBG_TCR register accessor: an alias for Reg<CH4_DBG_TCR_SPEC>
CH5_DBG_CTDREQ register accessor: an alias for Reg<CH5_DBG_CTDREQ_SPEC>
CH5_DBG_TCR register accessor: an alias for Reg<CH5_DBG_TCR_SPEC>
CH6_DBG_CTDREQ register accessor: an alias for Reg<CH6_DBG_CTDREQ_SPEC>
CH6_DBG_TCR register accessor: an alias for Reg<CH6_DBG_TCR_SPEC>
CH7_DBG_CTDREQ register accessor: an alias for Reg<CH7_DBG_CTDREQ_SPEC>
CH7_DBG_TCR register accessor: an alias for Reg<CH7_DBG_TCR_SPEC>
CH8_DBG_CTDREQ register accessor: an alias for Reg<CH8_DBG_CTDREQ_SPEC>
CH8_DBG_TCR register accessor: an alias for Reg<CH8_DBG_TCR_SPEC>
CH9_DBG_CTDREQ register accessor: an alias for Reg<CH9_DBG_CTDREQ_SPEC>
CH9_DBG_TCR register accessor: an alias for Reg<CH9_DBG_TCR_SPEC>
CH10_DBG_CTDREQ register accessor: an alias for Reg<CH10_DBG_CTDREQ_SPEC>
CH10_DBG_TCR register accessor: an alias for Reg<CH10_DBG_TCR_SPEC>
CH11_DBG_CTDREQ register accessor: an alias for Reg<CH11_DBG_CTDREQ_SPEC>
CH11_DBG_TCR register accessor: an alias for Reg<CH11_DBG_TCR_SPEC>
CHAN_ABORT register accessor: an alias for Reg<CHAN_ABORT_SPEC>
FIFO_LEVELS register accessor: an alias for Reg<FIFO_LEVELS_SPEC>
INTE0 register accessor: an alias for Reg<INTE0_SPEC>
INTE1 register accessor: an alias for Reg<INTE1_SPEC>
INTF0 register accessor: an alias for Reg<INTF0_SPEC>
INTF1 register accessor: an alias for Reg<INTF1_SPEC>
INTR register accessor: an alias for Reg<INTR_SPEC>
INTS0 register accessor: an alias for Reg<INTS0_SPEC>
INTS1 register accessor: an alias for Reg<INTS1_SPEC>
MULTI_CHAN_TRIGGER register accessor: an alias for Reg<MULTI_CHAN_TRIGGER_SPEC>
N_CHANNELS register accessor: an alias for Reg<N_CHANNELS_SPEC>
SNIFF_CTRL register accessor: an alias for Reg<SNIFF_CTRL_SPEC>
SNIFF_DATA register accessor: an alias for Reg<SNIFF_DATA_SPEC>
TIMER0 register accessor: an alias for Reg<TIMER0_SPEC>
TIMER1 register accessor: an alias for Reg<TIMER1_SPEC>
TIMER2 register accessor: an alias for Reg<TIMER2_SPEC>
TIMER3 register accessor: an alias for Reg<TIMER3_SPEC>