Struct rp2040_pac::pll_sys::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cs: CS,
    pub pwr: PWR,
    pub fbdiv_int: FBDIV_INT,
    pub prim: PRIM,
}

Register block

Fields

cs: CS

0x00 - Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz, max=800MHz\n Feedback divider min=16, max=320\n VCO frequency min=400MHz, max=1600MHz

pwr: PWR

0x04 - Controls the PLL power modes.

fbdiv_int: FBDIV_INT

0x08 - Feedback divisor\n (note: this PLL does not support fractional division)

prim: PRIM

0x0c - Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2