rp2040_hal

Module dma

Source
Expand description

Direct memory access (DMA).

The DMA unit of the RP2040 seems very simplistic at first when compared to other MCUs. For example, the individual DMA channels do not support chaining multiple buffers. However, within certain limits, the DMA engine supports a wide range of transfer and buffer types, often by combining multiple DMA channels:

  • Simple RX/TX transfers filling a single buffer or transferring data from one peripheral to another.
  • RX/TX transfers that use multiple chained buffers: These transfers require two channels to be combined, where the first DMA channel configures the second DMA channel. An example for this transfer type can be found in the datasheet.
  • Repeated transfers from/to a set of buffers: By allocating one channel per buffer and chaining the channels together, continuous transfers to a set of ring buffers can be achieved. Note, however, that the MCU manually needs to reconfigure the DMA units unless the buffer addresses and sizes are aligned, in which case the ring buffer functionality of the DMA engine can be used. Even then, however, at least two DMA channels are required as a channel cannot be chained to itself.

This API tries to provide three types of buffers: Single buffers, double-buffered transfers where the user can specify the next buffer while the previous is being transferred, and automatic continuous ring buffers consisting of two aligned buffers being read or written alternatingly.

Modules§

bidirectional
Bidirectional DMA transfers
double_buffer
Double-buffered DMA Transfers
single_buffer
Single-buffered or peripheral-peripheral DMA Transfers

Structs§

Byte
DMA transfer in bytes (u8)
CH0
DMA channel identifier.
CH1
DMA channel identifier.
CH2
DMA channel identifier.
CH3
DMA channel identifier.
CH4
DMA channel identifier.
CH5
DMA channel identifier.
CH6
DMA channel identifier.
CH7
DMA channel identifier.
CH8
DMA channel identifier.
CH9
DMA channel identifier.
CH10
DMA channel identifier.
CH11
DMA channel identifier.
Channel
DMA channel.
Channels
Set of DMA channels.
DynChannels
Set of DMA channels with runtime ownership.
HalfWord
DMA transfer in half words (u16)
Word
DMA transfer in words (u32)

Enums§

DMAError
Error during DMA configuration.
Pace
Pacing for DMA transfers.

Traits§

ChannelIndex
DMA channel identifier.
DMAExt
DMA unit.
EndlessReadTarget
Marker which signals that rx_address_count() can be called multiple times.
EndlessWriteTarget
Marker which signals that tx_address_count() can be called multiple times.
ReadTarget
Trait which is implemented by anything that can be read via DMA.
SingleChannel
Trait which implements low-level functionality for transfers using a single DMA channel.
TransferSize
Constraint on transfer size types
WriteTarget
Trait which is implemented by anything that can be written via DMA.