Crate rp2040_emu 

RP2040 emulator library.

Phase 5.A fills in the bus fabric, CLOCKS/RESETS/PLL/XOSC/ROSC register storage, full SIO (GPIO, CPUID, FIFO, spinlocks, divider, interpolators — no doorbells / MTIME / coprocessor bridge), IO_BANK0 / PADS_BANK0, XIP_CTRL / SSI stubs, and dual-core stepping (core 0 runs; core 1 stays halted until woken via the SIO FIFO protocol).

Phase 5.B wires the two PIO blocks (bus.pio[0], bus.pio[1]) into AHB at 0x5020_0000 / 0x5030_0000, steps them once per emulator step, and merges their pad outputs into bus.gpio_in (PIO OE overrides SIO on a per-pin basis, mirroring rp2350_emu::Emulator).

See wrk_docs/2026.04.14 - HLD - mdpicoem Workspace Restructure.md.

Re-exports

pub use self::bus::Bus;

pub use self::core::CortexM0Plus;

pub use self::memory::ROM_SIZE;

pub use self::memory::SRAM_SIZE;

pub use self::memory::bank_for_address;

Modules

bus

RP2040 AHB-Lite bus fabric.

core

Cortex-M0+ CPU core (ARMv6-M).

dma

RP2040 DMA controller — Phase 4 (HLD V7 §5.6).

dreq

RP2040 DREQ (data request) constants — Phase 4.

irq

RP2040 interrupt-number constants (NVIC line numbers, 0..=25).

memory

RP2040-specific memory bank topology.

peripherals

On-chip peripheral models plus integration tests for off-chip devices.

threaded

RP2040 threaded dual-core execution runtime.

Structs

Clock

Master cycle counter. All timing in the emulator derives from this.

Config

Emulator configuration.

Emulator

Top-level RP2040 emulator. Owns dual Cortex-M0+ cores, bus fabric, memory, and clock.

EmulatorBuilder

Builder for assembling the emulator. Seeds the Bus clock tree from Config::sys_clk_hz — the first CLOCKS / PLL register write replaces the seed with the derived value.

Memory

Unified memory backing stores. Owns the actual byte arrays for ROM, SRAM, and flash (XIP). No bus fabric or timing — just raw storage.

Pacer

Real-time pacer that spin-waits to keep emulation at the target clock rate.

PacerSnapshot

Point-in-time snapshot of pacer stats. All values are plain integers copied from the atomic counters. Derived metrics are computed here to keep the hot path (atomic updates) minimal.

PacerStats

Shared monitoring state. Atomic counters updated on the hot path, safe to read from any thread without locking.

Enums

ConfigError

Errors returned by EmulatorBuilder::build once the Stage 3b.4 wiring lands. The only non-trivial variant today is ThreadingUnavailable, returned when the caller selects ExecutionModel::Threaded but the host platform or build configuration cannot satisfy it.

EmulatorError

Errors returned by post-construction Emulator methods once the Stage 3b.4 wiring lands. Surfaces runtime-model mismatches and worker panics (dual-execution HLD V1 §5.5).

ExecutionModel

Execution model for an Emulator. Selected at construction via EmulatorBuilder::execution; cannot be switched post-build.

WorkerName

Identifier for a worker thread in the threaded runtime. RP2040 uses a three-worker layout (core0, core1, coordinator) — smaller than RP2350’s six-worker layout because M0+ has no PIO-as-worker split in the Stage 3b plan. rp2350_emu’s Pio0/Pio1/Pio2 worker variants are intentionally omitted here; if PIO becomes a bottleneck the enum can gain those variants in a follow-up.

Constants

DEFAULT_STEP_QUANTUM

Default quantum size in cycles. Matches rp2350_emu.

ROSC_FREQ_HZ

ROSC nominal frequency (~6.5 MHz). RP2040 boots on ROSC at the same nominal rate as RP2350; PLL configuration (if any) happens later in firmware. ROSC nominal frequency (~6.5 MHz). The RP2350 boots on ROSC; PLL configuration (if any) happens later in firmware.