#[doc = "PIO control register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ctrl(pub u32);
impl Ctrl {
#[doc = "Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."]
#[inline(always)]
pub const fn sm_enable(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."]
#[inline(always)]
pub fn set_sm_enable(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."]
#[inline(always)]
pub const fn sm_restart(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x0f;
val as u8
}
#[doc = "Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."]
#[inline(always)]
pub fn set_sm_restart(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
}
#[doc = "Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."]
#[inline(always)]
pub const fn clkdiv_restart(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."]
#[inline(always)]
pub fn set_clkdiv_restart(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
}
impl Default for Ctrl {
#[inline(always)]
fn default() -> Ctrl {
Ctrl(0)
}
}
#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct DbgCfginfo(pub u32);
impl DbgCfginfo {
#[doc = "The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."]
#[inline(always)]
pub const fn fifo_depth(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x3f;
val as u8
}
#[doc = "The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."]
#[inline(always)]
pub fn set_fifo_depth(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
}
#[doc = "The number of state machines this PIO instance is equipped with."]
#[inline(always)]
pub const fn sm_count(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "The number of state machines this PIO instance is equipped with."]
#[inline(always)]
pub fn set_sm_count(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[doc = "The size of the instruction memory, measured in units of one instruction"]
#[inline(always)]
pub const fn imem_size(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x3f;
val as u8
}
#[doc = "The size of the instruction memory, measured in units of one instruction"]
#[inline(always)]
pub fn set_imem_size(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize);
}
}
impl Default for DbgCfginfo {
#[inline(always)]
fn default() -> DbgCfginfo {
DbgCfginfo(0)
}
}
#[doc = "FIFO debug register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fdebug(pub u32);
impl Fdebug {
#[doc = "State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."]
#[inline(always)]
pub const fn rxstall(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."]
#[inline(always)]
pub fn set_rxstall(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."]
#[inline(always)]
pub const fn rxunder(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."]
#[inline(always)]
pub fn set_rxunder(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[doc = "TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."]
#[inline(always)]
pub const fn txover(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."]
#[inline(always)]
pub fn set_txover(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."]
#[inline(always)]
pub const fn txstall(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[doc = "State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."]
#[inline(always)]
pub fn set_txstall(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
}
impl Default for Fdebug {
#[inline(always)]
fn default() -> Fdebug {
Fdebug(0)
}
}
#[doc = "FIFO levels"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Flevel(pub u32);
impl Flevel {
#[inline(always)]
pub const fn tx0(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_tx0(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[inline(always)]
pub const fn rx0(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_rx0(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
}
#[inline(always)]
pub const fn tx1(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_tx1(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[inline(always)]
pub const fn rx1(&self) -> u8 {
let val = (self.0 >> 12usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_rx1(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u32) & 0x0f) << 12usize);
}
#[inline(always)]
pub const fn tx2(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_tx2(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[inline(always)]
pub const fn rx2(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_rx2(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
}
#[inline(always)]
pub const fn tx3(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_tx3(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
#[inline(always)]
pub const fn rx3(&self) -> u8 {
let val = (self.0 >> 28usize) & 0x0f;
val as u8
}
#[inline(always)]
pub fn set_rx3(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 28usize)) | (((val as u32) & 0x0f) << 28usize);
}
}
impl Default for Flevel {
#[inline(always)]
fn default() -> Flevel {
Flevel(0)
}
}
#[doc = "FIFO status register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fstat(pub u32);
impl Fstat {
#[doc = "State machine RX FIFO is full"]
#[inline(always)]
pub const fn rxfull(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "State machine RX FIFO is full"]
#[inline(always)]
pub fn set_rxfull(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "State machine RX FIFO is empty"]
#[inline(always)]
pub const fn rxempty(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "State machine RX FIFO is empty"]
#[inline(always)]
pub fn set_rxempty(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
#[doc = "State machine TX FIFO is full"]
#[inline(always)]
pub const fn txfull(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "State machine TX FIFO is full"]
#[inline(always)]
pub fn set_txfull(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "State machine TX FIFO is empty"]
#[inline(always)]
pub const fn txempty(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x0f;
val as u8
}
#[doc = "State machine TX FIFO is empty"]
#[inline(always)]
pub fn set_txempty(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 24usize)) | (((val as u32) & 0x0f) << 24usize);
}
}
impl Default for Fstat {
#[inline(always)]
fn default() -> Fstat {
Fstat(0)
}
}
#[doc = "Write-only access to instruction memory location 14"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct InstrMem(pub u32);
impl InstrMem {
#[inline(always)]
pub const fn instr_mem(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[inline(always)]
pub fn set_instr_mem(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for InstrMem {
#[inline(always)]
fn default() -> InstrMem {
InstrMem(0)
}
}
#[doc = "Raw Interrupts"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Intr(pub u32);
impl Intr {
#[inline(always)]
pub const fn sm0_rxnempty(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm0_rxnempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[inline(always)]
pub const fn sm1_rxnempty(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm1_rxnempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[inline(always)]
pub const fn sm2_rxnempty(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm2_rxnempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[inline(always)]
pub const fn sm3_rxnempty(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm3_rxnempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[inline(always)]
pub const fn sm0_txnfull(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm0_txnfull(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[inline(always)]
pub const fn sm1_txnfull(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm1_txnfull(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[inline(always)]
pub const fn sm2_txnfull(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm2_txnfull(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[inline(always)]
pub const fn sm3_txnfull(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm3_txnfull(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[inline(always)]
pub const fn sm0(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm0(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[inline(always)]
pub const fn sm1(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm1(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[inline(always)]
pub const fn sm2(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[inline(always)]
pub const fn sm3(&self) -> bool {
let val = (self.0 >> 11usize) & 0x01;
val != 0
}
#[inline(always)]
pub fn set_sm3(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
}
}
impl Default for Intr {
#[inline(always)]
fn default() -> Intr {
Intr(0)
}
}
#[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Irq(pub u32);
impl Irq {
#[inline(always)]
pub const fn irq(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[inline(always)]
pub fn set_irq(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
}
impl Default for Irq {
#[inline(always)]
fn default() -> Irq {
Irq(0)
}
}
#[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct IrqForce(pub u32);
impl IrqForce {
#[inline(always)]
pub const fn irq_force(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[inline(always)]
pub fn set_irq_force(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
}
impl Default for IrqForce {
#[inline(always)]
fn default() -> IrqForce {
IrqForce(0)
}
}
#[doc = "Current instruction address of state machine 0"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmAddr(pub u32);
impl SmAddr {
#[inline(always)]
pub const fn addr(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x1f;
val as u8
}
#[inline(always)]
pub fn set_addr(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
}
}
impl Default for SmAddr {
#[inline(always)]
fn default() -> SmAddr {
SmAddr(0)
}
}
#[doc = "Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmClkdiv(pub u32);
impl SmClkdiv {
#[doc = "Fractional part of clock divisor"]
#[inline(always)]
pub const fn frac(&self) -> u8 {
let val = (self.0 >> 8usize) & 0xff;
val as u8
}
#[doc = "Fractional part of clock divisor"]
#[inline(always)]
pub fn set_frac(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
}
#[doc = "Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
#[inline(always)]
pub const fn int(&self) -> u16 {
let val = (self.0 >> 16usize) & 0xffff;
val as u16
}
#[doc = "Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
#[inline(always)]
pub fn set_int(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
}
}
impl Default for SmClkdiv {
#[inline(always)]
fn default() -> SmClkdiv {
SmClkdiv(0)
}
}
#[doc = "Execution/behavioural settings for state machine 2"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmExecctrl(pub u32);
impl SmExecctrl {
#[doc = "Comparison level for the MOV x, STATUS instruction"]
#[inline(always)]
pub const fn status_n(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "Comparison level for the MOV x, STATUS instruction"]
#[inline(always)]
pub fn set_status_n(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "Comparison used for the MOV x, STATUS instruction."]
#[inline(always)]
pub const fn status_sel(&self) -> super::vals::SmExecctrlStatusSel {
let val = (self.0 >> 4usize) & 0x01;
super::vals::SmExecctrlStatusSel::from_bits(val as u8)
}
#[doc = "Comparison used for the MOV x, STATUS instruction."]
#[inline(always)]
pub fn set_status_sel(&mut self, val: super::vals::SmExecctrlStatusSel) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
}
#[doc = "After reaching wrap_top, execution is wrapped to this address."]
#[inline(always)]
pub const fn wrap_bottom(&self) -> u8 {
let val = (self.0 >> 7usize) & 0x1f;
val as u8
}
#[doc = "After reaching wrap_top, execution is wrapped to this address."]
#[inline(always)]
pub fn set_wrap_bottom(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 7usize)) | (((val as u32) & 0x1f) << 7usize);
}
#[doc = "After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."]
#[inline(always)]
pub const fn wrap_top(&self) -> u8 {
let val = (self.0 >> 12usize) & 0x1f;
val as u8
}
#[doc = "After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."]
#[inline(always)]
pub fn set_wrap_top(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 12usize)) | (((val as u32) & 0x1f) << 12usize);
}
#[doc = "Continuously assert the most recent OUT/SET to the pins"]
#[inline(always)]
pub const fn out_sticky(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Continuously assert the most recent OUT/SET to the pins"]
#[inline(always)]
pub fn set_out_sticky(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
#[inline(always)]
pub const fn inline_out_en(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
#[inline(always)]
pub fn set_inline_out_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Which data bit to use for inline OUT enable"]
#[inline(always)]
pub const fn out_en_sel(&self) -> u8 {
let val = (self.0 >> 19usize) & 0x1f;
val as u8
}
#[doc = "Which data bit to use for inline OUT enable"]
#[inline(always)]
pub fn set_out_en_sel(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 19usize)) | (((val as u32) & 0x1f) << 19usize);
}
#[doc = "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
#[inline(always)]
pub const fn jmp_pin(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x1f;
val as u8
}
#[doc = "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
#[inline(always)]
pub fn set_jmp_pin(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize);
}
#[doc = "If 1, side-set data is asserted to pin directions, instead of pin values"]
#[inline(always)]
pub const fn side_pindir(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "If 1, side-set data is asserted to pin directions, instead of pin values"]
#[inline(always)]
pub fn set_side_pindir(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
#[inline(always)]
pub const fn side_en(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
#[inline(always)]
pub fn set_side_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
#[inline(always)]
pub const fn exec_stalled(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."]
#[inline(always)]
pub fn set_exec_stalled(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for SmExecctrl {
#[inline(always)]
fn default() -> SmExecctrl {
SmExecctrl(0)
}
}
#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmInstr(pub u32);
impl SmInstr {
#[inline(always)]
pub const fn instr(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[inline(always)]
pub fn set_instr(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for SmInstr {
#[inline(always)]
fn default() -> SmInstr {
SmInstr(0)
}
}
#[doc = "State machine pin control"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmPinctrl(pub u32);
impl SmPinctrl {
#[doc = "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
#[inline(always)]
pub const fn out_base(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x1f;
val as u8
}
#[doc = "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
#[inline(always)]
pub fn set_out_base(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
}
#[doc = "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
#[inline(always)]
pub const fn set_base(&self) -> u8 {
let val = (self.0 >> 5usize) & 0x1f;
val as u8
}
#[doc = "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
#[inline(always)]
pub fn set_set_base(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 5usize)) | (((val as u32) & 0x1f) << 5usize);
}
#[doc = "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
#[inline(always)]
pub const fn sideset_base(&self) -> u8 {
let val = (self.0 >> 10usize) & 0x1f;
val as u8
}
#[doc = "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
#[inline(always)]
pub fn set_sideset_base(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize);
}
#[doc = "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
#[inline(always)]
pub const fn in_base(&self) -> u8 {
let val = (self.0 >> 15usize) & 0x1f;
val as u8
}
#[doc = "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
#[inline(always)]
pub fn set_in_base(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 15usize)) | (((val as u32) & 0x1f) << 15usize);
}
#[doc = "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
#[inline(always)]
pub const fn out_count(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x3f;
val as u8
}
#[doc = "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
#[inline(always)]
pub fn set_out_count(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 20usize)) | (((val as u32) & 0x3f) << 20usize);
}
#[doc = "The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
#[inline(always)]
pub const fn set_count(&self) -> u8 {
let val = (self.0 >> 26usize) & 0x07;
val as u8
}
#[doc = "The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
#[inline(always)]
pub fn set_set_count(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 26usize)) | (((val as u32) & 0x07) << 26usize);
}
#[doc = "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
#[inline(always)]
pub const fn sideset_count(&self) -> u8 {
let val = (self.0 >> 29usize) & 0x07;
val as u8
}
#[doc = "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
#[inline(always)]
pub fn set_sideset_count(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 29usize)) | (((val as u32) & 0x07) << 29usize);
}
}
impl Default for SmPinctrl {
#[inline(always)]
fn default() -> SmPinctrl {
SmPinctrl(0)
}
}
#[doc = "Control behaviour of the input/output shift registers for state machine 3"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct SmShiftctrl(pub u32);
impl SmShiftctrl {
#[doc = "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."]
#[inline(always)]
pub const fn autopush(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."]
#[inline(always)]
pub fn set_autopush(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."]
#[inline(always)]
pub const fn autopull(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."]
#[inline(always)]
pub fn set_autopull(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "1 = shift input shift register to right (data enters from left). 0 = to left."]
#[inline(always)]
pub const fn in_shiftdir(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "1 = shift input shift register to right (data enters from left). 0 = to left."]
#[inline(always)]
pub fn set_in_shiftdir(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "1 = shift out of output shift register to right. 0 = to left."]
#[inline(always)]
pub const fn out_shiftdir(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "1 = shift out of output shift register to right. 0 = to left."]
#[inline(always)]
pub fn set_out_shiftdir(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."]
#[inline(always)]
pub const fn push_thresh(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x1f;
val as u8
}
#[doc = "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."]
#[inline(always)]
pub fn set_push_thresh(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 20usize)) | (((val as u32) & 0x1f) << 20usize);
}
#[doc = "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."]
#[inline(always)]
pub const fn pull_thresh(&self) -> u8 {
let val = (self.0 >> 25usize) & 0x1f;
val as u8
}
#[doc = "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."]
#[inline(always)]
pub fn set_pull_thresh(&mut self, val: u8) {
self.0 = (self.0 & !(0x1f << 25usize)) | (((val as u32) & 0x1f) << 25usize);
}
#[doc = "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
#[inline(always)]
pub const fn fjoin_tx(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
#[inline(always)]
pub fn set_fjoin_tx(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
#[doc = "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
#[inline(always)]
pub const fn fjoin_rx(&self) -> bool {
let val = (self.0 >> 31usize) & 0x01;
val != 0
}
#[doc = "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
#[inline(always)]
pub fn set_fjoin_rx(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
}
}
impl Default for SmShiftctrl {
#[inline(always)]
fn default() -> SmShiftctrl {
SmShiftctrl(0)
}
}