Expand description
Clock driver for RK3588
§Overview
Clock is the heart of synchronous digital systems. All the events in an SoC are controlled by the active edge of the clock and clock frequency is often synonymous with throughput and performance.
§Clock tree
The clock tree is a hierarchical structure that distributes the clock signal from a single source to various components in the system. The clock tree is designed to minimize skew and ensure that all components receive the clock signal at the same time. The clock tree is typically implemented using a combination of buffers, inverters, and multiplexers. The clock tree is also responsible for generating different clock frequencies for different components in the system.
§CRU
The Clock Reset Unit (CRU) is responsible for managing the clock and reset signals for the various components in the RK3588 SoC. The CRU is responsible for generating the clock signals for the CPU, GPU, NPU, and other peripherals. The CRU is also responsible for managing the reset signals for the various components in the RK3588 SoC.
§About the driver
The driver is designed to be used in a no_std environment, and provides abstractions for configuring clocks on the RK3588 SoC. It supports:
- MMC (eMMC/SDIO) clock configuration
- NPU clock gate control
- USB clock management
- PLL clock management
§Usage
use rk3588_clk::{Rk3588Cru, constant::*};
use core::ptr::NonNull;
let cru = Rk3588Cru::new(NonNull::new(clk_addr as *mut u8).unwrap());
// Get clock frequency
let rate = cru.mmc_get_clk(CCLK_EMMC)?;
// Set clock frequency
cru.mmc_set_clk(CCLK_EMMC, 200_000_000)?;
// Enable NPU clock gates
cru.npu_gate_enable(ACLK_NPU0)?;Modules§
Structs§
- Rk3588
Cru - RK3588 Clock and Reset Unit (CRU) driver
- Rk3588
CruRegisters - CRU register layout for RK3588