Crate rk3568_clk 

Clock driver for RK3568

Overview

Clock is the heart of synchronous digital systems. All the events in an SoC are controlled by the active edge of the clock and clock frequency is often synonymous with throughput and performance.

Clock tree

The clock tree is a hierarchical structure that distributes the clock signal from a single source to various components in the system. The clock tree is designed to minimize skew and ensure that all components receive the clock signal at the same time. The clock tree is typically implemented using a combination of buffers, inverters, and multiplexers. The clock tree is also responsible for generating different clock frequencies for different components in the system.

CRU

The Clock Reset Unit (CRU) is responsible for managing the clock and reset signals for the various components in the RK3568 SoC. The CRU is responsible for generating the clock signals for the CPU, GPU, DSP, and other peripherals. The CRU is also responsible for managing the reset signals for the various components in the RK3568 SoC.

About the driver

The driver is designed to be used in a no_std environment, and does not depend on any external libraries or crates. The driver is designed to be used in a no_std environment, and does not depend on any external libraries or crates. The driver is designed to be used in a no_std environment, and does not depend on any external libraries or crates.

Usage

use rk3568_clk::CRU;
use rk3568_clk::cru_clksel_con28_bits::{*};

let clock = CRU::new(clk_addr as u64);
clock.cru_clksel_set_cclk_emmc(CRU_CLKSEL_CCLK_EMMC_GPL_DIV_200M);
clock.cru_enable_tclk_emmc();

Modules

cru_clksel_con28_bits

This module contains the bit field definitions for the CRU_CLKSEL_CON28 register. It defines the positions and masks for various clock selection bits.

cru_emmc_con0_bits

This module contains the bit field definitions for the CRU_EMMC_CON0 register. It defines the positions and masks for various clock selection bits.

cru_emmc_con1_bits

This module contains the bit field definitions for the CRU_EMMC_CON1 register. It defines the positions and masks for various clock selection bits.

cru_gate_con09_bits

This module contains the bit field definitions for the CRU_GATE_CON09 register. It defines the positions and masks for various clock selection bits.

cru_softrst_con07_bits

This module contains the bit field definitions for the CRU_SOFTRST_CON07 register. It defines the positions and masks for various clock selection bits.

Structs

CRU

Clock and Reset Unit (CRU) This struct provides a safe interface to the CRU registers. It allows reading and writing to the registers, as well as setting and getting specific bits in the registers.

RegMap

Clock and Reset Unit (CRU) register map this struct defines the layout of the CRU registers in memory. It is used to access the CRU registers in a safe and efficient manner. There are a total of 240 registers in the CRU, each 4 bytes wide.