rk3399_pac/msch/
dev_to_dev0.rs

1#[doc = "Register `DevToDev0` reader"]
2pub type R = crate::R<DevToDev0Spec>;
3#[doc = "Register `DevToDev0` writer"]
4pub type W = crate::W<DevToDev0Spec>;
5#[doc = "Field `BUSRDTORD` reader - number of cycle between the last read data of a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
6pub type BusrdtordR = crate::FieldReader;
7#[doc = "Field `BUSRDTORD` writer - number of cycle between the last read data of a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
8pub type BusrdtordW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `BUSRDTOWR` reader - number of cycle between the last read data of a device and the first\n\nwrite data to another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
10pub type BusrdtowrR = crate::FieldReader;
11#[doc = "Field `BUSRDTOWR` writer - number of cycle between the last read data of a device and the first\n\nwrite data to another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
12pub type BusrdtowrW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `BUSWRTORD` reader - number of cycle between the last write data to a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
14pub type BuswrtordR = crate::FieldReader;
15#[doc = "Field `BUSWRTORD` writer - number of cycle between the last write data to a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
16pub type BuswrtordW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `BUSWRTOWR` reader - number of cycle between the last write data to a device and the first\n\nwrite data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
18pub type BuswrtowrR = crate::FieldReader;
19#[doc = "Field `BUSWRTOWR` writer - number of cycle between the last write data to a device and the first\n\nwrite data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
20pub type BuswrtowrW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21impl R {
22    #[doc = "Bits 0:2 - number of cycle between the last read data of a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
23    #[inline(always)]
24    pub fn busrdtord(&self) -> BusrdtordR {
25        BusrdtordR::new((self.bits & 7) as u8)
26    }
27    #[doc = "Bits 4:6 - number of cycle between the last read data of a device and the first\n\nwrite data to another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
28    #[inline(always)]
29    pub fn busrdtowr(&self) -> BusrdtowrR {
30        BusrdtowrR::new(((self.bits >> 4) & 7) as u8)
31    }
32    #[doc = "Bits 8:10 - number of cycle between the last write data to a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
33    #[inline(always)]
34    pub fn buswrtord(&self) -> BuswrtordR {
35        BuswrtordR::new(((self.bits >> 8) & 7) as u8)
36    }
37    #[doc = "Bits 12:14 - number of cycle between the last write data to a device and the first\n\nwrite data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
38    #[inline(always)]
39    pub fn buswrtowr(&self) -> BuswrtowrR {
40        BuswrtowrR::new(((self.bits >> 12) & 7) as u8)
41    }
42}
43impl W {
44    #[doc = "Bits 0:2 - number of cycle between the last read data of a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
45    #[inline(always)]
46    #[must_use]
47    pub fn busrdtord(&mut self) -> BusrdtordW<DevToDev0Spec> {
48        BusrdtordW::new(self, 0)
49    }
50    #[doc = "Bits 4:6 - number of cycle between the last read data of a device and the first\n\nwrite data to another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
51    #[inline(always)]
52    #[must_use]
53    pub fn busrdtowr(&mut self) -> BusrdtowrW<DevToDev0Spec> {
54        BusrdtowrW::new(self, 4)
55    }
56    #[doc = "Bits 8:10 - number of cycle between the last write data to a device and the first\n\nread data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
57    #[inline(always)]
58    #[must_use]
59    pub fn buswrtord(&mut self) -> BuswrtordW<DevToDev0Spec> {
60        BuswrtordW::new(self, 8)
61    }
62    #[doc = "Bits 12:14 - number of cycle between the last write data to a device and the first\n\nwrite data of another device.\n\nThe field must be set according to the third-party DDR controller\n\nspecification."]
63    #[inline(always)]
64    #[must_use]
65    pub fn buswrtowr(&mut self) -> BuswrtowrW<DevToDev0Spec> {
66        BuswrtowrW::new(self, 12)
67    }
68}
69#[doc = "Timing values concerning device to device data bus ownership c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_to_dev0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_to_dev0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct DevToDev0Spec;
71impl crate::RegisterSpec for DevToDev0Spec {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [`dev_to_dev0::R`](R) reader structure"]
75impl crate::Readable for DevToDev0Spec {}
76#[doc = "`write(|w| ..)` method takes [`dev_to_dev0::W`](W) writer structure"]
77impl crate::Writable for DevToDev0Spec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets DevToDev0 to value 0x0222"]
83impl crate::Resettable for DevToDev0Spec {
84    const RESET_VALUE: u32 = 0x0222;
85}
rk3399_pac/msch/dev_to_dev0.rs

rk3399_pac/msch/
dev_to_dev0.rs
