rk3399_pac/gmac/
debug.rs

1#[doc = "Register `DEBUG` reader"]
2pub type R = crate::R<DebugSpec>;
3#[doc = "Register `DEBUG` writer"]
4pub type W = crate::W<DebugSpec>;
5#[doc = "Field `RDB` reader - When high, it indicates that the MAC GMII/MII receive protocol\n\nengine is actively receiving data and not in IDLE state."]
6pub type RdbR = crate::BitReader;
7#[doc = "Field `RDB` writer - When high, it indicates that the MAC GMII/MII receive protocol\n\nengine is actively receiving data and not in IDLE state."]
8pub type RdbW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ACT` reader - When high, it indicates the active state of the small FIFO Read\n\nand Write controllers respectively of the MAC receive Frame\n\nController module"]
10pub type ActR = crate::FieldReader;
11#[doc = "Field `ACT` writer - When high, it indicates the active state of the small FIFO Read\n\nand Write controllers respectively of the MAC receive Frame\n\nController module"]
12pub type ActW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `RFIFOWR` reader - When high, it indicates that the MTL RxFIFO Write Controller is\n\nactive and transferring a received frame to the FIFO."]
14pub type RfifowrR = crate::BitReader;
15#[doc = "Field `RFIFOWR` writer - When high, it indicates that the MTL RxFIFO Write Controller is\n\nactive and transferring a received frame to the FIFO."]
16pub type RfifowrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "It gives the state of the RxFIFO read Controller:\n\nValue on reset: 0"]
18#[cfg_attr(feature = "defmt", derive(defmt::Format))]
19#[derive(Clone, Copy, Debug, PartialEq, Eq)]
20#[repr(u8)]
21pub enum Rfiford {
22    #[doc = "0: IDLE state"]
23    B00 = 0,
24    #[doc = "1: Reading frame data"]
25    B01 = 1,
26    #[doc = "2: Reading frame status (or time-stamp)"]
27    B10 = 2,
28    #[doc = "3: Flushing the frame data and Status"]
29    B11 = 3,
30}
31impl From<Rfiford> for u8 {
32    #[inline(always)]
33    fn from(variant: Rfiford) -> Self {
34        variant as _
35    }
36}
37impl crate::FieldSpec for Rfiford {
38    type Ux = u8;
39}
40#[doc = "Field `RFIFORD` reader - It gives the state of the RxFIFO read Controller:"]
41pub type RfifordR = crate::FieldReader<Rfiford>;
42impl RfifordR {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub const fn variant(&self) -> Rfiford {
46        match self.bits {
47            0 => Rfiford::B00,
48            1 => Rfiford::B01,
49            2 => Rfiford::B10,
50            3 => Rfiford::B11,
51            _ => unreachable!(),
52        }
53    }
54    #[doc = "IDLE state"]
55    #[inline(always)]
56    pub fn is_b00(&self) -> bool {
57        *self == Rfiford::B00
58    }
59    #[doc = "Reading frame data"]
60    #[inline(always)]
61    pub fn is_b01(&self) -> bool {
62        *self == Rfiford::B01
63    }
64    #[doc = "Reading frame status (or time-stamp)"]
65    #[inline(always)]
66    pub fn is_b10(&self) -> bool {
67        *self == Rfiford::B10
68    }
69    #[doc = "Flushing the frame data and Status"]
70    #[inline(always)]
71    pub fn is_b11(&self) -> bool {
72        *self == Rfiford::B11
73    }
74}
75#[doc = "Field `RFIFORD` writer - It gives the state of the RxFIFO read Controller:"]
76pub type RfifordW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Rfiford>;
77impl<'a, REG> RfifordW<'a, REG>
78where
79    REG: crate::Writable + crate::RegisterSpec,
80    REG::Ux: From<u8>,
81{
82    #[doc = "IDLE state"]
83    #[inline(always)]
84    pub fn b00(self) -> &'a mut crate::W<REG> {
85        self.variant(Rfiford::B00)
86    }
87    #[doc = "Reading frame data"]
88    #[inline(always)]
89    pub fn b01(self) -> &'a mut crate::W<REG> {
90        self.variant(Rfiford::B01)
91    }
92    #[doc = "Reading frame status (or time-stamp)"]
93    #[inline(always)]
94    pub fn b10(self) -> &'a mut crate::W<REG> {
95        self.variant(Rfiford::B10)
96    }
97    #[doc = "Flushing the frame data and Status"]
98    #[inline(always)]
99    pub fn b11(self) -> &'a mut crate::W<REG> {
100        self.variant(Rfiford::B11)
101    }
102}
103#[doc = "This gives the status of the RxFIFO Fill-level:\n\nValue on reset: 0"]
104#[cfg_attr(feature = "defmt", derive(defmt::Format))]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum Rfifo {
108    #[doc = "0: RxFIFO Empty"]
109    B00 = 0,
110    #[doc = "1: RxFIFO fill-level below flow-control de-activate threshold"]
111    B01 = 1,
112    #[doc = "2: RxFIFO fill-level above flow-control activate threshold"]
113    B10 = 2,
114    #[doc = "3: RxFIFO Full"]
115    B11 = 3,
116}
117impl From<Rfifo> for u8 {
118    #[inline(always)]
119    fn from(variant: Rfifo) -> Self {
120        variant as _
121    }
122}
123impl crate::FieldSpec for Rfifo {
124    type Ux = u8;
125}
126#[doc = "Field `RFIFO` reader - This gives the status of the RxFIFO Fill-level:"]
127pub type RfifoR = crate::FieldReader<Rfifo>;
128impl RfifoR {
129    #[doc = "Get enumerated values variant"]
130    #[inline(always)]
131    pub const fn variant(&self) -> Rfifo {
132        match self.bits {
133            0 => Rfifo::B00,
134            1 => Rfifo::B01,
135            2 => Rfifo::B10,
136            3 => Rfifo::B11,
137            _ => unreachable!(),
138        }
139    }
140    #[doc = "RxFIFO Empty"]
141    #[inline(always)]
142    pub fn is_b00(&self) -> bool {
143        *self == Rfifo::B00
144    }
145    #[doc = "RxFIFO fill-level below flow-control de-activate threshold"]
146    #[inline(always)]
147    pub fn is_b01(&self) -> bool {
148        *self == Rfifo::B01
149    }
150    #[doc = "RxFIFO fill-level above flow-control activate threshold"]
151    #[inline(always)]
152    pub fn is_b10(&self) -> bool {
153        *self == Rfifo::B10
154    }
155    #[doc = "RxFIFO Full"]
156    #[inline(always)]
157    pub fn is_b11(&self) -> bool {
158        *self == Rfifo::B11
159    }
160}
161#[doc = "Field `RFIFO` writer - This gives the status of the RxFIFO Fill-level:"]
162pub type RfifoW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Rfifo>;
163impl<'a, REG> RfifoW<'a, REG>
164where
165    REG: crate::Writable + crate::RegisterSpec,
166    REG::Ux: From<u8>,
167{
168    #[doc = "RxFIFO Empty"]
169    #[inline(always)]
170    pub fn b00(self) -> &'a mut crate::W<REG> {
171        self.variant(Rfifo::B00)
172    }
173    #[doc = "RxFIFO fill-level below flow-control de-activate threshold"]
174    #[inline(always)]
175    pub fn b01(self) -> &'a mut crate::W<REG> {
176        self.variant(Rfifo::B01)
177    }
178    #[doc = "RxFIFO fill-level above flow-control activate threshold"]
179    #[inline(always)]
180    pub fn b10(self) -> &'a mut crate::W<REG> {
181        self.variant(Rfifo::B10)
182    }
183    #[doc = "RxFIFO Full"]
184    #[inline(always)]
185    pub fn b11(self) -> &'a mut crate::W<REG> {
186        self.variant(Rfifo::B11)
187    }
188}
189#[doc = "Field `TACT` reader - When high, it indicates that the MAC GMII/MII transmit protocol\n\nengine is actively transmitting data and not in IDLE state."]
190pub type TactR = crate::BitReader;
191#[doc = "Field `TACT` writer - When high, it indicates that the MAC GMII/MII transmit protocol\n\nengine is actively transmitting data and not in IDLE state."]
192pub type TactW<'a, REG> = crate::BitWriter<'a, REG>;
193#[doc = "This indicates the state of the MAC Transmit Frame Controller\n\nmodule:\n\nValue on reset: 0"]
194#[cfg_attr(feature = "defmt", derive(defmt::Format))]
195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
196#[repr(u8)]
197pub enum Tsat {
198    #[doc = "0: IDLE"]
199    B00 = 0,
200    #[doc = "1: Waiting for Status of previous frame or IFG/backoff period to be over"]
201    B01 = 1,
202    #[doc = "2: Generating and transmitting a PAUSE control frame (in full duplex mode)"]
203    B10 = 2,
204    #[doc = "3: Transferring input frame for transmission"]
205    B11 = 3,
206}
207impl From<Tsat> for u8 {
208    #[inline(always)]
209    fn from(variant: Tsat) -> Self {
210        variant as _
211    }
212}
213impl crate::FieldSpec for Tsat {
214    type Ux = u8;
215}
216#[doc = "Field `TSAT` reader - This indicates the state of the MAC Transmit Frame Controller\n\nmodule:"]
217pub type TsatR = crate::FieldReader<Tsat>;
218impl TsatR {
219    #[doc = "Get enumerated values variant"]
220    #[inline(always)]
221    pub const fn variant(&self) -> Tsat {
222        match self.bits {
223            0 => Tsat::B00,
224            1 => Tsat::B01,
225            2 => Tsat::B10,
226            3 => Tsat::B11,
227            _ => unreachable!(),
228        }
229    }
230    #[doc = "IDLE"]
231    #[inline(always)]
232    pub fn is_b00(&self) -> bool {
233        *self == Tsat::B00
234    }
235    #[doc = "Waiting for Status of previous frame or IFG/backoff period to be over"]
236    #[inline(always)]
237    pub fn is_b01(&self) -> bool {
238        *self == Tsat::B01
239    }
240    #[doc = "Generating and transmitting a PAUSE control frame (in full duplex mode)"]
241    #[inline(always)]
242    pub fn is_b10(&self) -> bool {
243        *self == Tsat::B10
244    }
245    #[doc = "Transferring input frame for transmission"]
246    #[inline(always)]
247    pub fn is_b11(&self) -> bool {
248        *self == Tsat::B11
249    }
250}
251#[doc = "Field `TSAT` writer - This indicates the state of the MAC Transmit Frame Controller\n\nmodule:"]
252pub type TsatW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Tsat>;
253impl<'a, REG> TsatW<'a, REG>
254where
255    REG: crate::Writable + crate::RegisterSpec,
256    REG::Ux: From<u8>,
257{
258    #[doc = "IDLE"]
259    #[inline(always)]
260    pub fn b00(self) -> &'a mut crate::W<REG> {
261        self.variant(Tsat::B00)
262    }
263    #[doc = "Waiting for Status of previous frame or IFG/backoff period to be over"]
264    #[inline(always)]
265    pub fn b01(self) -> &'a mut crate::W<REG> {
266        self.variant(Tsat::B01)
267    }
268    #[doc = "Generating and transmitting a PAUSE control frame (in full duplex mode)"]
269    #[inline(always)]
270    pub fn b10(self) -> &'a mut crate::W<REG> {
271        self.variant(Tsat::B10)
272    }
273    #[doc = "Transferring input frame for transmission"]
274    #[inline(always)]
275    pub fn b11(self) -> &'a mut crate::W<REG> {
276        self.variant(Tsat::B11)
277    }
278}
279#[doc = "Field `PAUSE` reader - When high, it indicates that the MAC transmitter is in PAUSE\n\ncondition (in full-duplex only) and hence will not schedule any\n\nframe for transmission"]
280pub type PauseR = crate::BitReader;
281#[doc = "Field `PAUSE` writer - When high, it indicates that the MAC transmitter is in PAUSE\n\ncondition (in full-duplex only) and hence will not schedule any\n\nframe for transmission"]
282pub type PauseW<'a, REG> = crate::BitWriter<'a, REG>;
283#[doc = "This indicates the state of the TxFIFO read Controller:\n\nValue on reset: 0"]
284#[cfg_attr(feature = "defmt", derive(defmt::Format))]
285#[derive(Clone, Copy, Debug, PartialEq, Eq)]
286#[repr(u8)]
287pub enum Tfifosta {
288    #[doc = "0: IDLE state"]
289    B00 = 0,
290    #[doc = "1: READ state (transferring data to MAC transmitter)"]
291    B01 = 1,
292    #[doc = "2: Waiting for TxStatus from MAC transmitter"]
293    B10 = 2,
294    #[doc = "3: Writing the received TxStatus or flushing the TxFIFO"]
295    B11 = 3,
296}
297impl From<Tfifosta> for u8 {
298    #[inline(always)]
299    fn from(variant: Tfifosta) -> Self {
300        variant as _
301    }
302}
303impl crate::FieldSpec for Tfifosta {
304    type Ux = u8;
305}
306#[doc = "Field `TFIFOSTA` reader - This indicates the state of the TxFIFO read Controller:"]
307pub type TfifostaR = crate::FieldReader<Tfifosta>;
308impl TfifostaR {
309    #[doc = "Get enumerated values variant"]
310    #[inline(always)]
311    pub const fn variant(&self) -> Tfifosta {
312        match self.bits {
313            0 => Tfifosta::B00,
314            1 => Tfifosta::B01,
315            2 => Tfifosta::B10,
316            3 => Tfifosta::B11,
317            _ => unreachable!(),
318        }
319    }
320    #[doc = "IDLE state"]
321    #[inline(always)]
322    pub fn is_b00(&self) -> bool {
323        *self == Tfifosta::B00
324    }
325    #[doc = "READ state (transferring data to MAC transmitter)"]
326    #[inline(always)]
327    pub fn is_b01(&self) -> bool {
328        *self == Tfifosta::B01
329    }
330    #[doc = "Waiting for TxStatus from MAC transmitter"]
331    #[inline(always)]
332    pub fn is_b10(&self) -> bool {
333        *self == Tfifosta::B10
334    }
335    #[doc = "Writing the received TxStatus or flushing the TxFIFO"]
336    #[inline(always)]
337    pub fn is_b11(&self) -> bool {
338        *self == Tfifosta::B11
339    }
340}
341#[doc = "Field `TFIFOSTA` writer - This indicates the state of the TxFIFO read Controller:"]
342pub type TfifostaW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Tfifosta>;
343impl<'a, REG> TfifostaW<'a, REG>
344where
345    REG: crate::Writable + crate::RegisterSpec,
346    REG::Ux: From<u8>,
347{
348    #[doc = "IDLE state"]
349    #[inline(always)]
350    pub fn b00(self) -> &'a mut crate::W<REG> {
351        self.variant(Tfifosta::B00)
352    }
353    #[doc = "READ state (transferring data to MAC transmitter)"]
354    #[inline(always)]
355    pub fn b01(self) -> &'a mut crate::W<REG> {
356        self.variant(Tfifosta::B01)
357    }
358    #[doc = "Waiting for TxStatus from MAC transmitter"]
359    #[inline(always)]
360    pub fn b10(self) -> &'a mut crate::W<REG> {
361        self.variant(Tfifosta::B10)
362    }
363    #[doc = "Writing the received TxStatus or flushing the TxFIFO"]
364    #[inline(always)]
365    pub fn b11(self) -> &'a mut crate::W<REG> {
366        self.variant(Tfifosta::B11)
367    }
368}
369#[doc = "Field `TFIFO1` reader - When high, it indicates that the MTL TxFIFO Write Controller is\n\nactive and transferring data to the TxFIFO."]
370pub type Tfifo1R = crate::BitReader;
371#[doc = "Field `TFIFO1` writer - When high, it indicates that the MTL TxFIFO Write Controller is\n\nactive and transferring data to the TxFIFO."]
372pub type Tfifo1W<'a, REG> = crate::BitWriter<'a, REG>;
373#[doc = "Field `TFIFO2` reader - When high, it indicates that the MTL TxFIFO is not empty and has\n\nsome data left for transmission."]
374pub type Tfifo2R = crate::BitReader;
375#[doc = "Field `TFIFO2` writer - When high, it indicates that the MTL TxFIFO is not empty and has\n\nsome data left for transmission."]
376pub type Tfifo2W<'a, REG> = crate::BitWriter<'a, REG>;
377#[doc = "Field `TFIFO3` reader - When high, it indicates that the MTL TxStatus FIFO is full and\n\nhence the MTL will not be accepting any more frames for\n\ntransmission."]
378pub type Tfifo3R = crate::BitReader;
379#[doc = "Field `TFIFO3` writer - When high, it indicates that the MTL TxStatus FIFO is full and\n\nhence the MTL will not be accepting any more frames for\n\ntransmission."]
380pub type Tfifo3W<'a, REG> = crate::BitWriter<'a, REG>;
381impl R {
382    #[doc = "Bit 0 - When high, it indicates that the MAC GMII/MII receive protocol\n\nengine is actively receiving data and not in IDLE state."]
383    #[inline(always)]
384    pub fn rdb(&self) -> RdbR {
385        RdbR::new((self.bits & 1) != 0)
386    }
387    #[doc = "Bits 1:2 - When high, it indicates the active state of the small FIFO Read\n\nand Write controllers respectively of the MAC receive Frame\n\nController module"]
388    #[inline(always)]
389    pub fn act(&self) -> ActR {
390        ActR::new(((self.bits >> 1) & 3) as u8)
391    }
392    #[doc = "Bit 4 - When high, it indicates that the MTL RxFIFO Write Controller is\n\nactive and transferring a received frame to the FIFO."]
393    #[inline(always)]
394    pub fn rfifowr(&self) -> RfifowrR {
395        RfifowrR::new(((self.bits >> 4) & 1) != 0)
396    }
397    #[doc = "Bits 5:6 - It gives the state of the RxFIFO read Controller:"]
398    #[inline(always)]
399    pub fn rfiford(&self) -> RfifordR {
400        RfifordR::new(((self.bits >> 5) & 3) as u8)
401    }
402    #[doc = "Bits 8:9 - This gives the status of the RxFIFO Fill-level:"]
403    #[inline(always)]
404    pub fn rfifo(&self) -> RfifoR {
405        RfifoR::new(((self.bits >> 8) & 3) as u8)
406    }
407    #[doc = "Bit 16 - When high, it indicates that the MAC GMII/MII transmit protocol\n\nengine is actively transmitting data and not in IDLE state."]
408    #[inline(always)]
409    pub fn tact(&self) -> TactR {
410        TactR::new(((self.bits >> 16) & 1) != 0)
411    }
412    #[doc = "Bits 17:18 - This indicates the state of the MAC Transmit Frame Controller\n\nmodule:"]
413    #[inline(always)]
414    pub fn tsat(&self) -> TsatR {
415        TsatR::new(((self.bits >> 17) & 3) as u8)
416    }
417    #[doc = "Bit 19 - When high, it indicates that the MAC transmitter is in PAUSE\n\ncondition (in full-duplex only) and hence will not schedule any\n\nframe for transmission"]
418    #[inline(always)]
419    pub fn pause(&self) -> PauseR {
420        PauseR::new(((self.bits >> 19) & 1) != 0)
421    }
422    #[doc = "Bits 20:21 - This indicates the state of the TxFIFO read Controller:"]
423    #[inline(always)]
424    pub fn tfifosta(&self) -> TfifostaR {
425        TfifostaR::new(((self.bits >> 20) & 3) as u8)
426    }
427    #[doc = "Bit 22 - When high, it indicates that the MTL TxFIFO Write Controller is\n\nactive and transferring data to the TxFIFO."]
428    #[inline(always)]
429    pub fn tfifo1(&self) -> Tfifo1R {
430        Tfifo1R::new(((self.bits >> 22) & 1) != 0)
431    }
432    #[doc = "Bit 24 - When high, it indicates that the MTL TxFIFO is not empty and has\n\nsome data left for transmission."]
433    #[inline(always)]
434    pub fn tfifo2(&self) -> Tfifo2R {
435        Tfifo2R::new(((self.bits >> 24) & 1) != 0)
436    }
437    #[doc = "Bit 25 - When high, it indicates that the MTL TxStatus FIFO is full and\n\nhence the MTL will not be accepting any more frames for\n\ntransmission."]
438    #[inline(always)]
439    pub fn tfifo3(&self) -> Tfifo3R {
440        Tfifo3R::new(((self.bits >> 25) & 1) != 0)
441    }
442}
443impl W {
444    #[doc = "Bit 0 - When high, it indicates that the MAC GMII/MII receive protocol\n\nengine is actively receiving data and not in IDLE state."]
445    #[inline(always)]
446    #[must_use]
447    pub fn rdb(&mut self) -> RdbW<DebugSpec> {
448        RdbW::new(self, 0)
449    }
450    #[doc = "Bits 1:2 - When high, it indicates the active state of the small FIFO Read\n\nand Write controllers respectively of the MAC receive Frame\n\nController module"]
451    #[inline(always)]
452    #[must_use]
453    pub fn act(&mut self) -> ActW<DebugSpec> {
454        ActW::new(self, 1)
455    }
456    #[doc = "Bit 4 - When high, it indicates that the MTL RxFIFO Write Controller is\n\nactive and transferring a received frame to the FIFO."]
457    #[inline(always)]
458    #[must_use]
459    pub fn rfifowr(&mut self) -> RfifowrW<DebugSpec> {
460        RfifowrW::new(self, 4)
461    }
462    #[doc = "Bits 5:6 - It gives the state of the RxFIFO read Controller:"]
463    #[inline(always)]
464    #[must_use]
465    pub fn rfiford(&mut self) -> RfifordW<DebugSpec> {
466        RfifordW::new(self, 5)
467    }
468    #[doc = "Bits 8:9 - This gives the status of the RxFIFO Fill-level:"]
469    #[inline(always)]
470    #[must_use]
471    pub fn rfifo(&mut self) -> RfifoW<DebugSpec> {
472        RfifoW::new(self, 8)
473    }
474    #[doc = "Bit 16 - When high, it indicates that the MAC GMII/MII transmit protocol\n\nengine is actively transmitting data and not in IDLE state."]
475    #[inline(always)]
476    #[must_use]
477    pub fn tact(&mut self) -> TactW<DebugSpec> {
478        TactW::new(self, 16)
479    }
480    #[doc = "Bits 17:18 - This indicates the state of the MAC Transmit Frame Controller\n\nmodule:"]
481    #[inline(always)]
482    #[must_use]
483    pub fn tsat(&mut self) -> TsatW<DebugSpec> {
484        TsatW::new(self, 17)
485    }
486    #[doc = "Bit 19 - When high, it indicates that the MAC transmitter is in PAUSE\n\ncondition (in full-duplex only) and hence will not schedule any\n\nframe for transmission"]
487    #[inline(always)]
488    #[must_use]
489    pub fn pause(&mut self) -> PauseW<DebugSpec> {
490        PauseW::new(self, 19)
491    }
492    #[doc = "Bits 20:21 - This indicates the state of the TxFIFO read Controller:"]
493    #[inline(always)]
494    #[must_use]
495    pub fn tfifosta(&mut self) -> TfifostaW<DebugSpec> {
496        TfifostaW::new(self, 20)
497    }
498    #[doc = "Bit 22 - When high, it indicates that the MTL TxFIFO Write Controller is\n\nactive and transferring data to the TxFIFO."]
499    #[inline(always)]
500    #[must_use]
501    pub fn tfifo1(&mut self) -> Tfifo1W<DebugSpec> {
502        Tfifo1W::new(self, 22)
503    }
504    #[doc = "Bit 24 - When high, it indicates that the MTL TxFIFO is not empty and has\n\nsome data left for transmission."]
505    #[inline(always)]
506    #[must_use]
507    pub fn tfifo2(&mut self) -> Tfifo2W<DebugSpec> {
508        Tfifo2W::new(self, 24)
509    }
510    #[doc = "Bit 25 - When high, it indicates that the MTL TxStatus FIFO is full and\n\nhence the MTL will not be accepting any more frames for\n\ntransmission."]
511    #[inline(always)]
512    #[must_use]
513    pub fn tfifo3(&mut self) -> Tfifo3W<DebugSpec> {
514        Tfifo3W::new(self, 25)
515    }
516}
517#[doc = "Debug register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
518pub struct DebugSpec;
519impl crate::RegisterSpec for DebugSpec {
520    type Ux = u32;
521}
522#[doc = "`read()` method returns [`debug::R`](R) reader structure"]
523impl crate::Readable for DebugSpec {}
524#[doc = "`write(|w| ..)` method takes [`debug::W`](W) writer structure"]
525impl crate::Writable for DebugSpec {
526    type Safety = crate::Unsafe;
527    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
528    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
529}
530#[doc = "`reset()` method sets DEBUG to value 0"]
531impl crate::Resettable for DebugSpec {
532    const RESET_VALUE: u32 = 0;
533}
rk3399_pac/gmac/debug.rs

rk3399_pac/gmac/
debug.rs
