Expand description
Rockchip Inter-Integrated Circuit (RKI2C) Registers
Modules§
- clkdiv
- clock divider register
- con
- control register
- fcnt
- finished count
- ien
- interrupt enable register
- ipd
- interrupt pending register
- mrxaddr
- the slave address accessed for master rx mode
- mrxcnt
- master rx count
- mrxraddr
- the slave register address accessed for master rx mode
- mtxcnt
- master transmit count
- rxdata0
- I2C rx data register 0
- rxdata1
- I2C rx data register 1
- rxdata2
- I2C rx data register 2
- rxdata3
- I2C rx data register 3
- rxdata4
- I2C rx data register 4
- rxdata5
- I2C rx data register 5
- rxdata6
- I2C rx data register 6
- rxdata7
- I2C rx data register 7
- scl_
oe_ db - slave hold debounce configure register
- st
- status debug register
- txdata0
- I2C tx data register 0
- txdata1
- I2C tx data register 1
- txdata2
- I2C tx data register 2
- txdata3
- I2C tx data register 3
- txdata4
- I2C tx data register 4
- txdata5
- I2C tx data register 5
- txdata6
- I2C tx data register 6
- txdata7
- I2C tx data register 7
Structs§
- Register
Block - Register block
Type Aliases§
- Clkdiv
- CLKDIV (rw) register accessor: clock divider register
- Con
- CON (rw) register accessor: control register
- Fcnt
- FCNT (r) register accessor: finished count
- Ien
- IEN (rw) register accessor: interrupt enable register
- Ipd
- IPD (rw) register accessor: interrupt pending register
- Mrxaddr
- MRXADDR (rw) register accessor: the slave address accessed for master rx mode
- Mrxcnt
- MRXCNT (rw) register accessor: master rx count
- Mrxraddr
- MRXRADDR (rw) register accessor: the slave register address accessed for master rx mode
- Mtxcnt
- MTXCNT (rw) register accessor: master transmit count
- Rxdata0
- RXDATA0 (r) register accessor: I2C rx data register 0
- Rxdata1
- RXDATA1 (r) register accessor: I2C rx data register 1
- Rxdata2
- RXDATA2 (r) register accessor: I2C rx data register 2
- Rxdata3
- RXDATA3 (r) register accessor: I2C rx data register 3
- Rxdata4
- RXDATA4 (r) register accessor: I2C rx data register 4
- Rxdata5
- RXDATA5 (r) register accessor: I2C rx data register 5
- Rxdata6
- RXDATA6 (r) register accessor: I2C rx data register 6
- Rxdata7
- RXDATA7 (r) register accessor: I2C rx data register 7
- SclOeDb
- SCL_OE_DB (rw) register accessor: slave hold debounce configure register
- St
- ST (r) register accessor: status debug register
- Txdata0
- TXDATA0 (rw) register accessor: I2C tx data register 0
- Txdata1
- TXDATA1 (rw) register accessor: I2C tx data register 1
- Txdata2
- TXDATA2 (rw) register accessor: I2C tx data register 2
- Txdata3
- TXDATA3 (rw) register accessor: I2C tx data register 3
- Txdata4
- TXDATA4 (rw) register accessor: I2C tx data register 4
- Txdata5
- TXDATA5 (rw) register accessor: I2C tx data register 5
- Txdata6
- TXDATA6 (rw) register accessor: I2C tx data register 6
- Txdata7
- TXDATA7 (rw) register accessor: I2C tx data register 7