Module rk3399_pac::i2s
source · Expand description
Inter-IC Sound (I2S) Registers
Modules§
- clock generation register
- SCLK domain logic clear Register
- DMA control register
- interrupt control register
- interrupt status register
- receive operation control register
- Receive FIFO Data Register
- RX FIFO level register
- transmit operation control register
- Transmit FIFO Data Register
- TX FIFO level register
- Transfer Start Register
Structs§
- Register block
Type Aliases§
- CKR (rw) register accessor: clock generation register
- CLR (rw) register accessor: SCLK domain logic clear Register
- DMACR (rw) register accessor: DMA control register
- INTCR (rw) register accessor: interrupt control register
- INTSR (r) register accessor: interrupt status register
- RXCR (rw) register accessor: receive operation control register
- RXDR (r) register accessor: Receive FIFO Data Register
- RXFIFOLR (r) register accessor: RX FIFO level register
- TXCR (rw) register accessor: transmit operation control register
- TXDR (w) register accessor: Transmit FIFO Data Register
- TXFIFOLR (r) register accessor: TX FIFO level register
- XFER (rw) register accessor: Transfer Start Register