1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 ppll_con0: PpllCon0,
5 ppll_con1: PpllCon1,
6 ppll_con2: PpllCon2,
7 ppll_con3: PpllCon3,
8 ppll_con4: PpllCon4,
9 ppll_con5: PpllCon5,
10 _reserved6: [u8; 0x68],
11 clksel_con0: ClkselCon0,
12 clksel_con1: ClkselCon1,
13 clksel_con2: ClkselCon2,
14 clksel_con3: ClkselCon3,
15 clksel_con4: ClkselCon4,
16 clksel_con5: ClkselCon5,
17 clkfrac_con0: ClkfracCon0,
18 clkfrac_con1: ClkfracCon1,
19 _reserved14: [u8; 0x60],
20 clkgate_con0: ClkgateCon0,
21 clkgate_con1: ClkgateCon1,
22 clkgate_con2: ClkgateCon2,
23 _reserved17: [u8; 0x04],
24 softrst_con0: SoftrstCon0,
25 softrst_con1: SoftrstCon1,
26 _reserved19: [u8; 0x08],
27 rstnhold_con0: RstnholdCon0,
28 rstnhold_con1: RstnholdCon1,
29 _reserved21: [u8; 0x08],
30 gatedis_con0: GatedisCon0,
31}
32impl RegisterBlock {
33 #[doc = "0x00 - PPLL configuration register0"]
34 #[inline(always)]
35 pub const fn ppll_con0(&self) -> &PpllCon0 {
36 &self.ppll_con0
37 }
38 #[doc = "0x04 - PPLL configuration register1"]
39 #[inline(always)]
40 pub const fn ppll_con1(&self) -> &PpllCon1 {
41 &self.ppll_con1
42 }
43 #[doc = "0x08 - PPLL configuration register2"]
44 #[inline(always)]
45 pub const fn ppll_con2(&self) -> &PpllCon2 {
46 &self.ppll_con2
47 }
48 #[doc = "0x0c - PPLL configuration register3"]
49 #[inline(always)]
50 pub const fn ppll_con3(&self) -> &PpllCon3 {
51 &self.ppll_con3
52 }
53 #[doc = "0x10 - PPLL configuration register4"]
54 #[inline(always)]
55 pub const fn ppll_con4(&self) -> &PpllCon4 {
56 &self.ppll_con4
57 }
58 #[doc = "0x14 - PPLL configuration register5"]
59 #[inline(always)]
60 pub const fn ppll_con5(&self) -> &PpllCon5 {
61 &self.ppll_con5
62 }
63 #[doc = "0x80 - Internal clock select and divide register0"]
64 #[inline(always)]
65 pub const fn clksel_con0(&self) -> &ClkselCon0 {
66 &self.clksel_con0
67 }
68 #[doc = "0x84 - Internal clock select and divide register1"]
69 #[inline(always)]
70 pub const fn clksel_con1(&self) -> &ClkselCon1 {
71 &self.clksel_con1
72 }
73 #[doc = "0x88 - Internal clock select and divide register2"]
74 #[inline(always)]
75 pub const fn clksel_con2(&self) -> &ClkselCon2 {
76 &self.clksel_con2
77 }
78 #[doc = "0x8c - Internal clock select and divide register3"]
79 #[inline(always)]
80 pub const fn clksel_con3(&self) -> &ClkselCon3 {
81 &self.clksel_con3
82 }
83 #[doc = "0x90 - Internal clock select and divide register4"]
84 #[inline(always)]
85 pub const fn clksel_con4(&self) -> &ClkselCon4 {
86 &self.clksel_con4
87 }
88 #[doc = "0x94 - Internal clock select and divide register5"]
89 #[inline(always)]
90 pub const fn clksel_con5(&self) -> &ClkselCon5 {
91 &self.clksel_con5
92 }
93 #[doc = "0x98 - Internal clock select and divide register6"]
94 #[inline(always)]
95 pub const fn clkfrac_con0(&self) -> &ClkfracCon0 {
96 &self.clkfrac_con0
97 }
98 #[doc = "0x9c - Internal clock select and divide register7"]
99 #[inline(always)]
100 pub const fn clkfrac_con1(&self) -> &ClkfracCon1 {
101 &self.clkfrac_con1
102 }
103 #[doc = "0x100 - Internal clock gating register0"]
104 #[inline(always)]
105 pub const fn clkgate_con0(&self) -> &ClkgateCon0 {
106 &self.clkgate_con0
107 }
108 #[doc = "0x104 - Internal clock gating register1"]
109 #[inline(always)]
110 pub const fn clkgate_con1(&self) -> &ClkgateCon1 {
111 &self.clkgate_con1
112 }
113 #[doc = "0x108 - Internal clock gating register2"]
114 #[inline(always)]
115 pub const fn clkgate_con2(&self) -> &ClkgateCon2 {
116 &self.clkgate_con2
117 }
118 #[doc = "0x110 - Internal software reset control register0"]
119 #[inline(always)]
120 pub const fn softrst_con0(&self) -> &SoftrstCon0 {
121 &self.softrst_con0
122 }
123 #[doc = "0x114 - Internal software reset control register1"]
124 #[inline(always)]
125 pub const fn softrst_con1(&self) -> &SoftrstCon1 {
126 &self.softrst_con1
127 }
128 #[doc = "0x120 - Internal reset hold control register0"]
129 #[inline(always)]
130 pub const fn rstnhold_con0(&self) -> &RstnholdCon0 {
131 &self.rstnhold_con0
132 }
133 #[doc = "0x124 - Internal reset hold control register1"]
134 #[inline(always)]
135 pub const fn rstnhold_con1(&self) -> &RstnholdCon1 {
136 &self.rstnhold_con1
137 }
138 #[doc = "0x130 - Internal gate disable control register0"]
139 #[inline(always)]
140 pub const fn gatedis_con0(&self) -> &GatedisCon0 {
141 &self.gatedis_con0
142 }
143}
144#[doc = "PPLL_CON0 (rw) register accessor: PPLL configuration register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con0`]
145module"]
146#[doc(alias = "PPLL_CON0")]
147pub type PpllCon0 = crate::Reg<ppll_con0::PpllCon0Spec>;
148#[doc = "PPLL configuration register0"]
149pub mod ppll_con0;
150#[doc = "PPLL_CON1 (rw) register accessor: PPLL configuration register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con1`]
151module"]
152#[doc(alias = "PPLL_CON1")]
153pub type PpllCon1 = crate::Reg<ppll_con1::PpllCon1Spec>;
154#[doc = "PPLL configuration register1"]
155pub mod ppll_con1;
156#[doc = "PPLL_CON2 (rw) register accessor: PPLL configuration register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con2`]
157module"]
158#[doc(alias = "PPLL_CON2")]
159pub type PpllCon2 = crate::Reg<ppll_con2::PpllCon2Spec>;
160#[doc = "PPLL configuration register2"]
161pub mod ppll_con2;
162#[doc = "PPLL_CON3 (rw) register accessor: PPLL configuration register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con3`]
163module"]
164#[doc(alias = "PPLL_CON3")]
165pub type PpllCon3 = crate::Reg<ppll_con3::PpllCon3Spec>;
166#[doc = "PPLL configuration register3"]
167pub mod ppll_con3;
168#[doc = "PPLL_CON4 (rw) register accessor: PPLL configuration register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con4`]
169module"]
170#[doc(alias = "PPLL_CON4")]
171pub type PpllCon4 = crate::Reg<ppll_con4::PpllCon4Spec>;
172#[doc = "PPLL configuration register4"]
173pub mod ppll_con4;
174#[doc = "PPLL_CON5 (rw) register accessor: PPLL configuration register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppll_con5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppll_con5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppll_con5`]
175module"]
176#[doc(alias = "PPLL_CON5")]
177pub type PpllCon5 = crate::Reg<ppll_con5::PpllCon5Spec>;
178#[doc = "PPLL configuration register5"]
179pub mod ppll_con5;
180#[doc = "CLKSEL_CON0 (rw) register accessor: Internal clock select and divide register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con0`]
181module"]
182#[doc(alias = "CLKSEL_CON0")]
183pub type ClkselCon0 = crate::Reg<clksel_con0::ClkselCon0Spec>;
184#[doc = "Internal clock select and divide register0"]
185pub mod clksel_con0;
186#[doc = "CLKSEL_CON1 (rw) register accessor: Internal clock select and divide register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con1`]
187module"]
188#[doc(alias = "CLKSEL_CON1")]
189pub type ClkselCon1 = crate::Reg<clksel_con1::ClkselCon1Spec>;
190#[doc = "Internal clock select and divide register1"]
191pub mod clksel_con1;
192#[doc = "CLKSEL_CON2 (rw) register accessor: Internal clock select and divide register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con2`]
193module"]
194#[doc(alias = "CLKSEL_CON2")]
195pub type ClkselCon2 = crate::Reg<clksel_con2::ClkselCon2Spec>;
196#[doc = "Internal clock select and divide register2"]
197pub mod clksel_con2;
198#[doc = "CLKSEL_CON3 (rw) register accessor: Internal clock select and divide register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con3`]
199module"]
200#[doc(alias = "CLKSEL_CON3")]
201pub type ClkselCon3 = crate::Reg<clksel_con3::ClkselCon3Spec>;
202#[doc = "Internal clock select and divide register3"]
203pub mod clksel_con3;
204#[doc = "CLKSEL_CON4 (rw) register accessor: Internal clock select and divide register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con4`]
205module"]
206#[doc(alias = "CLKSEL_CON4")]
207pub type ClkselCon4 = crate::Reg<clksel_con4::ClkselCon4Spec>;
208#[doc = "Internal clock select and divide register4"]
209pub mod clksel_con4;
210#[doc = "CLKSEL_CON5 (rw) register accessor: Internal clock select and divide register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel_con5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel_con5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel_con5`]
211module"]
212#[doc(alias = "CLKSEL_CON5")]
213pub type ClkselCon5 = crate::Reg<clksel_con5::ClkselCon5Spec>;
214#[doc = "Internal clock select and divide register5"]
215pub mod clksel_con5;
216#[doc = "CLKFRAC_CON0 (rw) register accessor: Internal clock select and divide register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkfrac_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkfrac_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkfrac_con0`]
217module"]
218#[doc(alias = "CLKFRAC_CON0")]
219pub type ClkfracCon0 = crate::Reg<clkfrac_con0::ClkfracCon0Spec>;
220#[doc = "Internal clock select and divide register6"]
221pub mod clkfrac_con0;
222#[doc = "CLKFRAC_CON1 (rw) register accessor: Internal clock select and divide register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkfrac_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkfrac_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkfrac_con1`]
223module"]
224#[doc(alias = "CLKFRAC_CON1")]
225pub type ClkfracCon1 = crate::Reg<clkfrac_con1::ClkfracCon1Spec>;
226#[doc = "Internal clock select and divide register7"]
227pub mod clkfrac_con1;
228#[doc = "CLKGATE_CON0 (rw) register accessor: Internal clock gating register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkgate_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkgate_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkgate_con0`]
229module"]
230#[doc(alias = "CLKGATE_CON0")]
231pub type ClkgateCon0 = crate::Reg<clkgate_con0::ClkgateCon0Spec>;
232#[doc = "Internal clock gating register0"]
233pub mod clkgate_con0;
234#[doc = "CLKGATE_CON1 (rw) register accessor: Internal clock gating register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkgate_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkgate_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkgate_con1`]
235module"]
236#[doc(alias = "CLKGATE_CON1")]
237pub type ClkgateCon1 = crate::Reg<clkgate_con1::ClkgateCon1Spec>;
238#[doc = "Internal clock gating register1"]
239pub mod clkgate_con1;
240#[doc = "CLKGATE_CON2 (rw) register accessor: Internal clock gating register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkgate_con2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkgate_con2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkgate_con2`]
241module"]
242#[doc(alias = "CLKGATE_CON2")]
243pub type ClkgateCon2 = crate::Reg<clkgate_con2::ClkgateCon2Spec>;
244#[doc = "Internal clock gating register2"]
245pub mod clkgate_con2;
246#[doc = "SOFTRST_CON0 (rw) register accessor: Internal software reset control register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softrst_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softrst_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softrst_con0`]
247module"]
248#[doc(alias = "SOFTRST_CON0")]
249pub type SoftrstCon0 = crate::Reg<softrst_con0::SoftrstCon0Spec>;
250#[doc = "Internal software reset control register0"]
251pub mod softrst_con0;
252#[doc = "SOFTRST_CON1 (rw) register accessor: Internal software reset control register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softrst_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softrst_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softrst_con1`]
253module"]
254#[doc(alias = "SOFTRST_CON1")]
255pub type SoftrstCon1 = crate::Reg<softrst_con1::SoftrstCon1Spec>;
256#[doc = "Internal software reset control register1"]
257pub mod softrst_con1;
258#[doc = "RSTNHOLD_CON0 (rw) register accessor: Internal reset hold control register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstnhold_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstnhold_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstnhold_con0`]
259module"]
260#[doc(alias = "RSTNHOLD_CON0")]
261pub type RstnholdCon0 = crate::Reg<rstnhold_con0::RstnholdCon0Spec>;
262#[doc = "Internal reset hold control register0"]
263pub mod rstnhold_con0;
264#[doc = "RSTNHOLD_CON1 (rw) register accessor: Internal reset hold control register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstnhold_con1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstnhold_con1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstnhold_con1`]
265module"]
266#[doc(alias = "RSTNHOLD_CON1")]
267pub type RstnholdCon1 = crate::Reg<rstnhold_con1::RstnholdCon1Spec>;
268#[doc = "Internal reset hold control register1"]
269pub mod rstnhold_con1;
270#[doc = "GATEDIS_CON0 (rw) register accessor: Internal gate disable control register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gatedis_con0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gatedis_con0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gatedis_con0`]
271module"]
272#[doc(alias = "GATEDIS_CON0")]
273pub type GatedisCon0 = crate::Reg<gatedis_con0::GatedisCon0Spec>;
274#[doc = "Internal gate disable control register0"]
275pub mod gatedis_con0;