Crate rk3399_pac 

Peripheral access API for RK3399 microcontrollers (generated using svd2rust v0.32.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

pub use self::crypto as crypto0;

pub use self::crypto as crypto1;

pub use self::ddrc as ddrc0;

pub use self::ddrc as ddrc1;

pub use self::dmac as dmac0;

pub use self::dmac as dmac1;

pub use self::efuse as efuse0;

pub use self::efuse as efuse1;

pub use self::err_logger_msch as err_logger_msch0;

pub use self::err_logger_msch as err_logger_msch1;

pub use self::err_logger_slv as err_logger_slv0;

pub use self::err_logger_slv as err_logger_slv1;

pub use self::gpio as gpio0;

pub use self::gpio as gpio1;

pub use self::gpio as gpio2;

pub use self::gpio as gpio3;

pub use self::gpio as gpio4;

pub use self::i2s as i2s0;

pub use self::i2s as i2s1;

pub use self::i2s as i2s2;

pub use self::isp as isp0;

pub use self::isp as isp1;

pub use self::mailbox as mailbox0;

pub use self::mailbox as mailbox1;

pub use self::mipi_dsi_host as mipi_dsi_host0;

pub use self::mipi_dsi_host as mipi_dsi_host1;

pub use self::mmu as mmu0_isp0;

pub use self::mmu as mmu0_isp1;

pub use self::mmu as mmu1_isp0;

pub use self::mmu as mmu1_isp1;

pub use self::mmu as mmu_hdcp;

pub use self::mmu as mmu_iep;

pub use self::mmu as mmu_rkvdec_r;

pub use self::mmu as mmu_rkvdec_w;

pub use self::mmu as mmu_vopb;

pub use self::mmu as mmu_vopl;

pub use self::mmu as mmu_vpu;

pub use self::msch as msch0;

pub use self::msch as msch1;

pub use self::pref_cache as pref_cache_rkvdec_chroma;

pub use self::pref_cache as pref_cache_rkvdec_luma;

pub use self::pref_cache as pref_cache_vpu;

pub use self::probe as probe_cci_msch0;

pub use self::probe as probe_cci_msch1;

pub use self::probe as probe_gpu_msch0;

pub use self::probe as probe_gpu_msch1;

pub use self::probe as probe_perihp_msch0;

pub use self::probe as probe_perihp_msch1;

pub use self::probe as probe_perilp_msch0;

pub use self::probe as probe_perilp_msch1;

pub use self::probe as probe_video_msch0;

pub use self::probe as probe_video_msch1;

pub use self::probe as probe_vio0_msch0;

pub use self::probe as probe_vio0_msch1;

pub use self::probe as probe_vio1_msch0;

pub use self::probe as probe_vio1_msch1;

pub use self::qos as qos_cci_m0;

pub use self::qos as qos_cci_m1;

pub use self::qos as qos_crypto0;

pub use self::qos as qos_crypto1;

pub use self::qos as qos_dcf;

pub use self::qos as qos_dmac0;

pub use self::qos as qos_dmac1;

pub use self::qos as qos_emmc;

pub use self::qos as qos_gic;

pub use self::qos as qos_gmac;

pub use self::qos as qos_gpu;

pub use self::qos as qos_hdcp;

pub use self::qos as qos_hsic;

pub use self::qos as qos_iep;

pub use self::qos as qos_isp0_m0;

pub use self::qos as qos_isp0_m1;

pub use self::qos as qos_isp1_m0;

pub use self::qos as qos_isp1_m1;

pub use self::qos as qos_pcie;

pub use self::qos as qos_perihp_nsp;

pub use self::qos as qos_perilpslv_nsp;

pub use self::qos as qos_perilp_nsp;

pub use self::qos as qos_peri_cm0;

pub use self::qos as qos_pmu_cm0;

pub use self::qos as qos_rga_r;

pub use self::qos as qos_rga_w;

pub use self::qos as qos_sdio;

pub use self::qos as qos_sdmmc;

pub use self::qos as qos_usb_host0;

pub use self::qos as qos_usb_host1;

pub use self::qos as qos_usb_otg0;

pub use self::qos as qos_usb_otg1;

pub use self::qos as qos_video_m0;

pub use self::qos as qos_video_m1_r;

pub use self::qos as qos_video_m1_w;

pub use self::qos as qos_vop_big_r;

pub use self::qos as qos_vop_big_w;

pub use self::qos as qos_vop_little;

pub use self::rki2c as rki2c0;

pub use self::rki2c as rki2c1;

pub use self::rki2c as rki2c2;

pub use self::rki2c as rki2c3;

pub use self::rki2c as rki2c4;

pub use self::rki2c as rki2c5;

pub use self::rki2c as rki2c6;

pub use self::rki2c as rki2c7;

pub use self::rki2c as rki2c8;

pub use self::spi as spi0;

pub use self::spi as spi1;

pub use self::spi as spi2;

pub use self::spi as spi3;

pub use self::spi as spi4;

pub use self::spi as spi5;

pub use self::timer as timer0;

pub use self::timer as timer1;

pub use self::timer as timer10;

pub use self::timer as timer11;

pub use self::timer as timer2;

pub use self::timer as timer3;

pub use self::timer as timer4;

pub use self::timer as timer5;

pub use self::timer as timer6;

pub use self::timer as timer7;

pub use self::timer as timer8;

pub use self::timer as timer9;

pub use self::timer as pmutimer0;

pub use self::timer as pmutimer1;

pub use self::timer as stimer0;

pub use self::timer as stimer1;

pub use self::timer as stimer10;

pub use self::timer as stimer11;

pub use self::timer as stimer2;

pub use self::timer as stimer3;

pub use self::timer as stimer4;

pub use self::timer as stimer5;

pub use self::timer as stimer6;

pub use self::timer as stimer7;

pub use self::timer as stimer8;

pub use self::timer as stimer9;

pub use self::typec_pd as typec_pd0;

pub use self::typec_pd as typec_pd1;

pub use self::typec_phy as typec_phy0;

pub use self::typec_phy as typec_phy1;

pub use self::uart as uart0;

pub use self::uart as uart1;

pub use self::uart as uart2;

pub use self::uart as uart3;

pub use self::uart as uart4;

pub use self::usb3 as usb3_otg0;

pub use self::usb3 as usb3_otg1;

pub use self::wdt as wdt0;

pub use self::wdt as wdt1;

pub use self::wdt as wdt2;

Modules

cci500

Cache Coherent Interconnect 500 (CCI500) Registers

cru

Clock and Reset Unit (CRU) Registers

crypto

Crypto Registers

dcf

DDR Converser of Frequency (DCF) Registers

ddr_cic

DDR Controller Interface Control Registers (DDR_CIC) Registers

ddr_mon

DDR Monitor (DDR_MON) Registers

ddrc

DDR Controller (DDRC) Registers

dmac

DMA Controller (DMAC) Registers

dp

DisplayPort Registers

efuse

eFuse Registers

emmccore

eMMC Controller (EMMCCORE) Registers

err_logger_msch

Error Logger (ERR_LOGGER) Registers for the paths from all masters to the memory schedule

err_logger_slv

Error Logger (ERR_LOGGER) Registers for the paths from all masters except the PMU of the Cortex-M0 to all slaves outside the PMU power domain

generic

Common register and bit access and modify traits

gmac

Gigabit Media Access Controller (GMAC) Registers

gpio

General Purpose Input/Output (GPIO) Registers

grf

General Register File (GRF) Registers

hdmi

HDMI Registers

i2s

Inter-IC Sound (I2S) Registers

iep

Image Enhancement Processor (IEP) Registers

isp

Image Signal Processor (ISP) Registers

mailbox

Mailbox Registers

mipi_dsi_host

MIPI Display Serial Interface (DSI) Host Registers

mmu

Memory Management Unit (MMU) Registers

msch

Memory Schedule (MSCH) Registers

pcie_client

PCIe Client Registers

pcie_core

PCIe Core Registers

pmu

Power Management Unit (PMU) Registers

pmucru

Power Management Unit Clock and Reset Unit (PMUCRU) Registers

pmugrf

Power Management Unit General Register File (PMUGRF) Registers

pref_cache

VPU Prefetch Cache Registers

probe

Probe Registers

pwm

Pulse Width Modulation (PWM) Registers

qos

Quality of Service (QOS) Registers

rga2

Rockchip Graphics Accelerator 2 (RGA2) Registers

rki2c

Rockchip Inter-Integrated Circuit (RKI2C) Registers

rkvdec

Rockchip Video Decoder (RKVDEC) Registers

saradc

Successive Approximation Register Analog-to-Digital Converter (SARADC) Registers

sdmmc

Secure Digital MultiMedia Card (SDMMC) Registers

spdif

Sony/Philips Digital Interface (SPDIF) Registers

spi

Serial Peripheral Interface (SPI) Registers

timer

Timer Registers

tsadc

Temperature Sensor Analog-to-Digital Converter (TSADC) Registers

typec_pd

Type-C Power Delivery (TYPEC_PD) Registers

typec_phy

Type-C PHY Registers

uart

Universal Asynchronous Receiver/Transmitter (UART) Registers

usb3

USB 3.0/2.0 OTG (USB3) Registers

vdpu

Video Processor Unit (VPU) Decoder Registers

vepu

Video Processor Unit (VPU) Encoder Registers

vopb

Visual Output Processor (Big) (VOPB) Registers

vopl

Visual Output Processor (Little) (VOPL) Registers

wdt

Watchdog Timer (WDT) Registers

Structs

Cci500

Cache Coherent Interconnect 500 (CCI500) Registers

Cru

Clock and Reset Unit (CRU) Registers

Crypto

Crypto Registers

Crypto0

Crypto 0 Registers

Crypto1

Crypto 1 Registers

Dcf

DDR Converser of Frequency (DCF) Registers

DdrCic

DDR Controller Interface Control Registers (DDR_CIC) Registers

DdrMon

DDR Monitor (DDR_MON) Registers

Ddrc

DDR Controller (DDRC) Registers

Ddrc0

DDR Controller 0 (DDRC0) Registers

Ddrc1

DDR Controller 1 (DDRC1) Registers

Dmac

DMA Controller (DMAC) Registers

Dmac0

DMA Controller 0 Registers

Dmac1

DMA Controller 1 Registers

Dp

DisplayPort Registers

Efuse

eFuse Registers

Efuse0

eFuse 0 Registers

Efuse1

eFuse 1 Registers

Emmccore

eMMC Controller (EMMCCORE) Registers

ErrLoggerMsch

Error Logger (ERR_LOGGER) Registers for the paths from all masters to the memory schedule

ErrLoggerMsch0

Error Logger (ERR_LOGGER) Registers for the paths from all masters to the memory schedule 0

ErrLoggerMsch1

Error Logger (ERR_LOGGER) Registers for the paths from all masters to the memory schedule 1

ErrLoggerSlv

Error Logger (ERR_LOGGER) Registers for the paths from all masters except the PMU of the Cortex-M0 to all slaves outside the PMU power domain

ErrLoggerSlv0

Error Logger (ERR_LOGGER) Registers for the paths from all masters except the PMU of the Cortex-M0 to all slaves outside the PMU power domain

ErrLoggerSlv1

Error Logger (ERR_LOGGER) Registers for the paths from the PMU of the Cortex-M0 to all slaves inside the PMU power domain

Gmac

Gigabit Media Access Controller (GMAC) Registers

Gpio

General Purpose Input/Output (GPIO) Registers

Gpio0

General Purpose Input/Output (GPIO) 0 Registers

Gpio1

General Purpose Input/Output (GPIO) 1 Registers

Gpio2

General Purpose Input/Output (GPIO) 2 Registers

Gpio3

General Purpose Input/Output (GPIO) 3 Registers

Gpio4

General Purpose Input/Output (GPIO) 4 Registers

Grf

General Register File (GRF) Registers

Hdmi

HDMI Registers

I2s

Inter-IC Sound (I2S) Registers

I2s0

Inter-IC Sound (I2S) 0 Registers

I2s1

Inter-IC Sound (I2S) 1 Registers

I2s2

Inter-IC Sound (I2S) 2 Registers

Iep

Image Enhancement Processor (IEP) Registers

Isp

Image Signal Processor (ISP) Registers

Isp0

Image Signal Processor 0 (ISP0) Registers

Isp1

Image Signal Processor 1 (ISP1) Registers

Mailbox

Mailbox Registers

Mailbox0

Mailbox 0 Registers

Mailbox1

Mailbox 1 Registers

MipiDsiHost

MIPI Display Serial Interface (DSI) Host Registers

MipiDsiHost0

MIPI Display Serial Interface (DSI) Host 0 Registers

MipiDsiHost1

MIPI Display Serial Interface (DSI) Host 1 Registers

Mmu

Memory Management Unit (MMU) Registers

Mmu0Isp0

Registers of Memory Management Unit 0 (MMU0) for Image Signal Processor 0 (ISP0)

Mmu0Isp1

Registers of Memory Management Unit 0 (MMU0) for Image Signal Processor 1 (ISP1)

Mmu1Isp0

Registers of Memory Management Unit 1 (MMU1) for Image Signal Processor 0 (ISP0)

Mmu1Isp1

Registers of Memory Management Unit 1 (MMU1) for Image Signal Processor 1 (ISP1)

MmuHdcp

Registers of Memory Management Unit (MMU) for High-bandwidth Digital Content Protection (HDCP)

MmuIep

Registers of Memory Management Unit (MMU) for Image Enhancement Processor (IEP)

MmuRkvdecR

Registers of Memory Management Unit (MMU) for Rockchip Video Decoder (RKVDEC) Read

MmuRkvdecW

Registers of Memory Management Unit (MMU) for Rockchip Video Decoder (RKVDEC) Write

MmuVopb

Registers of Memory Management Unit (MMU) for Visual Output Processor (Big) (VOPB)

MmuVopl

Registers of Memory Management Unit (MMU) for Visual Output Processor (Little) (VOPL)

MmuVpu

Registers of Memory Management Unit (MMU) for Video Processing Unit (VPU)

Msch

Memory Schedule (MSCH) Registers

Msch0

Memory Schedule (MSCH) 0 Registers

Msch1

Memory Schedule (MSCH) 1 Registers

PcieClient

PCIe Client Registers

PcieCore

PCIe Core Registers

Peripherals

All the peripherals.

Pmu

Power Management Unit (PMU) Registers

Pmucru

Power Management Unit Clock and Reset Unit (PMUCRU) Registers

Pmugrf

Power Management Unit General Register File (PMUGRF) Registers

Pmutimer0

Power Management Unit Timer 0 Registers

Pmutimer1

Power Management Unit Timer 1 Registers

PrefCache

VPU Prefetch Cache Registers

PrefCacheRkvdecChroma

RKVDEC Chroma Prefetch Cache Control Registers

PrefCacheRkvdecLuma

RKVDEC Luma Prefetch Cache Control Registers

PrefCacheVpu

VPU Prefetch Cache Control Registers

Probe

Probe Registers

ProbeCciMsch0

Registers for the probe covering paths from the CCI_M1 to the memory schedule 0

ProbeCciMsch1

Registers for the probe covering paths from the CCI_M1 to the memory schedule 1

ProbeGpuMsch0

Registers for the probe covering paths from the GPU to the memory schedule 0

ProbeGpuMsch1

Registers for the probe covering paths from the GPU to the memory schedule 1

ProbePerihpMsch0

Registers for the probe covering paths from the perihp master NIU to the memory schedule 0

ProbePerihpMsch1

Registers for the probe covering paths from the perihp master NIU to the memory schedule 1

ProbePerilpMsch0

Registers for the probe covering paths from the perilp master NIU, debug and CCI_M0 to the memory schedule 0

ProbePerilpMsch1

Registers for the probe covering paths from the perilp master NIU, debug and CCI_M0 to the memory schedule 1

ProbeVideoMsch0

Registers for the probe covering paths from video to the memory schedule 0

ProbeVideoMsch1

Registers for the probe covering paths from video to the memory schedule 1

ProbeVio0Msch0

Registers for the probe covering paths from the IEP, ISP0 and VOP-BIG to the memory schedule 0

ProbeVio0Msch1

Registers for the probe covering paths from the IEP, ISP0 and VOP-BIG to the memory schedule 1

ProbeVio1Msch0

Registers for the probe covering paths from the RGA, ISP1, VOP-LITTLE and HDCP to the memory schedule 0

ProbeVio1Msch1

Registers for the probe covering paths from the RGA, ISP1, VOP-LITTLE and HDCP to the memory schedule 1

Pwm

Pulse Width Modulation (PWM) Registers

Qos

Quality of Service (QOS) Registers

QosCciM0

QoS Registers for CCI_M0

QosCciM1

QoS Registers for CCI_M1

QosCrypto0

QoS Registers for CRYPTO0

QosCrypto1

QoS Registers for CRYPTO1

QosDcf

QoS Registers for DCF

QosDmac0

QoS Registers for DMAC0

QosDmac1

QoS Registers for DMAC1

QosEmmc

QoS Registers for EMMC

QosGic

QoS Registers for GIC

QosGmac

QoS Registers for GMAC

QosGpu

QoS Registers for GPU

QosHdcp

QoS Registers for HDCP

QosHsic

QoS Registers for HSIC

QosIep

QoS Registers for IEP

QosIsp0M0

QoS Registers for ISP0_M0

QosIsp0M1

QoS Registers for ISP0_M1

QosIsp1M0

QoS Registers for ISP1_M0

QosIsp1M1

QoS Registers for ISP1_M1

QosPcie

QoS Registers for PCIE

QosPeriCm0

QoS Registers for PERI_CM0

QosPerihpNsp

QoS Registers for PERIHP_NSP

QosPerilpNsp

QoS Registers for PERILP_NSP

QosPerilpslvNsp

QoS Registers for PERILPSLV_NSP

QosPmuCm0

QoS Registers for PMU_CM0

QosRgaR

QoS Registers for RGA_R

QosRgaW

QoS Registers for RGA_W

QosSdio

QoS Registers for SDIO

QosSdmmc

QoS Registers for SDMMC

QosUsbHost0

QoS Registers for USB_HOST0

QosUsbHost1

QoS Registers for USB_HOST1

QosUsbOtg0

QoS Registers for USB_OTG0

QosUsbOtg1

QoS Registers for USB_OTG1

QosVideoM0

QoS Registers for VIDEO_M0

QosVideoM1R

QoS Registers for VIDEO_M1_R

QosVideoM1W

QoS Registers for VIDEO_M1_W

QosVopBigR

QoS Registers for VOP-BIG_R

QosVopBigW

QoS Registers for VOP-BIG_W

QosVopLittle

QoS Registers for VOP-LITTLE

Rga2

Rockchip Graphics Accelerator 2 (RGA2) Registers

Rki2c

Rockchip Inter-Integrated Circuit (RKI2C) Registers

Rki2c0

Rockchip Inter-Integrated Circuit (RKI2C) 0 Registers

Rki2c1

Rockchip Inter-Integrated Circuit (RKI2C) 1 Registers

Rki2c2

Rockchip Inter-Integrated Circuit (RKI2C) 2 Registers

Rki2c3

Rockchip Inter-Integrated Circuit (RKI2C) 3 Registers

Rki2c4

Rockchip Inter-Integrated Circuit (RKI2C) 4 Registers

Rki2c5

Rockchip Inter-Integrated Circuit (RKI2C) 5 Registers

Rki2c6

Rockchip Inter-Integrated Circuit (RKI2C) 6 Registers

Rki2c7

Rockchip Inter-Integrated Circuit (RKI2C) 7 Registers

Rki2c8

Rockchip Inter-Integrated Circuit (RKI2C) 8 Registers

Rkvdec

Rockchip Video Decoder (RKVDEC) Registers

Saradc

Successive Approximation Register Analog-to-Digital Converter (SARADC) Registers

Sdmmc

Secure Digital MultiMedia Card (SDMMC) Registers

Spdif

Sony/Philips Digital Interface (SPDIF) Registers

Spi

Serial Peripheral Interface (SPI) Registers

Spi0

Serial Peripheral Interface (SPI) 0 Registers

Spi1

Serial Peripheral Interface (SPI) 1 Registers

Spi2

Serial Peripheral Interface (SPI) 2 Registers

Spi3

Serial Peripheral Interface (SPI) 3 Registers

Spi4

Serial Peripheral Interface (SPI) 4 Registers

Spi5

Serial Peripheral Interface (SPI) 5 Registers

Stimer0

Secure Timer 0 Registers

Stimer1

Secure Timer 1 Registers

Stimer2

Secure Timer 2 Registers

Stimer3

Secure Timer 3 Registers

Stimer4

Secure Timer 4 Registers

Stimer5

Secure Timer 5 Registers

Stimer6

Secure Timer 6 Registers

Stimer7

Secure Timer 7 Registers

Stimer8

Secure Timer 8 Registers

Stimer9

Secure Timer 9 Registers

Stimer10

Secure Timer 10 Registers

Stimer11

Secure Timer 11 Registers

Timer

Timer Registers

Timer0

Timer 0 Registers

Timer1

Timer 1 Registers

Timer2

Timer 2 Registers

Timer3

Timer 3 Registers

Timer4

Timer 4 Registers

Timer5

Timer 5 Registers

Timer6

Timer 6 Registers

Timer7

Timer 7 Registers

Timer8

Timer 8 Registers

Timer9

Timer 9 Registers

Timer10

Timer 10 Registers

Timer11

Timer 11 Registers

Tsadc

Temperature Sensor Analog-to-Digital Converter (TSADC) Registers

TypecPd

Type-C Power Delivery (TYPEC_PD) Registers

TypecPd0

Type-C Power Delivery (TYPEC_PD) 0 Registers

TypecPd1

Type-C Power Delivery (TYPEC_PD) 1 Registers

TypecPhy

Type-C PHY Registers

TypecPhy0

Type-C PHY 0 Registers

TypecPhy1

Type-C PHY 1 Registers

Uart

Universal Asynchronous Receiver/Transmitter (UART) Registers

Uart0

Universal Asynchronous Receiver/Transmitter 0 (UART0) Registers

Uart1

Universal Asynchronous Receiver/Transmitter 1 (UART1) Registers

Uart2

Universal Asynchronous Receiver/Transmitter 2 (UART2) Registers

Uart3

Universal Asynchronous Receiver/Transmitter 3 (UART3) Registers

Uart4

Universal Asynchronous Receiver/Transmitter 4 (UART4) Registers

Usb3

USB 3.0/2.0 OTG (USB3) Registers

Usb3Otg0

USB 3.0/2.0 OTG Register 0 (USB3_OTG0) Registers

Usb3Otg1

USB 3.0/2.0 OTG Register 1 (USB3_OTG1) Registers

Vdpu

Video Processor Unit (VPU) Decoder Registers

Vepu

Video Processor Unit (VPU) Encoder Registers

Vopb

Visual Output Processor (Big) (VOPB) Registers

Vopl

Visual Output Processor (Little) (VOPL) Registers

Wdt

Watchdog Timer (WDT) Registers

Wdt0

Watchdog Timer (WDT) 0 Registers

Wdt1

Watchdog Timer (WDT) 1 Registers

Wdt2

Watchdog Timer (WDT) 2 Registers

Enums

Interrupt

Enumeration of all the interrupts.

Constants

NVIC_PRIO_BITS

Number available in the NVIC for configuring priority