riscv/register/
mideleg.rs

1//! mideleg register
2
3read_write_csr! {
4    /// `mideleg` register
5    Mideleg: 0x303,
6    mask: 0x222,
7}
8
9read_write_csr_field! {
10    Mideleg,
11    /// Supervisor Software Interrupt Delegate
12    ssoft: 1,
13}
14
15read_write_csr_field! {
16    Mideleg,
17    /// Supervisor Timer Interrupt Delegate
18    stimer: 5,
19}
20
21read_write_csr_field! {
22    Mideleg,
23    /// Supervisor External Interrupt Delegate
24    sext: 9,
25}
26
27set!(0x303);
28clear!(0x303);
29
30set_clear_csr!(
31    /// Supervisor Software Interrupt Delegate
32    , set_ssoft, clear_ssoft, 1 << 1);
33set_clear_csr!(
34    /// Supervisor Timer Interrupt Delegate
35    , set_stimer, clear_stimer, 1 << 5);
36set_clear_csr!(
37    /// Supervisor External Interrupt Delegate
38    , set_sext, clear_sext, 1 << 9);
39
40#[cfg(test)]
41mod tests {
42    use super::*;
43
44    #[test]
45    fn test_mideleg() {
46        let mut m = Mideleg::from_bits(0);
47
48        test_csr_field!(m, ssoft);
49        test_csr_field!(m, stimer);
50        test_csr_field!(m, sext);
51    }
52}
riscv/register/mideleg.rs

riscv/register/
mideleg.rs
