riscv_isa/
lib.rs

1// Copyright James Wainwright
2//
3// SPDX-License-Identifier: MPL-2.0
4
5//! RISC-V instruction set architecture library.
6//!
7//! Supports decoding RV32 and RV64 from the following specs and extensions:
8//!
9//! * `I`, `M`, `A`, `F`, `D`, `Q`, `C`, `B`
10//! * `Zicsr`, `Zifencei`
11//! * `Zawrs`
12//! * `Zfh`
13//! * `Zba`, `Zbb`, `Zbs`, `Zbkb`, `Zbc`
14//!
15//! # Example
16//!
17//! ```rust
18//! use std::str::FromStr;
19//! use riscv_isa::{Decoder, Instruction, Target};
20//!
21//! let target = Target::from_str("RV32IMACZifencei_Zicsr").unwrap();
22//! let instructions = [
23//!     0x83, 0xa2, 0xad, 0x00, // lw x5, 10(x27)
24//!     0x33, 0x82, 0x78, 0x03, // mul x4, x17, x23
25//! ];
26//!
27//! let mut decoder = Decoder::from_le_bytes(target, &instructions[..]);
28//!
29//! assert_eq!(decoder.next(), Some(Instruction::LW { rd: 5, rs1: 27, offset: 10 }));
30//! assert_eq!(decoder.next(), Some(Instruction::MUL { rd: 4, rs1: 17, rs2: 23 }));
31//! assert_eq!(decoder.next(), None);
32//! ```
33
34mod asm;
35mod csr;
36mod decode;
37mod instruction;
38mod target;
39
40pub use csr::Csr;
41pub use decode::compressed::decode as decode_compressed;
42pub use decode::full::decode as decode_full;
43pub use decode::{decode_le_bytes, Decoder};
44pub use instruction::{Compressed, Instruction};
45pub use target::{Target, Xlen};
46
47/// Privilege mode, e.g. `User` or `Machine`.
48///
49/// Privileges can be compared, for example:
50///
51/// ```rust
52/// # use riscv_isa::Privilege;
53/// assert!(Privilege::User < Privilege::Machine);
54/// ```
55#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
56pub enum Privilege {
57    User,
58    Supervisor,
59    Hypervisor,
60    Machine,
61    Debug,
62}
riscv_isa/lib.rs

riscv_isa/
lib.rs
